fix automatic test signal generation

diff --git a/code/fee_signals.vhd b/code/fee_signals.vhd
index d62bfa6b52a0e7103e83d2cfe5119220a39daa6f..14e2f29d1c723d03bff55b8b11b3f3d72e1fbe4d 100644 (file)
--- a/code/fee_signals.vhd
+++ b/code/fee_signals.vhd
@@ -130,9 +130,8 @@ PROC_TESTSIG : process begin
   wait until rising_edge(CLK);
   if start = '1' then
     timer <= unsigned(timer_reg);
-    TEST_SIG_OUT <= not invert_reg;
-  end if;
-  if timer > 0 then
+    TEST_SIG_OUT <= (invert_reg xor select_reg);
+  elsif timer > 0 then
     timer <= timer - 1 ;
   else
     TEST_SIG_OUT <= invert_reg;