\end{table}
\begin{description}
- \item[Data Buffer Status] The registers 0x7100 to 0x710F give status information about each of the data buffers. The exact amount of available registers depends on the number of data interfaces set in the entities generics. The bits inside each register are defined as shown in table \ref{endpointbufferstatus}. The status of the fifo holding the length of each event in each buffer is only briefly shown. Normally, the state machine forces the fill level of all length fifos and the LVL1 header fifo to be equal.
- \item[LVL1 Buffer Status] The register 0x7110 gives status information about the LVL1 header buffer. The bit definition is the same as for register 0x7100 given in table \ref{endpointbufferstatus}. Here, the bits referring to the length buffers are not defined and will always read as 0.
+ \item[0x7100 - 0x710F: Data Buffer Status] The registers 0x7100 to 0x710F give status information about each of the data buffers. The exact amount of available registers depends on the number of data interfaces set in the entities generics. The bits inside each register are defined as shown in table \ref{endpointbufferstatus}. The status of the fifo holding the length of each event in each buffer is only briefly shown. Normally, the state machine forces the fill level of all length fifos and the LVL1 header fifo to be equal.
+ \item[0x7110: LVL1 Buffer Status] The register 0x7110 gives status information about the LVL1 header buffer. The bit definition is the same as for register 0x7100 given in table \ref{endpointbufferstatus}. Here, the bits referring to the length buffers are not defined and will always read as 0.
+ \item[0x7200: LVL1 release status] One bit for each data channel. The bit is 0 when the readout is idle or data is collected. It changes to 1 when the \portname{Fee\_Trigger\_Release} signal of this data channel has been set. The falling edge follows the global trigger release of the endpoint.
+ \item[0x7201: Data Handler Debug] The debug register of the data handler. The contents of this register may change anytime.
+ \item[0x7202: Status of the IPU handler] The status register of the IPU handler. The meanings of each bit is given in table \ref{endpointipuhandlerstatus}.
\end{description}
\begin{table}[htbp]
\hline
\hline
8000 - 803F & ADC & Voltage monitoring ADC. see table \ref{MDCOEPADCMemoryMap} \\
+9000 - 90FF & Status & Status of the various state machines and control signals \\
A000 - A0FF & Config. Mem. & Configuration memory for thresholds and TDC settings \\
D000 & SPI Status Reg. & see section SPI Flash \\
D001 & SPI Control Reg. & see section SPI Flash \\
\end{table}
\subsubsection{MDC OEP Status Register}
-% TDC Readout Status
-% DEBUG_REGISTER_OUT(3 downto 0) <= state_bits;
-% DEBUG_REGISTER_OUT(4) <= reg_data_valid_out;
-% DEBUG_REGISTER_OUT(5) <= TOKEN_IN;
-% DEBUG_REGISTER_OUT(6) <= A_DST_IN;
-% DEBUG_REGISTER_OUT(7) <= A_AOD_IN;
-% DEBUG_REGISTER_OUT(8) <= A_RESERV_IN;
-% DEBUG_REGISTER_OUT(12 downto 9) <= FLAG_EVENT_COUNTER_IN;
-% DEBUG_REGISTER_OUT(31 downto 13) <= (others => '0');
-%
+\begin{description}
+ \item[0x9000: \filename{Tdc\_Readout} status register] The status register of the entity that reads data provided by the MBO.
+ \begin{description}
+ \item[Bit 3..0] State machine status \\ 0: idle; 1: save\_L\_word, 2: send\_token, 3: wait\_1, 4: wait\_2, 5: save\_L\_word\_next. 6: wait\_for\_AOD\_low, 7: wait\_3, 8: wait\_4, 9: save\_H\_word\_state\_next
+ \item[Bit 4] Data valid out
+ \item[Bit 5] Token back from MBO
+ \item[Bit 6] \portname{A\_Dst\_In}
+ \item[Bit 7] \portname{A\_Aod\_In}
+ \item[Bit 8] \portname{A\_Reserve\_In}
+ \item[Bit 12..9] Lower four bits of trigger number - used to tag data in fifos
+ \end{description}
+ \item[0x9001: \filename{Load\_Mode\_Line} status register] The status register of the entity that controls the mode lines to the MBO.
+ \begin{description}
+ \item[Bit 7..0] State machine status
+ \item[Bit 8] MBO got the right sequence of modes for start-up
+ \item[Bit 9] MBO is configured for calibration
+ \item[Bit 16] status of GDE line
+ \item[Bit 17] status of MOD line
+ \item[Bit 18] status of RES line
+ \item[Bit 19] status of TOK line
+ \item[Bit 20] status of WRM line
+ \item[Bit 21] status of RDM line
+ \end{description}
+ \item[0x9002: \filename{Load\_Tdc\_Setup} status register] The status register of the entity that loads data to TDC and CPLD configuration registers.
+ \begin{description}
+ \item[Bit 7..0] State machine status
+ \item[Bit 17..8] Current address of configuration RAM read pointer
+ \item[Bit 18] TDC settings have been loaded
+ \item[Bit 19] Loading second part of configuration during calibration
+ \item[Bit 20] Processing a calibration trigger
+ \end{description}
+ \item[0x9003: \filename{Send\_Token\_To\_MB} status register] The status register of the entity that sends and receives the token to the MBO. Bits 3..0 show the status of the state machine.
+ \item[0x9004: \filename{Trigger\_Begrun} status register] The status register of the entity that controls the entities controlling mode lines and loading configuration to the MBO.
+ \begin{description}
+ \item[Bit 3..0] Step of the mode line loading sequence
+ \item[Bit 7..4] Step of the configuration loading sequence
+ \item[Bit 8] Start changing mode lines to begin calibration trigger
+ \item[Bit 9] Start configuration to begin calibration trigger
+ \item[Bit 10] Start changing mode lines for begin run trigger
+ \item[Bit 11] Start configuration for begin run trigger
+ \item[Bit 12] Configuration for calibration has been loaded
+ \item[Bit 13] Configuration for start-up has been loaded
+ \item[Bit 14] Configuration for start-up has been loaded
+ \item[Bit 19..16] Status of the state machine
+ \end{description}
+\end{description}
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