--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module Version: 4.6
+--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 36 -depth 512 -no_enable -pe -1 -pf -1 -e
+
+-- Thu Aug 27 10:17:29 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_36x512 is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(35 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_36x512;
+
+architecture Structure of fifo_36x512 is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal cnt_con: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_36x512.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "NOREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>rden_i, CLKR=>Clock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>Q(34), DO17=>Q(35), DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_21: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co3_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_36x512 is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+
+
+--synopsys translate_off
+
+library pcsc_work;
+use pcsc_work.all;
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity PCSC is
+GENERIC(
+ CONFIG_FILE : String := "serdes_fot_full_quad_ctc.txt"
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+
+end PCSC;
+
+architecture PCSC_arch of PCSC is
+
+component PCSC_sim
+GENERIC(
+ CONFIG_FILE : String
+ );
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+end component;
+
+begin
+
+PCSC_sim_inst : PCSC_sim
+generic map (
+ CONFIG_FILE => CONFIG_FILE)
+port map (
+ HDINN0 => HDINN0,
+ HDINN1 => HDINN1,
+ HDINN2 => HDINN2,
+ HDINN3 => HDINN3,
+ HDINP0 => HDINP0,
+ HDINP1 => HDINP1,
+ HDINP2 => HDINP2,
+ HDINP3 => HDINP3,
+ REFCLKN => REFCLKN,
+ REFCLKP => REFCLKP,
+ CIN11 => CIN11,
+ CIN10 => CIN10,
+ CIN9 => CIN9,
+ CIN8 => CIN8,
+ CIN7 => CIN7,
+ CIN6 => CIN6,
+ CIN5 => CIN5,
+ CIN4 => CIN4,
+ CIN3 => CIN3,
+ CIN2 => CIN2,
+ CIN1 => CIN1,
+ CIN0 => CIN0,
+ CYAWSTN => CYAWSTN,
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,
+
+ FF_TX_D_0_0 => FF_TX_D_0_0,
+ FF_TX_D_0_1 => FF_TX_D_0_1,
+ FF_TX_D_0_2 => FF_TX_D_0_2,
+ FF_TX_D_0_3 => FF_TX_D_0_3,
+ FF_TX_D_0_4 => FF_TX_D_0_4,
+ FF_TX_D_0_5 => FF_TX_D_0_5,
+ FF_TX_D_0_6 => FF_TX_D_0_6,
+ FF_TX_D_0_7 => FF_TX_D_0_7,
+ FF_TX_D_0_8 => FF_TX_D_0_8,
+ FF_TX_D_0_9 => FF_TX_D_0_9,
+ FF_TX_D_0_10 => FF_TX_D_0_10,
+ FF_TX_D_0_11 => FF_TX_D_0_11,
+ FF_TX_D_0_12 => FF_TX_D_0_12,
+ FF_TX_D_0_13 => FF_TX_D_0_13,
+ FF_TX_D_0_14 => FF_TX_D_0_14,
+ FF_TX_D_0_15 => FF_TX_D_0_15,
+ FF_TX_D_0_16 => FF_TX_D_0_16,
+ FF_TX_D_0_17 => FF_TX_D_0_17,
+ FF_TX_D_0_18 => FF_TX_D_0_18,
+ FF_TX_D_0_19 => FF_TX_D_0_19,
+ FF_TX_D_0_20 => FF_TX_D_0_20,
+ FF_TX_D_0_21 => FF_TX_D_0_21,
+ FF_TX_D_0_22 => FF_TX_D_0_22,
+ FF_TX_D_0_23 => FF_TX_D_0_23,
+ FF_TX_D_1_0 => FF_TX_D_1_0,
+ FF_TX_D_1_1 => FF_TX_D_1_1,
+ FF_TX_D_1_2 => FF_TX_D_1_2,
+ FF_TX_D_1_3 => FF_TX_D_1_3,
+ FF_TX_D_1_4 => FF_TX_D_1_4,
+ FF_TX_D_1_5 => FF_TX_D_1_5,
+ FF_TX_D_1_6 => FF_TX_D_1_6,
+ FF_TX_D_1_7 => FF_TX_D_1_7,
+ FF_TX_D_1_8 => FF_TX_D_1_8,
+ FF_TX_D_1_9 => FF_TX_D_1_9,
+ FF_TX_D_1_10 => FF_TX_D_1_10,
+ FF_TX_D_1_11 => FF_TX_D_1_11,
+ FF_TX_D_1_12 => FF_TX_D_1_12,
+ FF_TX_D_1_13 => FF_TX_D_1_13,
+ FF_TX_D_1_14 => FF_TX_D_1_14,
+ FF_TX_D_1_15 => FF_TX_D_1_15,
+ FF_TX_D_1_16 => FF_TX_D_1_16,
+ FF_TX_D_1_17 => FF_TX_D_1_17,
+ FF_TX_D_1_18 => FF_TX_D_1_18,
+ FF_TX_D_1_19 => FF_TX_D_1_19,
+ FF_TX_D_1_20 => FF_TX_D_1_20,
+ FF_TX_D_1_21 => FF_TX_D_1_21,
+ FF_TX_D_1_22 => FF_TX_D_1_22,
+ FF_TX_D_1_23 => FF_TX_D_1_23,
+ FF_TX_D_2_0 => FF_TX_D_2_0,
+ FF_TX_D_2_1 => FF_TX_D_2_1,
+ FF_TX_D_2_2 => FF_TX_D_2_2,
+ FF_TX_D_2_3 => FF_TX_D_2_3,
+ FF_TX_D_2_4 => FF_TX_D_2_4,
+ FF_TX_D_2_5 => FF_TX_D_2_5,
+ FF_TX_D_2_6 => FF_TX_D_2_6,
+ FF_TX_D_2_7 => FF_TX_D_2_7,
+ FF_TX_D_2_8 => FF_TX_D_2_8,
+ FF_TX_D_2_9 => FF_TX_D_2_9,
+ FF_TX_D_2_10 => FF_TX_D_2_10,
+ FF_TX_D_2_11 => FF_TX_D_2_11,
+ FF_TX_D_2_12 => FF_TX_D_2_12,
+ FF_TX_D_2_13 => FF_TX_D_2_13,
+ FF_TX_D_2_14 => FF_TX_D_2_14,
+ FF_TX_D_2_15 => FF_TX_D_2_15,
+ FF_TX_D_2_16 => FF_TX_D_2_16,
+ FF_TX_D_2_17 => FF_TX_D_2_17,
+ FF_TX_D_2_18 => FF_TX_D_2_18,
+ FF_TX_D_2_19 => FF_TX_D_2_19,
+ FF_TX_D_2_20 => FF_TX_D_2_20,
+ FF_TX_D_2_21 => FF_TX_D_2_21,
+ FF_TX_D_2_22 => FF_TX_D_2_22,
+ FF_TX_D_2_23 => FF_TX_D_2_23,
+ FF_TX_D_3_0 => FF_TX_D_3_0,
+ FF_TX_D_3_1 => FF_TX_D_3_1,
+ FF_TX_D_3_2 => FF_TX_D_3_2,
+ FF_TX_D_3_3 => FF_TX_D_3_3,
+ FF_TX_D_3_4 => FF_TX_D_3_4,
+ FF_TX_D_3_5 => FF_TX_D_3_5,
+ FF_TX_D_3_6 => FF_TX_D_3_6,
+ FF_TX_D_3_7 => FF_TX_D_3_7,
+ FF_TX_D_3_8 => FF_TX_D_3_8,
+ FF_TX_D_3_9 => FF_TX_D_3_9,
+ FF_TX_D_3_10 => FF_TX_D_3_10,
+ FF_TX_D_3_11 => FF_TX_D_3_11,
+ FF_TX_D_3_12 => FF_TX_D_3_12,
+ FF_TX_D_3_13 => FF_TX_D_3_13,
+ FF_TX_D_3_14 => FF_TX_D_3_14,
+ FF_TX_D_3_15 => FF_TX_D_3_15,
+ FF_TX_D_3_16 => FF_TX_D_3_16,
+ FF_TX_D_3_17 => FF_TX_D_3_17,
+ FF_TX_D_3_18 => FF_TX_D_3_18,
+ FF_TX_D_3_19 => FF_TX_D_3_19,
+ FF_TX_D_3_20 => FF_TX_D_3_20,
+ FF_TX_D_3_21 => FF_TX_D_3_21,
+ FF_TX_D_3_22 => FF_TX_D_3_22,
+ FF_TX_D_3_23 => FF_TX_D_3_23,
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,
+ FFC_EI_EN_0 => FFC_EI_EN_0,
+ FFC_EI_EN_1 => FFC_EI_EN_1,
+ FFC_EI_EN_2 => FFC_EI_EN_2,
+ FFC_EI_EN_3 => FFC_EI_EN_3,
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
+ FFC_MACRO_RST => FFC_MACRO_RST,
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
+ FFC_QUAD_RST => FFC_QUAD_RST,
+ FFC_RRST_0 => FFC_RRST_0,
+ FFC_RRST_1 => FFC_RRST_1,
+ FFC_RRST_2 => FFC_RRST_2,
+ FFC_RRST_3 => FFC_RRST_3,
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
+ FFC_TRST => FFC_TRST,
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
+ SCIADDR0 => SCIADDR0,
+ SCIADDR1 => SCIADDR1,
+ SCIADDR2 => SCIADDR2,
+ SCIADDR3 => SCIADDR3,
+ SCIADDR4 => SCIADDR4,
+ SCIADDR5 => SCIADDR5,
+ SCIENAUX => SCIENAUX,
+ SCIENCH0 => SCIENCH0,
+ SCIENCH1 => SCIENCH1,
+ SCIENCH2 => SCIENCH2,
+ SCIENCH3 => SCIENCH3,
+ SCIRD => SCIRD,
+ SCISELAUX => SCISELAUX,
+ SCISELCH0 => SCISELCH0,
+ SCISELCH1 => SCISELCH1,
+ SCISELCH2 => SCISELCH2,
+ SCISELCH3 => SCISELCH3,
+ SCIWDATA0 => SCIWDATA0,
+ SCIWDATA1 => SCIWDATA1,
+ SCIWDATA2 => SCIWDATA2,
+ SCIWDATA3 => SCIWDATA3,
+ SCIWDATA4 => SCIWDATA4,
+ SCIWDATA5 => SCIWDATA5,
+ SCIWDATA6 => SCIWDATA6,
+ SCIWDATA7 => SCIWDATA7,
+ SCIWSTN => SCIWSTN,
+ HDOUTN0 => HDOUTN0,
+ HDOUTN1 => HDOUTN1,
+ HDOUTN2 => HDOUTN2,
+ HDOUTN3 => HDOUTN3,
+ HDOUTP0 => HDOUTP0,
+ HDOUTP1 => HDOUTP1,
+ HDOUTP2 => HDOUTP2,
+ HDOUTP3 => HDOUTP3,
+ COUT19 => COUT19,
+ COUT18 => COUT18,
+ COUT17 => COUT17,
+ COUT16 => COUT16,
+ COUT15 => COUT15,
+ COUT14 => COUT14,
+ COUT13 => COUT13,
+ COUT12 => COUT12,
+ COUT11 => COUT11,
+ COUT10 => COUT10,
+ COUT9 => COUT9,
+ COUT8 => COUT8,
+ COUT7 => COUT7,
+ COUT6 => COUT6,
+ COUT5 => COUT5,
+ COUT4 => COUT4,
+ COUT3 => COUT3,
+ COUT2 => COUT2,
+ COUT1 => COUT1,
+ COUT0 => COUT0,
+ FF_RX_D_0_0 => FF_RX_D_0_0,
+ FF_RX_D_0_1 => FF_RX_D_0_1,
+ FF_RX_D_0_2 => FF_RX_D_0_2,
+ FF_RX_D_0_3 => FF_RX_D_0_3,
+ FF_RX_D_0_4 => FF_RX_D_0_4,
+ FF_RX_D_0_5 => FF_RX_D_0_5,
+ FF_RX_D_0_6 => FF_RX_D_0_6,
+ FF_RX_D_0_7 => FF_RX_D_0_7,
+ FF_RX_D_0_8 => FF_RX_D_0_8,
+ FF_RX_D_0_9 => FF_RX_D_0_9,
+ FF_RX_D_0_10 => FF_RX_D_0_10,
+ FF_RX_D_0_11 => FF_RX_D_0_11,
+ FF_RX_D_0_12 => FF_RX_D_0_12,
+ FF_RX_D_0_13 => FF_RX_D_0_13,
+ FF_RX_D_0_14 => FF_RX_D_0_14,
+ FF_RX_D_0_15 => FF_RX_D_0_15,
+ FF_RX_D_0_16 => FF_RX_D_0_16,
+ FF_RX_D_0_17 => FF_RX_D_0_17,
+ FF_RX_D_0_18 => FF_RX_D_0_18,
+ FF_RX_D_0_19 => FF_RX_D_0_19,
+ FF_RX_D_0_20 => FF_RX_D_0_20,
+ FF_RX_D_0_21 => FF_RX_D_0_21,
+ FF_RX_D_0_22 => FF_RX_D_0_22,
+ FF_RX_D_0_23 => FF_RX_D_0_23,
+ FF_RX_D_1_0 => FF_RX_D_1_0,
+ FF_RX_D_1_1 => FF_RX_D_1_1,
+ FF_RX_D_1_2 => FF_RX_D_1_2,
+ FF_RX_D_1_3 => FF_RX_D_1_3,
+ FF_RX_D_1_4 => FF_RX_D_1_4,
+ FF_RX_D_1_5 => FF_RX_D_1_5,
+ FF_RX_D_1_6 => FF_RX_D_1_6,
+ FF_RX_D_1_7 => FF_RX_D_1_7,
+ FF_RX_D_1_8 => FF_RX_D_1_8,
+ FF_RX_D_1_9 => FF_RX_D_1_9,
+ FF_RX_D_1_10 => FF_RX_D_1_10,
+ FF_RX_D_1_11 => FF_RX_D_1_11,
+ FF_RX_D_1_12 => FF_RX_D_1_12,
+ FF_RX_D_1_13 => FF_RX_D_1_13,
+ FF_RX_D_1_14 => FF_RX_D_1_14,
+ FF_RX_D_1_15 => FF_RX_D_1_15,
+ FF_RX_D_1_16 => FF_RX_D_1_16,
+ FF_RX_D_1_17 => FF_RX_D_1_17,
+ FF_RX_D_1_18 => FF_RX_D_1_18,
+ FF_RX_D_1_19 => FF_RX_D_1_19,
+ FF_RX_D_1_20 => FF_RX_D_1_20,
+ FF_RX_D_1_21 => FF_RX_D_1_21,
+ FF_RX_D_1_22 => FF_RX_D_1_22,
+ FF_RX_D_1_23 => FF_RX_D_1_23,
+ FF_RX_D_2_0 => FF_RX_D_2_0,
+ FF_RX_D_2_1 => FF_RX_D_2_1,
+ FF_RX_D_2_2 => FF_RX_D_2_2,
+ FF_RX_D_2_3 => FF_RX_D_2_3,
+ FF_RX_D_2_4 => FF_RX_D_2_4,
+ FF_RX_D_2_5 => FF_RX_D_2_5,
+ FF_RX_D_2_6 => FF_RX_D_2_6,
+ FF_RX_D_2_7 => FF_RX_D_2_7,
+ FF_RX_D_2_8 => FF_RX_D_2_8,
+ FF_RX_D_2_9 => FF_RX_D_2_9,
+ FF_RX_D_2_10 => FF_RX_D_2_10,
+ FF_RX_D_2_11 => FF_RX_D_2_11,
+ FF_RX_D_2_12 => FF_RX_D_2_12,
+ FF_RX_D_2_13 => FF_RX_D_2_13,
+ FF_RX_D_2_14 => FF_RX_D_2_14,
+ FF_RX_D_2_15 => FF_RX_D_2_15,
+ FF_RX_D_2_16 => FF_RX_D_2_16,
+ FF_RX_D_2_17 => FF_RX_D_2_17,
+ FF_RX_D_2_18 => FF_RX_D_2_18,
+ FF_RX_D_2_19 => FF_RX_D_2_19,
+ FF_RX_D_2_20 => FF_RX_D_2_20,
+ FF_RX_D_2_21 => FF_RX_D_2_21,
+ FF_RX_D_2_22 => FF_RX_D_2_22,
+ FF_RX_D_2_23 => FF_RX_D_2_23,
+ FF_RX_D_3_0 => FF_RX_D_3_0,
+ FF_RX_D_3_1 => FF_RX_D_3_1,
+ FF_RX_D_3_2 => FF_RX_D_3_2,
+ FF_RX_D_3_3 => FF_RX_D_3_3,
+ FF_RX_D_3_4 => FF_RX_D_3_4,
+ FF_RX_D_3_5 => FF_RX_D_3_5,
+ FF_RX_D_3_6 => FF_RX_D_3_6,
+ FF_RX_D_3_7 => FF_RX_D_3_7,
+ FF_RX_D_3_8 => FF_RX_D_3_8,
+ FF_RX_D_3_9 => FF_RX_D_3_9,
+ FF_RX_D_3_10 => FF_RX_D_3_10,
+ FF_RX_D_3_11 => FF_RX_D_3_11,
+ FF_RX_D_3_12 => FF_RX_D_3_12,
+ FF_RX_D_3_13 => FF_RX_D_3_13,
+ FF_RX_D_3_14 => FF_RX_D_3_14,
+ FF_RX_D_3_15 => FF_RX_D_3_15,
+ FF_RX_D_3_16 => FF_RX_D_3_16,
+ FF_RX_D_3_17 => FF_RX_D_3_17,
+ FF_RX_D_3_18 => FF_RX_D_3_18,
+ FF_RX_D_3_19 => FF_RX_D_3_19,
+ FF_RX_D_3_20 => FF_RX_D_3_20,
+ FF_RX_D_3_21 => FF_RX_D_3_21,
+ FF_RX_D_3_22 => FF_RX_D_3_22,
+ FF_RX_D_3_23 => FF_RX_D_3_23,
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
+ FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,
+ FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,
+ FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,
+ FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,
+ FF_TX_F_CLK => FF_TX_F_CLK,
+ FF_TX_H_CLK => FF_TX_H_CLK,
+ FF_TX_Q_CLK => FF_TX_Q_CLK,
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
+ FFS_PLOL => FFS_PLOL,
+ FFS_RLOL_0 => FFS_RLOL_0,
+ FFS_RLOL_1 => FFS_RLOL_1,
+ FFS_RLOL_2 => FFS_RLOL_2,
+ FFS_RLOL_3 => FFS_RLOL_3,
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
+ OOB_OUT_0 => OOB_OUT_0,
+ OOB_OUT_1 => OOB_OUT_1,
+ OOB_OUT_2 => OOB_OUT_2,
+ OOB_OUT_3 => OOB_OUT_3,
+ REFCK2CORE => REFCK2CORE,
+ SCIINT => SCIINT,
+ SCIRDATA0 => SCIRDATA0,
+ SCIRDATA1 => SCIRDATA1,
+ SCIRDATA2 => SCIRDATA2,
+ SCIRDATA3 => SCIRDATA3,
+ SCIRDATA4 => SCIRDATA4,
+ SCIRDATA5 => SCIRDATA5,
+ SCIRDATA6 => SCIRDATA6,
+ SCIRDATA7 => SCIRDATA7
+ );
+
+end PCSC_arch;
+
+--synopsys translate_on
+
+--synopsys translate_off
+library ECP2;
+use ECP2.components.all;
+--synopsys translate_on
+
+library IEEE, STD;
+use IEEE.std_logic_1164.all;
+use STD.TEXTIO.all;
+
+entity serdes_fot_full_quad_ctc is
+ GENERIC (USER_CONFIG_FILE : String := "serdes_fot_full_quad_ctc.txt");
+ port (
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp0, hdinn0 : in std_logic;
+ hdoutp0, hdoutn0 : out std_logic;
+ ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;
+ ff_txdata_ch0 : in std_logic_vector (7 downto 0);
+ ff_rxdata_ch0 : out std_logic_vector (7 downto 0);
+ ff_tx_k_cntrl_ch0 : in std_logic;
+ ff_rx_k_cntrl_ch0 : out std_logic;
+ ff_rxfullclk_ch0 : out std_logic;
+ ff_xmit_ch0 : in std_logic;
+ ff_correct_disp_ch0 : in std_logic;
+ ff_disp_err_ch0, ff_cv_ch0 : out std_logic;
+ ff_rx_even_ch0 : out std_logic;
+ ffc_rrst_ch0 : in std_logic;
+ ffc_lane_tx_rst_ch0 : in std_logic;
+ ffc_lane_rx_rst_ch0 : in std_logic;
+ ffc_txpwdnb_ch0 : in std_logic;
+ ffc_rxpwdnb_ch0 : in std_logic;
+ ffs_rlos_lo_ch0 : out std_logic;
+ ffs_ls_sync_status_ch0 : out std_logic;
+ ffs_cc_underrun_ch0 : out std_logic;
+ ffs_cc_overrun_ch0 : out std_logic;
+ ffs_txfbfifo_error_ch0 : out std_logic;
+ ffs_rxfbfifo_error_ch0 : out std_logic;
+ ffs_rlol_ch0 : out std_logic;
+ oob_out_ch0 : out std_logic;
+ hdinp1, hdinn1 : in std_logic;
+ hdoutp1, hdoutn1 : out std_logic;
+ ff_rxiclk_ch1, ff_txiclk_ch1, ff_ebrd_clk_1 : in std_logic;
+ ff_txdata_ch1 : in std_logic_vector (7 downto 0);
+ ff_rxdata_ch1 : out std_logic_vector (7 downto 0);
+ ff_tx_k_cntrl_ch1 : in std_logic;
+ ff_rx_k_cntrl_ch1 : out std_logic;
+ ff_rxfullclk_ch1 : out std_logic;
+ ff_xmit_ch1 : in std_logic;
+ ff_correct_disp_ch1 : in std_logic;
+ ff_disp_err_ch1, ff_cv_ch1 : out std_logic;
+ ff_rx_even_ch1 : out std_logic;
+ ffc_rrst_ch1 : in std_logic;
+ ffc_lane_tx_rst_ch1 : in std_logic;
+ ffc_lane_rx_rst_ch1 : in std_logic;
+ ffc_txpwdnb_ch1 : in std_logic;
+ ffc_rxpwdnb_ch1 : in std_logic;
+ ffs_rlos_lo_ch1 : out std_logic;
+ ffs_ls_sync_status_ch1 : out std_logic;
+ ffs_cc_underrun_ch1 : out std_logic;
+ ffs_cc_overrun_ch1 : out std_logic;
+ ffs_txfbfifo_error_ch1 : out std_logic;
+ ffs_rxfbfifo_error_ch1 : out std_logic;
+ ffs_rlol_ch1 : out std_logic;
+ oob_out_ch1 : out std_logic;
+ hdinp2, hdinn2 : in std_logic;
+ hdoutp2, hdoutn2 : out std_logic;
+ ff_rxiclk_ch2, ff_txiclk_ch2, ff_ebrd_clk_2 : in std_logic;
+ ff_txdata_ch2 : in std_logic_vector (7 downto 0);
+ ff_rxdata_ch2 : out std_logic_vector (7 downto 0);
+ ff_tx_k_cntrl_ch2 : in std_logic;
+ ff_rx_k_cntrl_ch2 : out std_logic;
+ ff_rxfullclk_ch2 : out std_logic;
+ ff_xmit_ch2 : in std_logic;
+ ff_correct_disp_ch2 : in std_logic;
+ ff_disp_err_ch2, ff_cv_ch2 : out std_logic;
+ ff_rx_even_ch2 : out std_logic;
+ ffc_rrst_ch2 : in std_logic;
+ ffc_lane_tx_rst_ch2 : in std_logic;
+ ffc_lane_rx_rst_ch2 : in std_logic;
+ ffc_txpwdnb_ch2 : in std_logic;
+ ffc_rxpwdnb_ch2 : in std_logic;
+ ffs_rlos_lo_ch2 : out std_logic;
+ ffs_ls_sync_status_ch2 : out std_logic;
+ ffs_cc_underrun_ch2 : out std_logic;
+ ffs_cc_overrun_ch2 : out std_logic;
+ ffs_txfbfifo_error_ch2 : out std_logic;
+ ffs_rxfbfifo_error_ch2 : out std_logic;
+ ffs_rlol_ch2 : out std_logic;
+ oob_out_ch2 : out std_logic;
+ hdinp3, hdinn3 : in std_logic;
+ hdoutp3, hdoutn3 : out std_logic;
+ ff_rxiclk_ch3, ff_txiclk_ch3, ff_ebrd_clk_3 : in std_logic;
+ ff_txdata_ch3 : in std_logic_vector (7 downto 0);
+ ff_rxdata_ch3 : out std_logic_vector (7 downto 0);
+ ff_tx_k_cntrl_ch3 : in std_logic;
+ ff_rx_k_cntrl_ch3 : out std_logic;
+ ff_rxfullclk_ch3 : out std_logic;
+ ff_xmit_ch3 : in std_logic;
+ ff_correct_disp_ch3 : in std_logic;
+ ff_disp_err_ch3, ff_cv_ch3 : out std_logic;
+ ff_rx_even_ch3 : out std_logic;
+ ffc_rrst_ch3 : in std_logic;
+ ffc_lane_tx_rst_ch3 : in std_logic;
+ ffc_lane_rx_rst_ch3 : in std_logic;
+ ffc_txpwdnb_ch3 : in std_logic;
+ ffc_rxpwdnb_ch3 : in std_logic;
+ ffs_rlos_lo_ch3 : out std_logic;
+ ffs_ls_sync_status_ch3 : out std_logic;
+ ffs_cc_underrun_ch3 : out std_logic;
+ ffs_cc_overrun_ch3 : out std_logic;
+ ffs_txfbfifo_error_ch3 : out std_logic;
+ ffs_rxfbfifo_error_ch3 : out std_logic;
+ ffs_rlol_ch3 : out std_logic;
+ oob_out_ch3 : out std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic);
+
+end serdes_fot_full_quad_ctc;
+
+architecture serdes_fot_full_quad_ctc_arch of serdes_fot_full_quad_ctc is
+
+component VLO
+port (
+ Z : out std_logic);
+end component;
+
+component VHI
+port (
+ Z : out std_logic);
+end component;
+component PCSC
+--synopsys translate_off
+GENERIC(
+ CONFIG_FILE : String
+ );
+--synopsys translate_on
+port (
+ HDINN0 : in std_logic;
+ HDINN1 : in std_logic;
+ HDINN2 : in std_logic;
+ HDINN3 : in std_logic;
+ HDINP0 : in std_logic;
+ HDINP1 : in std_logic;
+ HDINP2 : in std_logic;
+ HDINP3 : in std_logic;
+ REFCLKN : in std_logic;
+ REFCLKP : in std_logic;
+ CIN0 : in std_logic;
+ CIN1 : in std_logic;
+ CIN2 : in std_logic;
+ CIN3 : in std_logic;
+ CIN4 : in std_logic;
+ CIN5 : in std_logic;
+ CIN6 : in std_logic;
+ CIN7 : in std_logic;
+ CIN8 : in std_logic;
+ CIN9 : in std_logic;
+ CIN10 : in std_logic;
+ CIN11 : in std_logic;
+ CYAWSTN : in std_logic;
+ FF_EBRD_CLK_0 : in std_logic;
+ FF_EBRD_CLK_1 : in std_logic;
+ FF_EBRD_CLK_2 : in std_logic;
+ FF_EBRD_CLK_3 : in std_logic;
+ FF_RXI_CLK_0 : in std_logic;
+ FF_RXI_CLK_1 : in std_logic;
+ FF_RXI_CLK_2 : in std_logic;
+ FF_RXI_CLK_3 : in std_logic;
+ FF_TX_D_0_0 : in std_logic;
+ FF_TX_D_0_1 : in std_logic;
+ FF_TX_D_0_2 : in std_logic;
+ FF_TX_D_0_3 : in std_logic;
+ FF_TX_D_0_4 : in std_logic;
+ FF_TX_D_0_5 : in std_logic;
+ FF_TX_D_0_6 : in std_logic;
+ FF_TX_D_0_7 : in std_logic;
+ FF_TX_D_0_8 : in std_logic;
+ FF_TX_D_0_9 : in std_logic;
+ FF_TX_D_0_10 : in std_logic;
+ FF_TX_D_0_11 : in std_logic;
+ FF_TX_D_0_12 : in std_logic;
+ FF_TX_D_0_13 : in std_logic;
+ FF_TX_D_0_14 : in std_logic;
+ FF_TX_D_0_15 : in std_logic;
+ FF_TX_D_0_16 : in std_logic;
+ FF_TX_D_0_17 : in std_logic;
+ FF_TX_D_0_18 : in std_logic;
+ FF_TX_D_0_19 : in std_logic;
+ FF_TX_D_0_20 : in std_logic;
+ FF_TX_D_0_21 : in std_logic;
+ FF_TX_D_0_22 : in std_logic;
+ FF_TX_D_0_23 : in std_logic;
+ FF_TX_D_1_0 : in std_logic;
+ FF_TX_D_1_1 : in std_logic;
+ FF_TX_D_1_2 : in std_logic;
+ FF_TX_D_1_3 : in std_logic;
+ FF_TX_D_1_4 : in std_logic;
+ FF_TX_D_1_5 : in std_logic;
+ FF_TX_D_1_6 : in std_logic;
+ FF_TX_D_1_7 : in std_logic;
+ FF_TX_D_1_8 : in std_logic;
+ FF_TX_D_1_9 : in std_logic;
+ FF_TX_D_1_10 : in std_logic;
+ FF_TX_D_1_11 : in std_logic;
+ FF_TX_D_1_12 : in std_logic;
+ FF_TX_D_1_13 : in std_logic;
+ FF_TX_D_1_14 : in std_logic;
+ FF_TX_D_1_15 : in std_logic;
+ FF_TX_D_1_16 : in std_logic;
+ FF_TX_D_1_17 : in std_logic;
+ FF_TX_D_1_18 : in std_logic;
+ FF_TX_D_1_19 : in std_logic;
+ FF_TX_D_1_20 : in std_logic;
+ FF_TX_D_1_21 : in std_logic;
+ FF_TX_D_1_22 : in std_logic;
+ FF_TX_D_1_23 : in std_logic;
+ FF_TX_D_2_0 : in std_logic;
+ FF_TX_D_2_1 : in std_logic;
+ FF_TX_D_2_2 : in std_logic;
+ FF_TX_D_2_3 : in std_logic;
+ FF_TX_D_2_4 : in std_logic;
+ FF_TX_D_2_5 : in std_logic;
+ FF_TX_D_2_6 : in std_logic;
+ FF_TX_D_2_7 : in std_logic;
+ FF_TX_D_2_8 : in std_logic;
+ FF_TX_D_2_9 : in std_logic;
+ FF_TX_D_2_10 : in std_logic;
+ FF_TX_D_2_11 : in std_logic;
+ FF_TX_D_2_12 : in std_logic;
+ FF_TX_D_2_13 : in std_logic;
+ FF_TX_D_2_14 : in std_logic;
+ FF_TX_D_2_15 : in std_logic;
+ FF_TX_D_2_16 : in std_logic;
+ FF_TX_D_2_17 : in std_logic;
+ FF_TX_D_2_18 : in std_logic;
+ FF_TX_D_2_19 : in std_logic;
+ FF_TX_D_2_20 : in std_logic;
+ FF_TX_D_2_21 : in std_logic;
+ FF_TX_D_2_22 : in std_logic;
+ FF_TX_D_2_23 : in std_logic;
+ FF_TX_D_3_0 : in std_logic;
+ FF_TX_D_3_1 : in std_logic;
+ FF_TX_D_3_2 : in std_logic;
+ FF_TX_D_3_3 : in std_logic;
+ FF_TX_D_3_4 : in std_logic;
+ FF_TX_D_3_5 : in std_logic;
+ FF_TX_D_3_6 : in std_logic;
+ FF_TX_D_3_7 : in std_logic;
+ FF_TX_D_3_8 : in std_logic;
+ FF_TX_D_3_9 : in std_logic;
+ FF_TX_D_3_10 : in std_logic;
+ FF_TX_D_3_11 : in std_logic;
+ FF_TX_D_3_12 : in std_logic;
+ FF_TX_D_3_13 : in std_logic;
+ FF_TX_D_3_14 : in std_logic;
+ FF_TX_D_3_15 : in std_logic;
+ FF_TX_D_3_16 : in std_logic;
+ FF_TX_D_3_17 : in std_logic;
+ FF_TX_D_3_18 : in std_logic;
+ FF_TX_D_3_19 : in std_logic;
+ FF_TX_D_3_20 : in std_logic;
+ FF_TX_D_3_21 : in std_logic;
+ FF_TX_D_3_22 : in std_logic;
+ FF_TX_D_3_23 : in std_logic;
+ FF_TXI_CLK_0 : in std_logic;
+ FF_TXI_CLK_1 : in std_logic;
+ FF_TXI_CLK_2 : in std_logic;
+ FF_TXI_CLK_3 : in std_logic;
+ FFC_CK_CORE_RX : in std_logic;
+ FFC_CK_CORE_TX : in std_logic;
+ FFC_EI_EN_0 : in std_logic;
+ FFC_EI_EN_1 : in std_logic;
+ FFC_EI_EN_2 : in std_logic;
+ FFC_EI_EN_3 : in std_logic;
+ FFC_ENABLE_CGALIGN_0 : in std_logic;
+ FFC_ENABLE_CGALIGN_1 : in std_logic;
+ FFC_ENABLE_CGALIGN_2 : in std_logic;
+ FFC_ENABLE_CGALIGN_3 : in std_logic;
+ FFC_FB_LOOPBACK_0 : in std_logic;
+ FFC_FB_LOOPBACK_1 : in std_logic;
+ FFC_FB_LOOPBACK_2 : in std_logic;
+ FFC_FB_LOOPBACK_3 : in std_logic;
+ FFC_LANE_RX_RST_0 : in std_logic;
+ FFC_LANE_RX_RST_1 : in std_logic;
+ FFC_LANE_RX_RST_2 : in std_logic;
+ FFC_LANE_RX_RST_3 : in std_logic;
+ FFC_LANE_TX_RST_0 : in std_logic;
+ FFC_LANE_TX_RST_1 : in std_logic;
+ FFC_LANE_TX_RST_2 : in std_logic;
+ FFC_LANE_TX_RST_3 : in std_logic;
+ FFC_MACRO_RST : in std_logic;
+ FFC_PCI_DET_EN_0 : in std_logic;
+ FFC_PCI_DET_EN_1 : in std_logic;
+ FFC_PCI_DET_EN_2 : in std_logic;
+ FFC_PCI_DET_EN_3 : in std_logic;
+ FFC_PCIE_CT_0 : in std_logic;
+ FFC_PCIE_CT_1 : in std_logic;
+ FFC_PCIE_CT_2 : in std_logic;
+ FFC_PCIE_CT_3 : in std_logic;
+ FFC_PFIFO_CLR_0 : in std_logic;
+ FFC_PFIFO_CLR_1 : in std_logic;
+ FFC_PFIFO_CLR_2 : in std_logic;
+ FFC_PFIFO_CLR_3 : in std_logic;
+ FFC_QUAD_RST : in std_logic;
+ FFC_RRST_0 : in std_logic;
+ FFC_RRST_1 : in std_logic;
+ FFC_RRST_2 : in std_logic;
+ FFC_RRST_3 : in std_logic;
+ FFC_RXPWDNB_0 : in std_logic;
+ FFC_RXPWDNB_1 : in std_logic;
+ FFC_RXPWDNB_2 : in std_logic;
+ FFC_RXPWDNB_3 : in std_logic;
+ FFC_SB_INV_RX_0 : in std_logic;
+ FFC_SB_INV_RX_1 : in std_logic;
+ FFC_SB_INV_RX_2 : in std_logic;
+ FFC_SB_INV_RX_3 : in std_logic;
+ FFC_SB_PFIFO_LP_0 : in std_logic;
+ FFC_SB_PFIFO_LP_1 : in std_logic;
+ FFC_SB_PFIFO_LP_2 : in std_logic;
+ FFC_SB_PFIFO_LP_3 : in std_logic;
+ FFC_SIGNAL_DETECT_0 : in std_logic;
+ FFC_SIGNAL_DETECT_1 : in std_logic;
+ FFC_SIGNAL_DETECT_2 : in std_logic;
+ FFC_SIGNAL_DETECT_3 : in std_logic;
+ FFC_TRST : in std_logic;
+ FFC_TXPWDNB_0 : in std_logic;
+ FFC_TXPWDNB_1 : in std_logic;
+ FFC_TXPWDNB_2 : in std_logic;
+ FFC_TXPWDNB_3 : in std_logic;
+ SCIADDR0 : in std_logic;
+ SCIADDR1 : in std_logic;
+ SCIADDR2 : in std_logic;
+ SCIADDR3 : in std_logic;
+ SCIADDR4 : in std_logic;
+ SCIADDR5 : in std_logic;
+ SCIENAUX : in std_logic;
+ SCIENCH0 : in std_logic;
+ SCIENCH1 : in std_logic;
+ SCIENCH2 : in std_logic;
+ SCIENCH3 : in std_logic;
+ SCIRD : in std_logic;
+ SCISELAUX : in std_logic;
+ SCISELCH0 : in std_logic;
+ SCISELCH1 : in std_logic;
+ SCISELCH2 : in std_logic;
+ SCISELCH3 : in std_logic;
+ SCIWDATA0 : in std_logic;
+ SCIWDATA1 : in std_logic;
+ SCIWDATA2 : in std_logic;
+ SCIWDATA3 : in std_logic;
+ SCIWDATA4 : in std_logic;
+ SCIWDATA5 : in std_logic;
+ SCIWDATA6 : in std_logic;
+ SCIWDATA7 : in std_logic;
+ SCIWSTN : in std_logic;
+ HDOUTN0 : out std_logic;
+ HDOUTN1 : out std_logic;
+ HDOUTN2 : out std_logic;
+ HDOUTN3 : out std_logic;
+ HDOUTP0 : out std_logic;
+ HDOUTP1 : out std_logic;
+ HDOUTP2 : out std_logic;
+ HDOUTP3 : out std_logic;
+ COUT0 : out std_logic;
+ COUT1 : out std_logic;
+ COUT2 : out std_logic;
+ COUT3 : out std_logic;
+ COUT4 : out std_logic;
+ COUT5 : out std_logic;
+ COUT6 : out std_logic;
+ COUT7 : out std_logic;
+ COUT8 : out std_logic;
+ COUT9 : out std_logic;
+ COUT10 : out std_logic;
+ COUT11 : out std_logic;
+ COUT12 : out std_logic;
+ COUT13 : out std_logic;
+ COUT14 : out std_logic;
+ COUT15 : out std_logic;
+ COUT16 : out std_logic;
+ COUT17 : out std_logic;
+ COUT18 : out std_logic;
+ COUT19 : out std_logic;
+ FF_RX_D_0_0 : out std_logic;
+ FF_RX_D_0_1 : out std_logic;
+ FF_RX_D_0_2 : out std_logic;
+ FF_RX_D_0_3 : out std_logic;
+ FF_RX_D_0_4 : out std_logic;
+ FF_RX_D_0_5 : out std_logic;
+ FF_RX_D_0_6 : out std_logic;
+ FF_RX_D_0_7 : out std_logic;
+ FF_RX_D_0_8 : out std_logic;
+ FF_RX_D_0_9 : out std_logic;
+ FF_RX_D_0_10 : out std_logic;
+ FF_RX_D_0_11 : out std_logic;
+ FF_RX_D_0_12 : out std_logic;
+ FF_RX_D_0_13 : out std_logic;
+ FF_RX_D_0_14 : out std_logic;
+ FF_RX_D_0_15 : out std_logic;
+ FF_RX_D_0_16 : out std_logic;
+ FF_RX_D_0_17 : out std_logic;
+ FF_RX_D_0_18 : out std_logic;
+ FF_RX_D_0_19 : out std_logic;
+ FF_RX_D_0_20 : out std_logic;
+ FF_RX_D_0_21 : out std_logic;
+ FF_RX_D_0_22 : out std_logic;
+ FF_RX_D_0_23 : out std_logic;
+ FF_RX_D_1_0 : out std_logic;
+ FF_RX_D_1_1 : out std_logic;
+ FF_RX_D_1_2 : out std_logic;
+ FF_RX_D_1_3 : out std_logic;
+ FF_RX_D_1_4 : out std_logic;
+ FF_RX_D_1_5 : out std_logic;
+ FF_RX_D_1_6 : out std_logic;
+ FF_RX_D_1_7 : out std_logic;
+ FF_RX_D_1_8 : out std_logic;
+ FF_RX_D_1_9 : out std_logic;
+ FF_RX_D_1_10 : out std_logic;
+ FF_RX_D_1_11 : out std_logic;
+ FF_RX_D_1_12 : out std_logic;
+ FF_RX_D_1_13 : out std_logic;
+ FF_RX_D_1_14 : out std_logic;
+ FF_RX_D_1_15 : out std_logic;
+ FF_RX_D_1_16 : out std_logic;
+ FF_RX_D_1_17 : out std_logic;
+ FF_RX_D_1_18 : out std_logic;
+ FF_RX_D_1_19 : out std_logic;
+ FF_RX_D_1_20 : out std_logic;
+ FF_RX_D_1_21 : out std_logic;
+ FF_RX_D_1_22 : out std_logic;
+ FF_RX_D_1_23 : out std_logic;
+ FF_RX_D_2_0 : out std_logic;
+ FF_RX_D_2_1 : out std_logic;
+ FF_RX_D_2_2 : out std_logic;
+ FF_RX_D_2_3 : out std_logic;
+ FF_RX_D_2_4 : out std_logic;
+ FF_RX_D_2_5 : out std_logic;
+ FF_RX_D_2_6 : out std_logic;
+ FF_RX_D_2_7 : out std_logic;
+ FF_RX_D_2_8 : out std_logic;
+ FF_RX_D_2_9 : out std_logic;
+ FF_RX_D_2_10 : out std_logic;
+ FF_RX_D_2_11 : out std_logic;
+ FF_RX_D_2_12 : out std_logic;
+ FF_RX_D_2_13 : out std_logic;
+ FF_RX_D_2_14 : out std_logic;
+ FF_RX_D_2_15 : out std_logic;
+ FF_RX_D_2_16 : out std_logic;
+ FF_RX_D_2_17 : out std_logic;
+ FF_RX_D_2_18 : out std_logic;
+ FF_RX_D_2_19 : out std_logic;
+ FF_RX_D_2_20 : out std_logic;
+ FF_RX_D_2_21 : out std_logic;
+ FF_RX_D_2_22 : out std_logic;
+ FF_RX_D_2_23 : out std_logic;
+ FF_RX_D_3_0 : out std_logic;
+ FF_RX_D_3_1 : out std_logic;
+ FF_RX_D_3_2 : out std_logic;
+ FF_RX_D_3_3 : out std_logic;
+ FF_RX_D_3_4 : out std_logic;
+ FF_RX_D_3_5 : out std_logic;
+ FF_RX_D_3_6 : out std_logic;
+ FF_RX_D_3_7 : out std_logic;
+ FF_RX_D_3_8 : out std_logic;
+ FF_RX_D_3_9 : out std_logic;
+ FF_RX_D_3_10 : out std_logic;
+ FF_RX_D_3_11 : out std_logic;
+ FF_RX_D_3_12 : out std_logic;
+ FF_RX_D_3_13 : out std_logic;
+ FF_RX_D_3_14 : out std_logic;
+ FF_RX_D_3_15 : out std_logic;
+ FF_RX_D_3_16 : out std_logic;
+ FF_RX_D_3_17 : out std_logic;
+ FF_RX_D_3_18 : out std_logic;
+ FF_RX_D_3_19 : out std_logic;
+ FF_RX_D_3_20 : out std_logic;
+ FF_RX_D_3_21 : out std_logic;
+ FF_RX_D_3_22 : out std_logic;
+ FF_RX_D_3_23 : out std_logic;
+ FF_RX_F_CLK_0 : out std_logic;
+ FF_RX_F_CLK_1 : out std_logic;
+ FF_RX_F_CLK_2 : out std_logic;
+ FF_RX_F_CLK_3 : out std_logic;
+ FF_RX_H_CLK_0 : out std_logic;
+ FF_RX_H_CLK_1 : out std_logic;
+ FF_RX_H_CLK_2 : out std_logic;
+ FF_RX_H_CLK_3 : out std_logic;
+ FF_RX_Q_CLK_0 : out std_logic;
+ FF_RX_Q_CLK_1 : out std_logic;
+ FF_RX_Q_CLK_2 : out std_logic;
+ FF_RX_Q_CLK_3 : out std_logic;
+ FF_TX_F_CLK : out std_logic;
+ FF_TX_H_CLK : out std_logic;
+ FF_TX_Q_CLK : out std_logic;
+ FFS_CC_OVERRUN_0 : out std_logic;
+ FFS_CC_OVERRUN_1 : out std_logic;
+ FFS_CC_OVERRUN_2 : out std_logic;
+ FFS_CC_OVERRUN_3 : out std_logic;
+ FFS_CC_UNDERRUN_0 : out std_logic;
+ FFS_CC_UNDERRUN_1 : out std_logic;
+ FFS_CC_UNDERRUN_2 : out std_logic;
+ FFS_CC_UNDERRUN_3 : out std_logic;
+ FFS_LS_SYNC_STATUS_0 : out std_logic;
+ FFS_LS_SYNC_STATUS_1 : out std_logic;
+ FFS_LS_SYNC_STATUS_2 : out std_logic;
+ FFS_LS_SYNC_STATUS_3 : out std_logic;
+ FFS_PCIE_CON_0 : out std_logic;
+ FFS_PCIE_CON_1 : out std_logic;
+ FFS_PCIE_CON_2 : out std_logic;
+ FFS_PCIE_CON_3 : out std_logic;
+ FFS_PCIE_DONE_0 : out std_logic;
+ FFS_PCIE_DONE_1 : out std_logic;
+ FFS_PCIE_DONE_2 : out std_logic;
+ FFS_PCIE_DONE_3 : out std_logic;
+ FFS_RLOS_LO_0 : out std_logic;
+ FFS_RLOS_LO_1 : out std_logic;
+ FFS_RLOS_LO_2 : out std_logic;
+ FFS_RLOS_LO_3 : out std_logic;
+ OOB_OUT_0 : out std_logic;
+ OOB_OUT_1 : out std_logic;
+ OOB_OUT_2 : out std_logic;
+ OOB_OUT_3 : out std_logic;
+ REFCK2CORE : out std_logic;
+ SCIINT : out std_logic;
+ SCIRDATA0 : out std_logic;
+ SCIRDATA1 : out std_logic;
+ SCIRDATA2 : out std_logic;
+ SCIRDATA3 : out std_logic;
+ SCIRDATA4 : out std_logic;
+ SCIRDATA5 : out std_logic;
+ SCIRDATA6 : out std_logic;
+ SCIRDATA7 : out std_logic;
+ FFS_PLOL : out std_logic;
+ FFS_RLOL_0 : out std_logic;
+ FFS_RLOL_1 : out std_logic;
+ FFS_RLOL_2 : out std_logic;
+ FFS_RLOL_3 : out std_logic;
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;
+ FFS_TXFBFIFO_ERROR_3 : out std_logic
+);
+end component;
+ attribute IS_ASB: string;
+ attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";
+ attribute CONFIG_FILE: string;
+ attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;
+ attribute black_box_pad_pin: string;
+ attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
+
+signal fpsc_vlo : std_logic := '0';
+signal cin : std_logic_vector (11 downto 0) := "000000000000";
+signal cout : std_logic_vector (19 downto 0);
+
+begin
+
+vlo_inst : VLO port map(Z => fpsc_vlo);
+
+-- pcs_quad instance
+PCSC_INST : PCSC
+--synopsys translate_off
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)
+--synopsys translate_on
+port map (
+ FFC_CK_CORE_TX => core_txrefclk,
+ FFC_CK_CORE_RX => core_rxrefclk,
+ REFCLKP => fpsc_vlo,
+ REFCLKN => fpsc_vlo,
+ HDINP0 => hdinp0,
+ HDINN0 => hdinn0,
+ HDOUTP0 => hdoutp0,
+ HDOUTN0 => hdoutn0,
+ SCISELCH0 => fpsc_vlo,
+ SCIENCH0 => fpsc_vlo,
+ FF_RXI_CLK_0 => ff_rxiclk_ch0,
+ FF_TXI_CLK_0 => ff_txiclk_ch0,
+ FF_EBRD_CLK_0 => ff_ebrd_clk_0,
+ FF_RX_F_CLK_0 => ff_rxfullclk_ch0,
+ FF_RX_H_CLK_0 => open,
+ FF_RX_Q_CLK_0 => open,
+ FF_TX_D_0_0 => ff_txdata_ch0(0),
+ FF_TX_D_0_1 => ff_txdata_ch0(1),
+ FF_TX_D_0_2 => ff_txdata_ch0(2),
+ FF_TX_D_0_3 => ff_txdata_ch0(3),
+ FF_TX_D_0_4 => ff_txdata_ch0(4),
+ FF_TX_D_0_5 => ff_txdata_ch0(5),
+ FF_TX_D_0_6 => ff_txdata_ch0(6),
+ FF_TX_D_0_7 => ff_txdata_ch0(7),
+ FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,
+ FF_TX_D_0_9 => fpsc_vlo,
+ FF_TX_D_0_10 => ff_xmit_ch0,
+ FF_TX_D_0_11 => ff_correct_disp_ch0,
+ FF_TX_D_0_12 => fpsc_vlo,
+ FF_TX_D_0_13 => fpsc_vlo,
+ FF_TX_D_0_14 => fpsc_vlo,
+ FF_TX_D_0_15 => fpsc_vlo,
+ FF_TX_D_0_16 => fpsc_vlo,
+ FF_TX_D_0_17 => fpsc_vlo,
+ FF_TX_D_0_18 => fpsc_vlo,
+ FF_TX_D_0_19 => fpsc_vlo,
+ FF_TX_D_0_20 => fpsc_vlo,
+ FF_TX_D_0_21 => fpsc_vlo,
+ FF_TX_D_0_22 => fpsc_vlo,
+ FF_TX_D_0_23 => fpsc_vlo,
+ FF_RX_D_0_0 => ff_rxdata_ch0(0),
+ FF_RX_D_0_1 => ff_rxdata_ch0(1),
+ FF_RX_D_0_2 => ff_rxdata_ch0(2),
+ FF_RX_D_0_3 => ff_rxdata_ch0(3),
+ FF_RX_D_0_4 => ff_rxdata_ch0(4),
+ FF_RX_D_0_5 => ff_rxdata_ch0(5),
+ FF_RX_D_0_6 => ff_rxdata_ch0(6),
+ FF_RX_D_0_7 => ff_rxdata_ch0(7),
+ FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,
+ FF_RX_D_0_9 => ff_disp_err_ch0,
+ FF_RX_D_0_10 => ff_cv_ch0,
+ FF_RX_D_0_11 => ff_rx_even_ch0,
+ FF_RX_D_0_12 => open,
+ FF_RX_D_0_13 => open,
+ FF_RX_D_0_14 => open,
+ FF_RX_D_0_15 => open,
+ FF_RX_D_0_16 => open,
+ FF_RX_D_0_17 => open,
+ FF_RX_D_0_18 => open,
+ FF_RX_D_0_19 => open,
+ FF_RX_D_0_20 => open,
+ FF_RX_D_0_21 => open,
+ FF_RX_D_0_22 => open,
+ FF_RX_D_0_23 => open,
+ FFC_RRST_0 => ffc_rrst_ch0,
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,
+ FFC_PFIFO_CLR_0 => fpsc_vlo,
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,
+ FFC_SB_INV_RX_0 => fpsc_vlo,
+ FFC_PCIE_CT_0 => fpsc_vlo,
+ FFC_PCI_DET_EN_0 => fpsc_vlo,
+ FFS_PCIE_DONE_0 => open,
+ FFS_PCIE_CON_0 => open,
+ FFC_EI_EN_0 => fpsc_vlo,
+ FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,
+ FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,
+ FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,
+ FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,
+ FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,
+ FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,
+ FFS_CC_UNDERRUN_0 => ffs_cc_underrun_ch0,
+ FFS_CC_OVERRUN_0 => ffs_cc_overrun_ch0,
+ FFS_RXFBFIFO_ERROR_0 => ffs_rxfbfifo_error_ch0,
+ FFS_TXFBFIFO_ERROR_0 => ffs_txfbfifo_error_ch0,
+ FFS_RLOL_0 => ffs_rlol_ch0,
+ OOB_OUT_0 => oob_out_ch0,
+ HDINP1 => hdinp1,
+ HDINN1 => hdinn1,
+ HDOUTP1 => hdoutp1,
+ HDOUTN1 => hdoutn1,
+ SCISELCH1 => fpsc_vlo,
+ SCIENCH1 => fpsc_vlo,
+ FF_RXI_CLK_1 => ff_rxiclk_ch1,
+ FF_TXI_CLK_1 => ff_txiclk_ch1,
+ FF_EBRD_CLK_1 => ff_ebrd_clk_1,
+ FF_RX_F_CLK_1 => ff_rxfullclk_ch1,
+ FF_RX_H_CLK_1 => open,
+ FF_RX_Q_CLK_1 => open,
+ FF_TX_D_1_0 => ff_txdata_ch1(0),
+ FF_TX_D_1_1 => ff_txdata_ch1(1),
+ FF_TX_D_1_2 => ff_txdata_ch1(2),
+ FF_TX_D_1_3 => ff_txdata_ch1(3),
+ FF_TX_D_1_4 => ff_txdata_ch1(4),
+ FF_TX_D_1_5 => ff_txdata_ch1(5),
+ FF_TX_D_1_6 => ff_txdata_ch1(6),
+ FF_TX_D_1_7 => ff_txdata_ch1(7),
+ FF_TX_D_1_8 => ff_tx_k_cntrl_ch1,
+ FF_TX_D_1_9 => fpsc_vlo,
+ FF_TX_D_1_10 => ff_xmit_ch1,
+ FF_TX_D_1_11 => ff_correct_disp_ch1,
+ FF_TX_D_1_12 => fpsc_vlo,
+ FF_TX_D_1_13 => fpsc_vlo,
+ FF_TX_D_1_14 => fpsc_vlo,
+ FF_TX_D_1_15 => fpsc_vlo,
+ FF_TX_D_1_16 => fpsc_vlo,
+ FF_TX_D_1_17 => fpsc_vlo,
+ FF_TX_D_1_18 => fpsc_vlo,
+ FF_TX_D_1_19 => fpsc_vlo,
+ FF_TX_D_1_20 => fpsc_vlo,
+ FF_TX_D_1_21 => fpsc_vlo,
+ FF_TX_D_1_22 => fpsc_vlo,
+ FF_TX_D_1_23 => fpsc_vlo,
+ FF_RX_D_1_0 => ff_rxdata_ch1(0),
+ FF_RX_D_1_1 => ff_rxdata_ch1(1),
+ FF_RX_D_1_2 => ff_rxdata_ch1(2),
+ FF_RX_D_1_3 => ff_rxdata_ch1(3),
+ FF_RX_D_1_4 => ff_rxdata_ch1(4),
+ FF_RX_D_1_5 => ff_rxdata_ch1(5),
+ FF_RX_D_1_6 => ff_rxdata_ch1(6),
+ FF_RX_D_1_7 => ff_rxdata_ch1(7),
+ FF_RX_D_1_8 => ff_rx_k_cntrl_ch1,
+ FF_RX_D_1_9 => ff_disp_err_ch1,
+ FF_RX_D_1_10 => ff_cv_ch1,
+ FF_RX_D_1_11 => ff_rx_even_ch1,
+ FF_RX_D_1_12 => open,
+ FF_RX_D_1_13 => open,
+ FF_RX_D_1_14 => open,
+ FF_RX_D_1_15 => open,
+ FF_RX_D_1_16 => open,
+ FF_RX_D_1_17 => open,
+ FF_RX_D_1_18 => open,
+ FF_RX_D_1_19 => open,
+ FF_RX_D_1_20 => open,
+ FF_RX_D_1_21 => open,
+ FF_RX_D_1_22 => open,
+ FF_RX_D_1_23 => open,
+ FFC_RRST_1 => ffc_rrst_ch1,
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,
+ FFC_PFIFO_CLR_1 => fpsc_vlo,
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,
+ FFC_SB_INV_RX_1 => fpsc_vlo,
+ FFC_PCIE_CT_1 => fpsc_vlo,
+ FFC_PCI_DET_EN_1 => fpsc_vlo,
+ FFS_PCIE_DONE_1 => open,
+ FFS_PCIE_CON_1 => open,
+ FFC_EI_EN_1 => fpsc_vlo,
+ FFC_LANE_TX_RST_1 => ffc_lane_tx_rst_ch1,
+ FFC_LANE_RX_RST_1 => ffc_lane_rx_rst_ch1,
+ FFC_TXPWDNB_1 => ffc_txpwdnb_ch1,
+ FFC_RXPWDNB_1 => ffc_rxpwdnb_ch1,
+ FFS_RLOS_LO_1 => ffs_rlos_lo_ch1,
+ FFS_LS_SYNC_STATUS_1 => ffs_ls_sync_status_ch1,
+ FFS_CC_UNDERRUN_1 => ffs_cc_underrun_ch1,
+ FFS_CC_OVERRUN_1 => ffs_cc_overrun_ch1,
+ FFS_RXFBFIFO_ERROR_1 => ffs_rxfbfifo_error_ch1,
+ FFS_TXFBFIFO_ERROR_1 => ffs_txfbfifo_error_ch1,
+ FFS_RLOL_1 => ffs_rlol_ch1,
+ OOB_OUT_1 => oob_out_ch1,
+ HDINP2 => hdinp2,
+ HDINN2 => hdinn2,
+ HDOUTP2 => hdoutp2,
+ HDOUTN2 => hdoutn2,
+ SCISELCH2 => fpsc_vlo,
+ SCIENCH2 => fpsc_vlo,
+ FF_RXI_CLK_2 => ff_rxiclk_ch2,
+ FF_TXI_CLK_2 => ff_txiclk_ch2,
+ FF_EBRD_CLK_2 => ff_ebrd_clk_2,
+ FF_RX_F_CLK_2 => ff_rxfullclk_ch2,
+ FF_RX_H_CLK_2 => open,
+ FF_RX_Q_CLK_2 => open,
+ FF_TX_D_2_0 => ff_txdata_ch2(0),
+ FF_TX_D_2_1 => ff_txdata_ch2(1),
+ FF_TX_D_2_2 => ff_txdata_ch2(2),
+ FF_TX_D_2_3 => ff_txdata_ch2(3),
+ FF_TX_D_2_4 => ff_txdata_ch2(4),
+ FF_TX_D_2_5 => ff_txdata_ch2(5),
+ FF_TX_D_2_6 => ff_txdata_ch2(6),
+ FF_TX_D_2_7 => ff_txdata_ch2(7),
+ FF_TX_D_2_8 => ff_tx_k_cntrl_ch2,
+ FF_TX_D_2_9 => fpsc_vlo,
+ FF_TX_D_2_10 => ff_xmit_ch2,
+ FF_TX_D_2_11 => ff_correct_disp_ch2,
+ FF_TX_D_2_12 => fpsc_vlo,
+ FF_TX_D_2_13 => fpsc_vlo,
+ FF_TX_D_2_14 => fpsc_vlo,
+ FF_TX_D_2_15 => fpsc_vlo,
+ FF_TX_D_2_16 => fpsc_vlo,
+ FF_TX_D_2_17 => fpsc_vlo,
+ FF_TX_D_2_18 => fpsc_vlo,
+ FF_TX_D_2_19 => fpsc_vlo,
+ FF_TX_D_2_20 => fpsc_vlo,
+ FF_TX_D_2_21 => fpsc_vlo,
+ FF_TX_D_2_22 => fpsc_vlo,
+ FF_TX_D_2_23 => fpsc_vlo,
+ FF_RX_D_2_0 => ff_rxdata_ch2(0),
+ FF_RX_D_2_1 => ff_rxdata_ch2(1),
+ FF_RX_D_2_2 => ff_rxdata_ch2(2),
+ FF_RX_D_2_3 => ff_rxdata_ch2(3),
+ FF_RX_D_2_4 => ff_rxdata_ch2(4),
+ FF_RX_D_2_5 => ff_rxdata_ch2(5),
+ FF_RX_D_2_6 => ff_rxdata_ch2(6),
+ FF_RX_D_2_7 => ff_rxdata_ch2(7),
+ FF_RX_D_2_8 => ff_rx_k_cntrl_ch2,
+ FF_RX_D_2_9 => ff_disp_err_ch2,
+ FF_RX_D_2_10 => ff_cv_ch2,
+ FF_RX_D_2_11 => ff_rx_even_ch2,
+ FF_RX_D_2_12 => open,
+ FF_RX_D_2_13 => open,
+ FF_RX_D_2_14 => open,
+ FF_RX_D_2_15 => open,
+ FF_RX_D_2_16 => open,
+ FF_RX_D_2_17 => open,
+ FF_RX_D_2_18 => open,
+ FF_RX_D_2_19 => open,
+ FF_RX_D_2_20 => open,
+ FF_RX_D_2_21 => open,
+ FF_RX_D_2_22 => open,
+ FF_RX_D_2_23 => open,
+ FFC_RRST_2 => ffc_rrst_ch2,
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,
+ FFC_PFIFO_CLR_2 => fpsc_vlo,
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,
+ FFC_SB_INV_RX_2 => fpsc_vlo,
+ FFC_PCIE_CT_2 => fpsc_vlo,
+ FFC_PCI_DET_EN_2 => fpsc_vlo,
+ FFS_PCIE_DONE_2 => open,
+ FFS_PCIE_CON_2 => open,
+ FFC_EI_EN_2 => fpsc_vlo,
+ FFC_LANE_TX_RST_2 => ffc_lane_tx_rst_ch2,
+ FFC_LANE_RX_RST_2 => ffc_lane_rx_rst_ch2,
+ FFC_TXPWDNB_2 => ffc_txpwdnb_ch2,
+ FFC_RXPWDNB_2 => ffc_rxpwdnb_ch2,
+ FFS_RLOS_LO_2 => ffs_rlos_lo_ch2,
+ FFS_LS_SYNC_STATUS_2 => ffs_ls_sync_status_ch2,
+ FFS_CC_UNDERRUN_2 => ffs_cc_underrun_ch2,
+ FFS_CC_OVERRUN_2 => ffs_cc_overrun_ch2,
+ FFS_RXFBFIFO_ERROR_2 => ffs_rxfbfifo_error_ch2,
+ FFS_TXFBFIFO_ERROR_2 => ffs_txfbfifo_error_ch2,
+ FFS_RLOL_2 => ffs_rlol_ch2,
+ OOB_OUT_2 => oob_out_ch2,
+ HDINP3 => hdinp3,
+ HDINN3 => hdinn3,
+ HDOUTP3 => hdoutp3,
+ HDOUTN3 => hdoutn3,
+ SCISELCH3 => fpsc_vlo,
+ SCIENCH3 => fpsc_vlo,
+ FF_RXI_CLK_3 => ff_rxiclk_ch3,
+ FF_TXI_CLK_3 => ff_txiclk_ch3,
+ FF_EBRD_CLK_3 => ff_ebrd_clk_3,
+ FF_RX_F_CLK_3 => ff_rxfullclk_ch3,
+ FF_RX_H_CLK_3 => open,
+ FF_RX_Q_CLK_3 => open,
+ FF_TX_D_3_0 => ff_txdata_ch3(0),
+ FF_TX_D_3_1 => ff_txdata_ch3(1),
+ FF_TX_D_3_2 => ff_txdata_ch3(2),
+ FF_TX_D_3_3 => ff_txdata_ch3(3),
+ FF_TX_D_3_4 => ff_txdata_ch3(4),
+ FF_TX_D_3_5 => ff_txdata_ch3(5),
+ FF_TX_D_3_6 => ff_txdata_ch3(6),
+ FF_TX_D_3_7 => ff_txdata_ch3(7),
+ FF_TX_D_3_8 => ff_tx_k_cntrl_ch3,
+ FF_TX_D_3_9 => fpsc_vlo,
+ FF_TX_D_3_10 => ff_xmit_ch3,
+ FF_TX_D_3_11 => ff_correct_disp_ch3,
+ FF_TX_D_3_12 => fpsc_vlo,
+ FF_TX_D_3_13 => fpsc_vlo,
+ FF_TX_D_3_14 => fpsc_vlo,
+ FF_TX_D_3_15 => fpsc_vlo,
+ FF_TX_D_3_16 => fpsc_vlo,
+ FF_TX_D_3_17 => fpsc_vlo,
+ FF_TX_D_3_18 => fpsc_vlo,
+ FF_TX_D_3_19 => fpsc_vlo,
+ FF_TX_D_3_20 => fpsc_vlo,
+ FF_TX_D_3_21 => fpsc_vlo,
+ FF_TX_D_3_22 => fpsc_vlo,
+ FF_TX_D_3_23 => fpsc_vlo,
+ FF_RX_D_3_0 => ff_rxdata_ch3(0),
+ FF_RX_D_3_1 => ff_rxdata_ch3(1),
+ FF_RX_D_3_2 => ff_rxdata_ch3(2),
+ FF_RX_D_3_3 => ff_rxdata_ch3(3),
+ FF_RX_D_3_4 => ff_rxdata_ch3(4),
+ FF_RX_D_3_5 => ff_rxdata_ch3(5),
+ FF_RX_D_3_6 => ff_rxdata_ch3(6),
+ FF_RX_D_3_7 => ff_rxdata_ch3(7),
+ FF_RX_D_3_8 => ff_rx_k_cntrl_ch3,
+ FF_RX_D_3_9 => ff_disp_err_ch3,
+ FF_RX_D_3_10 => ff_cv_ch3,
+ FF_RX_D_3_11 => ff_rx_even_ch3,
+ FF_RX_D_3_12 => open,
+ FF_RX_D_3_13 => open,
+ FF_RX_D_3_14 => open,
+ FF_RX_D_3_15 => open,
+ FF_RX_D_3_16 => open,
+ FF_RX_D_3_17 => open,
+ FF_RX_D_3_18 => open,
+ FF_RX_D_3_19 => open,
+ FF_RX_D_3_20 => open,
+ FF_RX_D_3_21 => open,
+ FF_RX_D_3_22 => open,
+ FF_RX_D_3_23 => open,
+ FFC_RRST_3 => ffc_rrst_ch3,
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+ FFC_PFIFO_CLR_3 => fpsc_vlo,
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,
+ FFC_SB_INV_RX_3 => fpsc_vlo,
+ FFC_PCIE_CT_3 => fpsc_vlo,
+ FFC_PCI_DET_EN_3 => fpsc_vlo,
+ FFS_PCIE_DONE_3 => open,
+ FFS_PCIE_CON_3 => open,
+ FFC_EI_EN_3 => fpsc_vlo,
+ FFC_LANE_TX_RST_3 => ffc_lane_tx_rst_ch3,
+ FFC_LANE_RX_RST_3 => ffc_lane_rx_rst_ch3,
+ FFC_TXPWDNB_3 => ffc_txpwdnb_ch3,
+ FFC_RXPWDNB_3 => ffc_rxpwdnb_ch3,
+ FFS_RLOS_LO_3 => ffs_rlos_lo_ch3,
+ FFS_LS_SYNC_STATUS_3 => ffs_ls_sync_status_ch3,
+ FFS_CC_UNDERRUN_3 => ffs_cc_underrun_ch3,
+ FFS_CC_OVERRUN_3 => ffs_cc_overrun_ch3,
+ FFS_RXFBFIFO_ERROR_3 => ffs_rxfbfifo_error_ch3,
+ FFS_TXFBFIFO_ERROR_3 => ffs_txfbfifo_error_ch3,
+ FFS_RLOL_3 => ffs_rlol_ch3,
+ OOB_OUT_3 => oob_out_ch3,
+ SCIWDATA0 => fpsc_vlo,
+ SCIWDATA1 => fpsc_vlo,
+ SCIWDATA2 => fpsc_vlo,
+ SCIWDATA3 => fpsc_vlo,
+ SCIWDATA4 => fpsc_vlo,
+ SCIWDATA5 => fpsc_vlo,
+ SCIWDATA6 => fpsc_vlo,
+ SCIWDATA7 => fpsc_vlo,
+ SCIADDR0 => fpsc_vlo,
+ SCIADDR1 => fpsc_vlo,
+ SCIADDR2 => fpsc_vlo,
+ SCIADDR3 => fpsc_vlo,
+ SCIADDR4 => fpsc_vlo,
+ SCIADDR5 => fpsc_vlo,
+ SCIRDATA0 => open,
+ SCIRDATA1 => open,
+ SCIRDATA2 => open,
+ SCIRDATA3 => open,
+ SCIRDATA4 => open,
+ SCIRDATA5 => open,
+ SCIRDATA6 => open,
+ SCIRDATA7 => open,
+ SCIENAUX => fpsc_vlo,
+ SCISELAUX => fpsc_vlo,
+ SCIRD => fpsc_vlo,
+ SCIWSTN => fpsc_vlo,
+ CYAWSTN => fpsc_vlo,
+ SCIINT => open,
+ FFC_MACRO_RST => ffc_macro_rst,
+ FFC_QUAD_RST => ffc_quad_rst,
+ FFC_TRST => ffc_trst,
+ FF_TX_F_CLK => ff_txfullclk,
+ FF_TX_H_CLK => ff_txhalfclk,
+ FF_TX_Q_CLK => open,
+ REFCK2CORE => open,
+ CIN0 => cin(0),
+ CIN1 => cin(1),
+ CIN2 => cin(2),
+ CIN3 => cin(3),
+ CIN4 => cin(4),
+ CIN5 => cin(5),
+ CIN6 => cin(6),
+ CIN7 => cin(7),
+ CIN8 => cin(8),
+ CIN9 => cin(9),
+ CIN10 => cin(10),
+ CIN11 => cin(11),
+ COUT0 => cout(0),
+ COUT1 => cout(1),
+ COUT2 => cout(2),
+ COUT3 => cout(3),
+ COUT4 => cout(4),
+ COUT5 => cout(5),
+ COUT6 => cout(6),
+ COUT7 => cout(7),
+ COUT8 => cout(8),
+ COUT9 => cout(9),
+ COUT10 => cout(10),
+ COUT11 => cout(11),
+ COUT12 => cout(12),
+ COUT13 => cout(13),
+ COUT14 => cout(14),
+ COUT15 => cout(15),
+ COUT16 => cout(16),
+ COUT17 => cout(17),
+ COUT18 => cout(18),
+ COUT19 => cout(19),
+ FFS_PLOL => ffs_plol);
+
+--synopsys translate_off
+file_read : PROCESS
+VARIABLE open_status : file_open_status;
+FILE config : text;
+BEGIN
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);
+ IF (open_status = name_error) THEN
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
+ severity ERROR;
+ END IF;
+ wait;
+END PROCESS;
+--synopsys translate_on
+
+end serdes_fot_full_quad_ctc_arch ;
--- /dev/null
+LIBRARY ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity trb_net16_med_ecp_fot_4_ctc is
+ generic(
+ REVERSE_ORDER : integer range 0 to 1 := c_NO
+ -- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
+ );
+ port(
+ CLK : in std_logic;
+ CLK_25 : in std_logic;
+ CLK_EN : in std_logic;
+ RESET : in std_logic;
+
+ --Internal Connection
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector(3 downto 0);
+ MED_READ_OUT : out std_logic_vector(3 downto 0);
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH*4-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH*4-1 downto 0);
+ MED_DATAREADY_OUT : out std_logic_vector(3 downto 0);
+ MED_READ_IN : in std_logic_vector(3 downto 0);
+
+ --SFP Connection
+ TXP : out std_logic_vector(3 downto 0);
+ TXN : out std_logic_vector(3 downto 0);
+ RXP : in std_logic_vector(3 downto 0);
+ RXN : in std_logic_vector(3 downto 0);
+ SD : in std_logic_vector(3 downto 0);
+
+ -- Status and control port
+ STAT_OP : out std_logic_vector (63 downto 0);
+ CTRL_OP : in std_logic_vector (63 downto 0);
+ STAT_DEBUG : out std_logic_vector (255 downto 0);
+ CTRL_DEBUG : in std_logic_vector (63 downto 0)
+ );
+end entity;
+
+architecture trb_net16_med_ecp_fot_4_ctc_arch of trb_net16_med_ecp_fot_4_ctc is
+
+ -- Placer Directives
+ attribute HGROUP : string;
+ -- for whole architecture
+ attribute HGROUP of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "GROUP_PCS";
+ attribute syn_sharing : string;
+ attribute syn_sharing of trb_net16_med_ecp_fot_4_ctc_arch : architecture is "false";
+
+component serdes_fot_full_quad_ctc is
+ generic(
+ USER_CONFIG_FILE : String := "serdes_fot_full_quad_ctc.txt" );
+ PORT(
+ core_txrefclk : in std_logic;
+ core_rxrefclk : in std_logic;
+ hdinp0 : in std_logic;
+ hdinn0 : in std_logic;
+ ff_rxiclk_ch0 : in std_logic;
+ ff_txiclk_ch0 : in std_logic;
+ ff_ebrd_clk_0 : in std_logic;
+ ff_txdata_ch0 : in std_logic_vector(7 downto 0);
+ ff_tx_k_cntrl_ch0 : in std_logic;
+ ff_xmit_ch0 : in std_logic;
+ ff_correct_disp_ch0 : in std_logic;
+ ffc_rrst_ch0 : in std_logic;
+ ffc_lane_tx_rst_ch0 : in std_logic;
+ ffc_lane_rx_rst_ch0 : in std_logic;
+ ffc_txpwdnb_ch0 : in std_logic;
+ ffc_rxpwdnb_ch0 : in std_logic;
+ hdinp1 : in std_logic;
+ hdinn1 : in std_logic;
+ ff_rxiclk_ch1 : in std_logic;
+ ff_txiclk_ch1 : in std_logic;
+ ff_ebrd_clk_1 : in std_logic;
+ ff_txdata_ch1 : in std_logic_vector(7 downto 0);
+ ff_tx_k_cntrl_ch1 : in std_logic;
+ ff_xmit_ch1 : in std_logic;
+ ff_correct_disp_ch1 : in std_logic;
+ ffc_rrst_ch1 : in std_logic;
+ ffc_lane_tx_rst_ch1 : in std_logic;
+ ffc_lane_rx_rst_ch1 : in std_logic;
+ ffc_txpwdnb_ch1 : in std_logic;
+ ffc_rxpwdnb_ch1 : in std_logic;
+ hdinp2 : in std_logic;
+ hdinn2 : in std_logic;
+ ff_rxiclk_ch2 : in std_logic;
+ ff_txiclk_ch2 : in std_logic;
+ ff_ebrd_clk_2 : in std_logic;
+ ff_txdata_ch2 : in std_logic_vector(7 downto 0);
+ ff_tx_k_cntrl_ch2 : in std_logic;
+ ff_xmit_ch2 : in std_logic;
+ ff_correct_disp_ch2 : in std_logic;
+ ffc_rrst_ch2 : in std_logic;
+ ffc_lane_tx_rst_ch2 : in std_logic;
+ ffc_lane_rx_rst_ch2 : in std_logic;
+ ffc_txpwdnb_ch2 : in std_logic;
+ ffc_rxpwdnb_ch2 : in std_logic;
+ hdinp3 : in std_logic;
+ hdinn3 : in std_logic;
+ ff_rxiclk_ch3 : in std_logic;
+ ff_txiclk_ch3 : in std_logic;
+ ff_ebrd_clk_3 : in std_logic;
+ ff_txdata_ch3 : in std_logic_vector(7 downto 0);
+ ff_tx_k_cntrl_ch3 : in std_logic;
+ ff_xmit_ch3 : in std_logic;
+ ff_correct_disp_ch3 : in std_logic;
+ ffc_rrst_ch3 : in std_logic;
+ ffc_lane_tx_rst_ch3 : in std_logic;
+ ffc_lane_rx_rst_ch3 : in std_logic;
+ ffc_txpwdnb_ch3 : in std_logic;
+ ffc_rxpwdnb_ch3 : in std_logic;
+ ffc_macro_rst : in std_logic;
+ ffc_quad_rst : in std_logic;
+ ffc_trst : in std_logic;
+ hdoutp0 : out std_logic;
+ hdoutn0 : out std_logic;
+ ff_rxdata_ch0 : out std_logic_vector(7 downto 0);
+ ff_rx_k_cntrl_ch0 : out std_logic;
+ ff_rxfullclk_ch0 : out std_logic;
+ ff_disp_err_ch0 : out std_logic;
+ ff_cv_ch0 : out std_logic;
+ ff_rx_even_ch0 : out std_logic;
+ ffs_rlos_lo_ch0 : out std_logic;
+ ffs_ls_sync_status_ch0 : out std_logic;
+ ffs_cc_underrun_ch0 : out std_logic;
+ ffs_cc_overrun_ch0 : out std_logic;
+ ffs_txfbfifo_error_ch0 : out std_logic;
+ ffs_rxfbfifo_error_ch0 : out std_logic;
+ ffs_rlol_ch0 : out std_logic;
+ oob_out_ch0 : out std_logic;
+ hdoutp1 : out std_logic;
+ hdoutn1 : out std_logic;
+ ff_rxdata_ch1 : out std_logic_vector(7 downto 0);
+ ff_rx_k_cntrl_ch1 : out std_logic;
+ ff_rxfullclk_ch1 : out std_logic;
+ ff_disp_err_ch1 : out std_logic;
+ ff_cv_ch1 : out std_logic;
+ ff_rx_even_ch1 : out std_logic;
+ ffs_rlos_lo_ch1 : out std_logic;
+ ffs_ls_sync_status_ch1 : out std_logic;
+ ffs_cc_underrun_ch1 : out std_logic;
+ ffs_cc_overrun_ch1 : out std_logic;
+ ffs_txfbfifo_error_ch1 : out std_logic;
+ ffs_rxfbfifo_error_ch1 : out std_logic;
+ ffs_rlol_ch1 : out std_logic;
+ oob_out_ch1 : out std_logic;
+ hdoutp2 : out std_logic;
+ hdoutn2 : out std_logic;
+ ff_rxdata_ch2 : out std_logic_vector(7 downto 0);
+ ff_rx_k_cntrl_ch2 : out std_logic;
+ ff_rxfullclk_ch2 : out std_logic;
+ ff_disp_err_ch2 : out std_logic;
+ ff_cv_ch2 : out std_logic;
+ ff_rx_even_ch2 : out std_logic;
+ ffs_rlos_lo_ch2 : out std_logic;
+ ffs_ls_sync_status_ch2 : out std_logic;
+ ffs_cc_underrun_ch2 : out std_logic;
+ ffs_cc_overrun_ch2 : out std_logic;
+ ffs_txfbfifo_error_ch2 : out std_logic;
+ ffs_rxfbfifo_error_ch2 : out std_logic;
+ ffs_rlol_ch2 : out std_logic;
+ oob_out_ch2 : out std_logic;
+ hdoutp3 : out std_logic;
+ hdoutn3 : out std_logic;
+ ff_rxdata_ch3 : out std_logic_vector(7 downto 0);
+ ff_rx_k_cntrl_ch3 : out std_logic;
+ ff_rxfullclk_ch3 : out std_logic;
+ ff_disp_err_ch3 : out std_logic;
+ ff_cv_ch3 : out std_logic;
+ ff_rx_even_ch3 : out std_logic;
+ ffs_rlos_lo_ch3 : out std_logic;
+ ffs_ls_sync_status_ch3 : out std_logic;
+ ffs_cc_underrun_ch3 : out std_logic;
+ ffs_cc_overrun_ch3 : out std_logic;
+ ffs_txfbfifo_error_ch3 : out std_logic;
+ ffs_rxfbfifo_error_ch3 : out std_logic;
+ ffs_rlol_ch3 : out std_logic;
+ oob_out_ch3 : out std_logic;
+ ff_txfullclk : out std_logic;
+ ff_txhalfclk : out std_logic;
+ ffs_plol : out std_logic
+ );
+ end component;
+
+
+ component lattice_ecp2m_fifo_8x8_dualport
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(7 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+
+ component lattice_ecp2m_fifo_16x8_dualport
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic
+ );
+ end component;
+
+
+ type link_error_t is array(0 to 3) of std_logic_vector(7 downto 0);
+ signal link_error : link_error_t;
+ signal link_error_q: link_error_t;
+ signal reg_link_error : link_error_t;
+ signal ffs_plol : std_logic;
+ signal link_ok : std_logic_vector(3 downto 0);
+ signal link_ok_q : std_logic_vector(3 downto 0);
+ signal tx_data : std_logic_vector(8*4-1 downto 0);
+ signal rx_data : std_logic_vector(8*4-1 downto 0);
+ signal buf_rx_data_reg : std_logic_vector(8*4-1 downto 0);
+ signal ff_rxfullclk : std_logic_vector(3 downto 0);
+ signal ff_txfullclk : std_logic;
+ signal rx_k : std_logic_vector(3 downto 0);
+ signal tx_k : std_logic_vector(3 downto 0);
+ signal lane_rst : std_logic_vector(3 downto 0);
+ signal lane_rst_qtx : std_logic_vector(3 downto 0);
+ signal quad_rst : std_logic_vector(3 downto 0);
+ signal quad_rst_qtx : std_logic_vector(3 downto 0);
+
+ signal byte_waiting : std_logic_vector(3 downto 0);
+ signal byte_buffer : std_logic_vector(4*8-1 downto 0);
+ signal fifo_reset : std_logic_vector(3 downto 0);
+ signal tx_fifo_dout : std_logic_vector(4*16-1 downto 0);
+ signal tx_fifo_data_in : std_logic_vector(4*16-1 downto 0);
+ signal tx_fifo_read_en : std_logic_vector(3 downto 0);
+ signal tx_fifo_write_en : std_logic_vector(3 downto 0);
+ signal tx_fifo_empty : std_logic_vector(3 downto 0);
+ signal tx_fifo_full : std_logic_vector(3 downto 0);
+
+ signal tx_fifo_valid_read : std_logic_vector(3 downto 0);
+ signal tx_allow : std_logic_vector(3 downto 0);
+ signal tx_allow_del : std_logic_vector(3 downto 0);
+ signal tx_allow_qtx : std_logic_vector(3 downto 0);
+
+ signal rx_data_reg : std_logic_vector(4*8-1 downto 0);
+ signal buf_rx_data : std_logic_vector(4*8-1 downto 0);
+ signal buf_rx_k : std_logic_vector(3 downto 0);
+ signal rx_fifo_write_en : std_logic_vector(3 downto 0);
+ signal rx_fifo_read_en : std_logic_vector(3 downto 0);
+ signal rx_fifo_empty : std_logic_vector(3 downto 0);
+ signal rx_fifo_full : std_logic_vector(3 downto 0);
+ signal rx_fifo_dout : std_logic_vector(4*8-1 downto 0);
+ signal is_idle_word : std_logic_vector(3 downto 0);
+ signal rx_starting : std_logic_vector(3 downto 0);
+ signal rx_allow : std_logic_vector(3 downto 0);
+ signal rx_allow_del : std_logic_vector(3 downto 0);
+ signal rx_allow_qrx : std_logic_vector(3 downto 0);
+ signal sd_q : std_logic_vector(3 downto 0);
+ signal last_rx_fifo_read_en : std_logic_vector(3 downto 0);
+ signal last_rx_fifo_empty : std_logic_vector(3 downto 0);
+ signal last_last_rx_fifo_read_en : std_logic_vector(3 downto 0);
+ signal last_last_rx_fifo_empty : std_logic_vector(3 downto 0);
+ signal last_rx_fifo_dout : std_logic_vector(4*8-1 downto 0);
+ signal tx_fifo_valid_read_q : std_logic_vector(3 downto 0);
+
+ signal buf_med_dataready_out : std_logic_vector(3 downto 0);
+ signal buf_med_read_out : std_logic_vector(3 downto 0);
+ signal buf_med_data_out : std_logic_vector(16*4-1 downto 0);
+ signal byte_select : std_logic_vector(3 downto 0);
+ signal rx_counter : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+ signal sfp_los : std_logic_vector(3 downto 0);
+
+-- type led_counter_t is array(0 to 3) of std_logic_vector(15 downto 0);
+ signal led_counter : std_logic_vector(15 downto 0);
+ signal rx_led : std_logic_vector(3 downto 0);
+ signal tx_led : std_logic_vector(3 downto 0);
+
+ signal FSM_STAT_OP : std_logic_vector(4*16-1 downto 0);
+ signal FSM_STAT_DEBUG : std_logic_vector(4*32-1 downto 0);
+ signal FSM_CTRL_OP : std_logic_vector(4*16-1 downto 0);
+
+ signal send_reset_q : std_logic_vector(3 downto 0);
+ signal reset_word_cnt : std_logic_vector(19 downto 0);
+ signal send_reset_words : std_logic_vector(3 downto 0);
+ signal send_reset_words_q : std_logic_vector(3 downto 0);
+ signal make_trbnet_reset : std_logic_vector(3 downto 0);
+ signal make_trbnet_reset_q: std_logic_vector(3 downto 0);
+
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+
+ attribute syn_keep of led_counter : signal is true;
+ attribute syn_preserve of led_counter : signal is true;
+ attribute syn_keep of byte_waiting : signal is true;
+ attribute syn_preserve of byte_waiting : signal is true;
+
+begin
+ gen_normal_serdes : if REVERSE_ORDER = c_NO generate
+ THE_SERDES: serdes_fot_full_quad_ctc
+ port map(
+ core_txrefclk => CLK_25,
+ core_rxrefclk => CLK_25,
+ hdinp0 => RXP(0),
+ hdinn0 => RXN(0),
+ hdoutp0 => TXP(0),
+ hdoutn0 => TXN(0),
+ ff_rxiclk_ch0 => CLK_25, --ff_rxfullclk(0),
+ ff_txiclk_ch0 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_0 => CLK_25, --ff_txfullclk,--ff_rxfullclk(0),
+ ff_txdata_ch0 => tx_data(7 downto 0),
+ ff_rxdata_ch0 => rx_data(7 downto 0),
+ ff_tx_k_cntrl_ch0 => tx_k(0),
+ ff_rx_k_cntrl_ch0 => rx_k(0),
+ -- ff_rxfullclk_ch0 => ff_rxfullclk(0),
+ -- ff_force_disp_ch0 => '0',
+ ff_xmit_ch0 => '0',
+ -- ff_disp_sel_ch0 => '0',
+ ff_correct_disp_ch0 => '0',
+ ff_disp_err_ch0 => link_error(0)(0),
+ ff_cv_ch0 => link_error(0)(1),
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => lane_rst(0), --lane_rst(0),
+ ffc_lane_rx_rst_ch0 => lane_rst(0),
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffs_rlos_lo_ch0 => link_error(0)(2),
+ ffs_ls_sync_status_ch0 => link_ok(0),
+ ffs_cc_underrun_ch0 => link_error(0)(3),
+ ffs_cc_overrun_ch0 => link_error(0)(4),
+ ffs_txfbfifo_error_ch0 => link_error(0)(5),
+ ffs_rxfbfifo_error_ch0 => link_error(0)(6),
+ ffs_rlol_ch0 => link_error(0)(7),
+ oob_out_ch0 => open,
+
+ hdinp1 => rxp(1),
+ hdinn1 => rxn(1),
+ hdoutp1 => txp(1),
+ hdoutn1 => txn(1),
+ ff_rxiclk_ch1 => CLK_25, --ff_rxfullclk(1),
+ ff_txiclk_ch1 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_1 => CLK_25, --ff_txfullclk,--ff_rxfullclk(1),
+ ff_txdata_ch1 => tx_data(15 downto 8),
+ ff_rxdata_ch1 => rx_data(15 downto 8),
+ ff_tx_k_cntrl_ch1 => tx_k(1),
+ ff_rx_k_cntrl_ch1 => rx_k(1),
+ --ff_rxfullclk_ch1 => ff_rxfullclk(1),
+ -- ff_force_disp_ch1 => '0',
+ ff_xmit_ch1 => '0',
+ -- ff_disp_sel_ch1 => '0',
+ ff_correct_disp_ch1 => '0',
+ ff_disp_err_ch1 => link_error(1)(0),
+ ff_cv_ch1 => link_error(1)(1),
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => lane_rst(1), --lane_rst(1),
+ ffc_lane_rx_rst_ch1 => lane_rst(1),
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffs_rlos_lo_ch1 => link_error(1)(2),
+ ffs_ls_sync_status_ch1 => link_ok(1),
+ ffs_cc_underrun_ch1 => link_error(1)(3),
+ ffs_cc_overrun_ch1 => link_error(1)(4),
+ ffs_txfbfifo_error_ch1 => link_error(1)(5),
+ ffs_rxfbfifo_error_ch1 => link_error(1)(6),
+ ffs_rlol_ch1 => link_error(1)(7),
+ oob_out_ch1 => open,
+
+ hdinp2 => rxp(2),
+ hdinn2 => rxn(2),
+ hdoutp2 => txp(2),
+ hdoutn2 => txn(2),
+ ff_rxiclk_ch2 => CLK_25, --ff_rxfullclk(2),
+ ff_txiclk_ch2 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_2 => CLK_25, --ff_txfullclk,--ff_rxfullclk(2),
+ ff_txdata_ch2 => tx_data(23 downto 16),
+ ff_rxdata_ch2 => rx_data(23 downto 16),
+ ff_tx_k_cntrl_ch2 => tx_k(2),
+ ff_rx_k_cntrl_ch2 => rx_k(2),
+ -- ff_rxfullclk_ch2 => ff_rxfullclk(2),
+ -- ff_force_disp_ch2 => '0',
+ ff_xmit_ch2 => '0',
+ -- ff_disp_sel_ch2 => '0',
+ ff_correct_disp_ch2 => '0',
+ ff_disp_err_ch2 => link_error(2)(0),
+ ff_cv_ch2 => link_error(2)(1),
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => lane_rst(2), --lane_rst(2),
+ ffc_lane_rx_rst_ch2 => lane_rst(2),
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffs_rlos_lo_ch2 => link_error(2)(2),
+ ffs_ls_sync_status_ch2 => link_ok(2),
+ ffs_cc_underrun_ch2 => link_error(2)(3),
+ ffs_cc_overrun_ch2 => link_error(2)(4),
+ ffs_txfbfifo_error_ch2 => link_error(2)(5),
+ ffs_rxfbfifo_error_ch2 => link_error(2)(6),
+ ffs_rlol_ch2 => link_error(2)(7),
+ oob_out_ch2 => open,
+
+ hdinp3 => rxp(3),
+ hdinn3 => rxn(3),
+ hdoutp3 => txp(3),
+ hdoutn3 => txn(3),
+ ff_rxiclk_ch3 => CLK_25, --ff_rxfullclk(3),
+ ff_txiclk_ch3 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_3 => CLK_25, --ff_txfullclk,--ff_rxfullclk(3),
+ ff_txdata_ch3 => tx_data(31 downto 24),
+ ff_rxdata_ch3 => rx_data(31 downto 24),
+ ff_tx_k_cntrl_ch3 => tx_k(3),
+ ff_rx_k_cntrl_ch3 => rx_k(3),
+ -- ff_rxfullclk_ch3 => ff_rxfullclk(3),
+ -- ff_force_disp_ch3 => '0',
+ ff_xmit_ch3 => '0',
+ -- ff_disp_sel_ch3 => '0',
+ ff_correct_disp_ch3 => '0',
+ ff_disp_err_ch3 => link_error(3)(0),
+ ff_cv_ch3 => link_error(3)(1),
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => lane_rst(3), --lane_rst(3),
+ ffc_lane_rx_rst_ch3 => lane_rst(3),
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffs_rlos_lo_ch3 => link_error(3)(2),
+ ffs_ls_sync_status_ch3 => link_ok(3),
+ ffs_cc_underrun_ch3 => link_error(3)(3),
+ ffs_cc_overrun_ch3 => link_error(3)(4),
+ ffs_txfbfifo_error_ch3 => link_error(3)(5),
+ ffs_rxfbfifo_error_ch3 => link_error(3)(6),
+ ffs_rlol_ch3 => link_error(3)(7),
+ oob_out_ch3 => open,
+
+ ffc_macro_rst => '0',
+ ffc_quad_rst => quad_rst(0),
+ ffc_trst => '0',
+ ff_txfullclk => ff_txfullclk,
+ ffs_plol => ffs_plol
+ );
+ end generate;
+
+ gen_twisted_serdes : if REVERSE_ORDER = c_YES generate
+ THE_SERDES: serdes_fot_full_quad_ctc
+ port map(
+ core_txrefclk => CLK_25,
+ core_rxrefclk => CLK_25,
+ hdinp0 => RXP(0),
+ hdinn0 => RXN(0),
+ hdoutp0 => TXP(0),
+ hdoutn0 => TXN(0),
+ ff_rxiclk_ch0 => CLK_25, --ff_rxfullclk(3),
+ ff_txiclk_ch0 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_0 => CLK_25, --ff_txfullclk,--ff_rxfullclk(3),
+ ff_txdata_ch0 => tx_data(31 downto 24),
+ ff_rxdata_ch0 => rx_data(31 downto 24),
+ ff_tx_k_cntrl_ch0 => tx_k(3),
+ ff_rx_k_cntrl_ch0 => rx_k(3),
+ -- ff_rxfullclk_ch0 => ff_rxfullclk(3),
+ -- ff_force_disp_ch0 => '0',
+ ff_xmit_ch0 => '0',
+ -- ff_disp_sel_ch0 => '0',
+ ff_correct_disp_ch0 => '0',
+ ff_disp_err_ch0 => link_error(3)(0),
+ ff_cv_ch0 => link_error(3)(1),
+ ffc_rrst_ch0 => '0',
+ ffc_lane_tx_rst_ch0 => lane_rst(3), --lane_rst(0),
+ ffc_lane_rx_rst_ch0 => lane_rst(3),
+ ffc_txpwdnb_ch0 => '1',
+ ffc_rxpwdnb_ch0 => '1',
+ ffs_rlos_lo_ch0 => link_error(3)(2),
+ ffs_ls_sync_status_ch0 => link_ok(3),
+ ffs_cc_underrun_ch0 => link_error(3)(3),
+ ffs_cc_overrun_ch0 => link_error(3)(4),
+ ffs_txfbfifo_error_ch0 => link_error(3)(5),
+ ffs_rxfbfifo_error_ch0 => link_error(3)(6),
+ ffs_rlol_ch0 => link_error(3)(7),
+ oob_out_ch0 => open,
+
+ hdinp1 => rxp(1),
+ hdinn1 => rxn(1),
+ hdoutp1 => txp(1),
+ hdoutn1 => txn(1),
+ ff_rxiclk_ch1 => CLK_25, --ff_rxfullclk(2),
+ ff_txiclk_ch1 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_1 => CLK_25, --ff_txfullclk,--ff_rxfullclk(2),
+ ff_txdata_ch1 => tx_data(23 downto 16),
+ ff_rxdata_ch1 => rx_data(23 downto 16),
+ ff_tx_k_cntrl_ch1 => tx_k(2),
+ ff_rx_k_cntrl_ch1 => rx_k(2),
+ -- ff_rxfullclk_ch1 => ff_rxfullclk(2),
+ -- ff_force_disp_ch1 => '0',
+ ff_xmit_ch1 => '0',
+ -- ff_disp_sel_ch1 => '0',
+ ff_correct_disp_ch1 => '0',
+ ff_disp_err_ch1 => link_error(2)(0),
+ ff_cv_ch1 => link_error(2)(1),
+ ffc_rrst_ch1 => '0',
+ ffc_lane_tx_rst_ch1 => lane_rst(2), --lane_rst(1),
+ ffc_lane_rx_rst_ch1 => lane_rst(2),
+ ffc_txpwdnb_ch1 => '1',
+ ffc_rxpwdnb_ch1 => '1',
+ ffs_rlos_lo_ch1 => link_error(2)(2),
+ ffs_ls_sync_status_ch1 => link_ok(2),
+ ffs_cc_underrun_ch1 => link_error(2)(3),
+ ffs_cc_overrun_ch1 => link_error(2)(4),
+ ffs_txfbfifo_error_ch1 => link_error(2)(5),
+ ffs_rxfbfifo_error_ch1 => link_error(2)(6),
+ ffs_rlol_ch1 => link_error(2)(7),
+ oob_out_ch1 => open,
+
+ hdinp2 => rxp(2),
+ hdinn2 => rxn(2),
+ hdoutp2 => txp(2),
+ hdoutn2 => txn(2),
+ ff_rxiclk_ch2 => CLK_25, --ff_rxfullclk(1),
+ ff_txiclk_ch2 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_2 => CLK_25, --ff_txfullclk,--ff_rxfullclk(1),
+ ff_txdata_ch2 => tx_data(15 downto 8),
+ ff_rxdata_ch2 => rx_data(15 downto 8),
+ ff_tx_k_cntrl_ch2 => tx_k(1),
+ ff_rx_k_cntrl_ch2 => rx_k(1),
+ -- ff_rxfullclk_ch2 => ff_rxfullclk(1),
+ -- ff_force_disp_ch2 => '0',
+ ff_xmit_ch2 => '0',
+ -- ff_disp_sel_ch2 => '0',
+ ff_correct_disp_ch2 => '0',
+ ff_disp_err_ch2 => link_error(1)(0),
+ ff_cv_ch2 => link_error(1)(1),
+ ffc_rrst_ch2 => '0',
+ ffc_lane_tx_rst_ch2 => lane_rst(1), --lane_rst(2),
+ ffc_lane_rx_rst_ch2 => lane_rst(1),
+ ffc_txpwdnb_ch2 => '1',
+ ffc_rxpwdnb_ch2 => '1',
+ ffs_rlos_lo_ch2 => link_error(1)(2),
+ ffs_ls_sync_status_ch2 => link_ok(1),
+ ffs_cc_underrun_ch2 => link_error(1)(3),
+ ffs_cc_overrun_ch2 => link_error(1)(4),
+ ffs_txfbfifo_error_ch2 => link_error(1)(5),
+ ffs_rxfbfifo_error_ch2 => link_error(1)(6),
+ ffs_rlol_ch2 => link_error(1)(7),
+ oob_out_ch2 => open,
+
+ hdinp3 => rxp(3),
+ hdinn3 => rxn(3),
+ hdoutp3 => txp(3),
+ hdoutn3 => txn(3),
+ ff_rxiclk_ch3 => CLK_25, --ff_rxfullclk(0),
+ ff_txiclk_ch3 => CLK_25, --ff_txfullclk,
+ ff_ebrd_clk_3 => CLK_25, --ff_txfullclk,--ff_rxfullclk(0),
+ ff_txdata_ch3 => tx_data(7 downto 0),
+ ff_rxdata_ch3 => rx_data(7 downto 0),
+ ff_tx_k_cntrl_ch3 => tx_k(0),
+ ff_rx_k_cntrl_ch3 => rx_k(0),
+ -- ff_rxfullclk_ch3 => ff_rxfullclk(0),
+ -- ff_force_disp_ch3 => '0',
+ ff_xmit_ch3 => '0',
+ -- ff_disp_sel_ch3 => '0',
+ ff_correct_disp_ch3 => '0',
+ ff_disp_err_ch3 => link_error(0)(0),
+ ff_cv_ch3 => link_error(0)(1),
+ ffc_rrst_ch3 => '0',
+ ffc_lane_tx_rst_ch3 => lane_rst(0), --lane_rst(3),
+ ffc_lane_rx_rst_ch3 => lane_rst(0),
+ ffc_txpwdnb_ch3 => '1',
+ ffc_rxpwdnb_ch3 => '1',
+ ffs_rlos_lo_ch3 => link_error(0)(2),
+ ffs_ls_sync_status_ch3 => link_ok(0),
+ ffs_cc_underrun_ch3 => link_error(0)(3),
+ ffs_cc_overrun_ch3 => link_error(0)(4),
+ ffs_txfbfifo_error_ch3 => link_error(0)(5),
+ ffs_rxfbfifo_error_ch3 => link_error(0)(6),
+ ffs_rlol_ch3 => link_error(0)(7),
+ oob_out_ch3 => open,
+
+ ffc_macro_rst => '0',
+ ffc_quad_rst => quad_rst(0),
+ ffc_trst => '0',
+ ff_txfullclk => ff_txfullclk,
+ ffs_plol => ffs_plol
+ );
+ end generate;
+
+--TX Control 25
+---------------
+
+ gen_tx_fifos : for i in 0 to 3 generate
+
+ THE_TX_FIFO : trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map(
+ read_clock_in => CLK_25,--ff_txfullclk,
+ write_clock_in => CLK,
+ read_enable_in => tx_fifo_read_en(i),
+ write_enable_in => tx_fifo_write_en(i),
+ fifo_gsr_in => fifo_reset(i),
+ write_data_in => "00" & tx_fifo_data_in((i+1)*16-1 downto i*16),
+ read_data_out(15 downto 0) => tx_fifo_dout((i+1)*16-1 downto i*16),
+ full_out => tx_fifo_full(i),
+ empty_out => tx_fifo_empty(i)
+ );
+
+-- THE_TX_FIFO: lattice_ecp2m_fifo_16x8_dualport
+-- port map(
+-- Data => tx_fifo_data_in((i+1)*16-1 downto i*16),
+-- WrClock => CLK,
+-- RdClock => ff_txfullclk,
+-- WrEn => tx_fifo_write_en(i),
+-- RdEn => tx_fifo_read_en(i),
+-- Reset => fifo_reset(i),
+-- RPReset => fifo_reset(i),
+-- Q => tx_fifo_dout((i+1)*16-1 downto i*16),
+-- Empty => tx_fifo_empty(i),
+-- Full => tx_fifo_full(i)
+-- );
+
+ THE_READ_TX_FIFO_PROC: process( CLK_25 )
+ begin
+ if( rising_edge(CLK_25) ) then
+ if( reset = '1' ) then
+ byte_waiting(i) <= '0';
+ tx_fifo_read_en(i) <= '0';
+ tx_k(i) <= '1';
+ tx_data((i+1)*8-1 downto i*8) <= x"FE";
+ tx_fifo_valid_read(i) <= '0';
+ else
+ tx_fifo_read_en(i) <= tx_allow_qtx(i);
+ tx_fifo_valid_read(i) <= tx_fifo_read_en(i) and not tx_fifo_empty(i);
+ if( byte_waiting(i) = '0' ) then
+ if( (tx_fifo_valid_read(i) = '1')) then
+ byte_buffer((i+1)*8-1 downto i*8) <= tx_fifo_dout((i)*16+15 downto i*16+8);
+ byte_waiting(i) <= '1';
+ tx_k(i) <= '0';
+ tx_data((i+1)*8-1 downto i*8) <= tx_fifo_dout(i*16+7 downto i*16+0);
+ tx_fifo_read_en(i) <= tx_allow_qtx(i);
+ elsif send_reset_q(i) = '1' then
+ byte_buffer((i+1)*8-1 downto i*8) <= x"FE";
+ byte_waiting(i) <= '1';
+ tx_k(i) <= '1';
+ tx_data((i+1)*8-1 downto i*8) <= x"FE";
+ tx_fifo_read_en(i) <= '0';
+ else
+ byte_buffer((i+1)*8-1 downto i*8) <= x"50";
+ byte_waiting(i) <= '1';
+ tx_k(i) <= '1';
+ tx_data((i+1)*8-1 downto i*8) <= x"BC";
+ tx_fifo_read_en(i) <= tx_allow_qtx(i);
+ end if;
+ else --if byte_waiting = '1' then
+ tx_data((i+1)*8-1 downto i*8) <= byte_buffer((i+1)*8-1 downto i*8);
+ tx_k(i) <= send_reset_q(i); --second byte is always data
+ byte_waiting(i) <= '0';
+ tx_fifo_read_en(i) <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ fifo_reset(i) <= reset or quad_rst(0) or not rx_allow(i); --(sync with SYSCLK)
+
+ --RX Control (25)
+ ---------------------
+
+
+
+ THE_FIFO_RX: trb_net_fifo_16bit_bram_dualport
+ generic map(
+ USE_STATUS_FLAGS => c_NO
+ )
+ port map(
+ read_clock_in => clk,
+ write_clock_in => CLK_25,--ff_rxfullclk(i),
+ read_enable_in => rx_fifo_read_en(i),
+ write_enable_in => rx_fifo_write_en(i),
+ fifo_gsr_in => fifo_reset(i),
+ write_data_in => "00" & x"00" & rx_data_reg((i+1)*8-1 downto i*8),
+ read_data_out(7 downto 0) => rx_fifo_dout((i+1)*8-1 downto i*8),
+ full_out => rx_fifo_full(i),
+ empty_out => rx_fifo_empty(i)
+ );
+
+
+-- THE_RX_FIFO: lattice_ecp2m_fifo_8x8_dualport
+-- port map(
+-- Data => rx_data_reg((i+1)*8-1 downto i*8),
+-- WrClock => ff_rxfullclk(i),
+-- RdClock => clk,
+-- WrEn => rx_fifo_write_en(i),
+-- RdEn => rx_fifo_read_en(i),
+-- Reset => fifo_reset(i),
+-- RPReset => fifo_reset(i),
+-- Q => rx_fifo_dout((i+1)*8-1 downto i*8),
+-- Empty => rx_fifo_empty(i),
+-- Full => rx_fifo_full(i)
+-- );
+
+ THE_WRITE_RX_FIFO_PROC: process( CLK_25 )
+ begin
+ if( rising_edge(CLK_25) ) then
+ buf_rx_data((i+1)*8-1 downto i*8) <= rx_data((i+1)*8-1 downto i*8);
+ buf_rx_k(i) <= rx_k(i);
+ if( (reset = '1') or (rx_allow_qrx(i) = '0') ) then
+ rx_fifo_write_en(i) <= '0';
+ is_idle_word(i) <= '1';
+ rx_starting(i) <= '1';
+ else
+ rx_data_reg((i+1)*8-1 downto i*8) <= buf_rx_data((i+1)*8-1 downto i*8);
+ if( (buf_rx_k(i) = '0') and (is_idle_word(i) = '0') and (rx_starting(i) = '0') ) then
+ rx_fifo_write_en(i) <= '1';
+ else
+ rx_fifo_write_en(i) <= '0';
+ end if;
+ if ( buf_rx_k(i) = '1' ) then
+ is_idle_word(i) <= '1';
+ rx_starting(i) <= '0';
+ elsif( (buf_rx_k(i) = '0') and (is_idle_word(i) = '1') ) then
+ is_idle_word(i) <= '0';
+ end if;
+ end if;
+ end if;
+ end process THE_WRITE_RX_FIFO_PROC;
+
+
+ THE_CNT_RESET_PROC : process( CLK_25 )
+ begin
+ if rising_edge(CLK_25) then
+ if reset = '1' then
+ send_reset_words(i) <= '0';
+ make_trbnet_reset(i) <= '0';
+ reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
+ else
+ send_reset_words(i) <= '0';
+ make_trbnet_reset(i) <= '0';
+ if buf_rx_data(i*8+7 downto i*8) = x"FE" and buf_rx_k(i) = '1' then
+ if reset_word_cnt(i*5+4) = '0' then
+ reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1;
+ else
+ send_reset_words(i) <= '1';
+ end if;
+ else
+ reset_word_cnt(i*5+4 downto i*5) <= (others => '0');
+ make_trbnet_reset(i) <= reset_word_cnt(i*5+4);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+--TX Control (100)
+---------------------
+ buf_med_read_out(i) <= not tx_fifo_full(i) and tx_allow_del(i);
+ tx_fifo_write_en(i) <= buf_med_read_out(i) and med_dataready_in(i);
+ tx_fifo_data_in(i*16+15 downto i*16) <= med_data_in(i*16+15 downto i*16);
+ med_read_out(i) <= buf_med_read_out(i);
+
+--RX Control (100)
+---------------------
+ process( clk )
+ begin
+ if( rising_edge(clk) ) then
+ if( reset = '1' ) then
+ buf_med_dataready_out(i) <= '0';
+ byte_select(i) <= '0';
+ last_rx_fifo_read_en(i) <= '0';
+ else
+ last_rx_fifo_read_en(i) <= rx_fifo_read_en(i);
+ last_rx_fifo_empty(i) <= rx_fifo_empty(i);
+ last_last_rx_fifo_read_en(i) <= last_rx_fifo_read_en(i);
+ last_last_rx_fifo_empty(i) <= last_rx_fifo_empty(i);
+ last_rx_fifo_dout(i*8+7 downto i*8) <= rx_fifo_dout(i*8+7 downto i*8);
+ buf_med_dataready_out(i) <= '0';
+ if( (last_last_rx_fifo_empty(i) = '0') and (last_last_rx_fifo_read_en(i) = '1') ) then
+ if( byte_select(i) = '1' ) then
+ buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= last_rx_fifo_dout((i+1)*8-1 downto i*8)
+ & buf_MED_DATA_OUT(i*16+7 downto i*16);
+ buf_MED_DATAREADY_OUT(i) <= '1';
+ else
+ buf_MED_DATA_OUT((i+1)*16-1 downto i*16) <= x"00" & last_rx_fifo_dout((i+1)*8-1 downto i*8);
+ end if;
+ byte_select(i) <= not byte_select(i);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ rx_fifo_read_en(i) <= rx_allow_del(i) and not rx_fifo_empty(i);
+ MED_DATA_OUT((i+1)*16-1 downto i*16) <= buf_MED_DATA_OUT((i+1)*16-1 downto i*16);
+ MED_DATAREADY_OUT(i) <= buf_MED_DATAREADY_OUT(i);
+ MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= rx_counter((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH);
+
+--rx packet counter
+---------------------
+ THE_RX_PACKETS_PROC: process( clk )
+ begin
+ if( rising_edge(clk) ) then
+ if( (reset = '1') or (rx_allow(i) = '0') ) then
+ rx_counter(i*3+2 downto i*3) <= c_H0;
+ else
+ if( buf_med_dataready_out(i) = '1' ) then
+ if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then
+ rx_counter(i*3+2 downto i*3) <= (others => '0');
+ else
+ rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+--Link State machine
+---------------------
+
+
+ CLK_TO_TX_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 4
+ )
+ port map(
+ RESET => reset,
+ D_IN(0) => tx_allow(i),
+ D_IN(1) => lane_rst(i),
+ D_IN(2) => quad_rst(i),
+ D_IN(3) => CTRL_OP(15+i*16),
+ CLK0 => CLK,
+ CLK1 => CLK_25,--ff_txfullclk,
+ D_OUT(0) => tx_allow_qtx(i),
+ D_OUT(1) => lane_rst_qtx(i),
+ D_OUT(2) => quad_rst_qtx(i),
+ D_OUT(3) => send_reset_q(i)
+ );
+
+ TX_TO_CLK_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => reset,
+ D_IN(0) => tx_fifo_valid_read(i),
+ CLK0 => CLK_25,--ff_txfullclk,
+ CLK1 => CLK,
+ D_OUT(0) => tx_fifo_valid_read_q(i)
+ );
+
+
+ LINK_ERROR_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 9
+ )
+ port map(
+ RESET => reset,
+ D_IN(7 downto 0) => link_error(i),
+ D_IN(8) => link_ok(i),
+ CLK0 => CLK_25,--ff_rxfullclk(i),
+ CLK1 => CLK,
+ D_OUT(7 downto 0) => link_error_q(i),
+ D_OUT(8) => link_ok_q(i)
+ );
+
+ SYNC_INPUT_TO_CLK : signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 3
+ )
+ port map(
+ RESET => reset,
+ D_IN(0) => sd(i),
+ D_IN(1) => tx_allow(i),
+ D_IN(2) => rx_allow(i),
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_OUT(0) => sd_q(i),
+ D_OUT(1) => tx_allow_del(i),
+ D_OUT(2) => rx_allow_del(i)
+ );
+
+
+ SYNC_RESET_DETECT_1 : signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 4
+ )
+ port map(
+ RESET => reset,
+ D_IN => send_reset_words,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_OUT => send_reset_words_q
+ );
+
+ SYNC_RESET_DETECT_2 : signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 4
+ )
+ port map(
+ RESET => reset,
+ D_IN => make_trbnet_reset,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_OUT => make_trbnet_reset_q
+ );
+
+ THE_SFP_STATUS_SYNC: signal_sync
+ generic map(
+ DEPTH => 2,
+ WIDTH => 1
+ )
+ port map(
+ RESET => RESET,
+ D_IN(0) => rx_allow(i),
+ CLK0 => CLK,
+ CLK1 => CLK_25,--ff_rxfullclk(i),
+ D_OUT(0) => rx_allow_qrx(i)
+ );
+
+--LED Signals
+---------------------
+ THE_TX_RX_LED_PROC: process( clk )
+ begin
+ if( rising_edge(CLK) ) then
+ if ( buf_med_dataready_out(i) = '1' ) then
+ rx_led(i) <= '1';
+ elsif( led_counter = 0 ) then
+ rx_led(i) <= '0';
+ end if;
+ if( tx_fifo_valid_read_q(i) = '1') then
+ tx_led(i) <= '1';
+ elsif led_counter = 0 then
+ tx_led(i) <= '0';
+ end if;
+ end if;
+ end process;
+
+
+ STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0);
+ STAT_OP(i*16+10) <= rx_led(i);
+ STAT_OP(i*16+11) <= tx_led(i);
+ STAT_OP(i*16+12) <= FSM_STAT_OP(i*16+12);
+ STAT_OP(i*16+13) <= make_trbnet_reset_q(i);
+ STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14);
+ STAT_OP(i*16+15) <= send_reset_words_q(i);
+
+ STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
+ STAT_DEBUG(i*64+39 downto i*64+32) <= buf_rx_data_reg(i*8+7 downto i*8);
+ STAT_DEBUG(i*64+40) <= rx_fifo_write_en(i);
+ STAT_DEBUG(i*64+48 downto i*64+41) <= last_rx_fifo_dout(i*8+7 downto i*8);
+ STAT_DEBUG(i*64+63 downto i*64+49) <= (others => '0');
+
+ PROC_DEBUG_OUT : process(CLK_25)
+ begin
+ if rising_edge(CLK_25) then
+ buf_rx_data_reg <= rx_data_reg;
+ end if;
+ end process;
+
+ end generate;
+
+ PROC_LED_COUNTER : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ led_counter <= led_counter + 1;
+ end if;
+ end process;
+
+ gen_lsm : for i in 0 to 3 generate
+ THE_SFP_LSM: trb_net16_lsm_sfp
+ port map(
+ SYSCLK => CLK,
+ RESET => reset,
+ CLEAR => reset,
+ SFP_MISSING_IN => '0',
+ SFP_LOS_IN => sfp_los(i),
+ SD_LINK_OK_IN => link_ok_q(i),
+ SD_LOS_IN => link_error_q(i)(2),
+ SD_TXCLK_BAD_IN => ffs_plol,
+ SD_RXCLK_BAD_IN => link_error_q(i)(7),
+ SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+ SD_ALIGNMENT_IN => "10",
+ SD_CV_IN(0) => link_error_q(i)(1),
+ SD_CV_IN(1) => '0',
+ FULL_RESET_OUT => quad_rst(i),
+ LANE_RESET_OUT => lane_rst(i),
+ TX_ALLOW_OUT => tx_allow(i),
+ RX_ALLOW_OUT => rx_allow(i),
+ SWAP_BYTES_OUT => open,
+ STAT_OP => FSM_STAT_OP(i*16+15 downto i*16),
+ CTRL_OP => FSM_CTRL_OP(i*16+15 downto i*16),
+ STAT_DEBUG => FSM_STAT_DEBUG(i*32+31 downto i*32)
+ );
+
+ end generate;
+
+ sfp_los <= not sd_q;
+ FSM_CTRL_OP <= CTRL_OP;
+
+
+
+
+
+end architecture;
\ No newline at end of file
jspc29 / trbnet.git / commitdiff