use ieee.numeric_std.all;
library work;
- use work.trb_net_components.all;
- use work.trb_net_std.all;
- use work.trb3_components.all;
- use work.config.all;
entity clock_reset_handler is
port(
);
end entity;
+-- Generates a one time CLEAR pulse at powerup.
+-- RESET is generated each time a reset is done.
+-- 1ms and 1us ticks are generated.
+-- This entity needs to run on the local clock for correct operation.
+
architecture clock_reset_handler_arch of clock_reset_handler is
-signal timer : unsigned(15 downto 0) := (others => '0');
-signal clear_n_i : std_logic;
-signal reset_i : std_logic;
+ signal timer : unsigned(15 downto 0) := (others => '0');
+ signal clear_n_i : std_logic;
+ signal reset_i : std_logic;
-signal ms_counter : unsigned(16 downto 0);
-signal ms_counter_done_x : std_logic;
-signal ms_counter_done : std_logic;
+ signal ms_counter : unsigned(16 downto 0);
+ signal ms_counter_done_x : std_logic;
+ signal ms_counter_done : std_logic;
-signal us_counter : unsigned(6 downto 0);
-signal us_counter_done_x : std_logic;
-signal us_counter_done : std_logic;
+ signal us_counter : unsigned(6 downto 0);
+ signal us_counter_done_x : std_logic;
+ signal us_counter_done : std_logic;
-attribute syn_keep : boolean;
-attribute syn_preserve : boolean;
-attribute syn_keep of clear_n_i : signal is true;
-attribute syn_preserve of clear_n_i : signal is true;
+ attribute syn_keep : boolean;
+ attribute syn_preserve : boolean;
+ attribute syn_keep of clear_n_i : signal is true;
+ attribute syn_preserve of clear_n_i : signal is true;
begin
---------------------------------------------------------------------------
-- 1ms tick counter
---------------------------------------------------------------------------
- THE_MS_COUNTER_PROC: process( CLK_IN )
+ PROC_MS_COUNTER: process( CLK_IN )
begin
if( rising_edge(CLK_IN) ) then
ms_counter_done <= ms_counter_done_x;
ms_counter <= ms_counter - 1;
end if;
end if;
- end process THE_MS_COUNTER_PROC;
+ end process PROC_MS_COUNTER;
ms_counter_done_x <= '1' when (ms_counter = b"0_0000_0000_0000_0000") else '0';
---------------------------------------------------------------------------
-- 1us tick counter
---------------------------------------------------------------------------
- THE_US_COUNTER_PROC: process( CLK_IN )
+ PROC_US_COUNTER: process( CLK_IN )
begin
if( rising_edge(CLK_IN) ) then
us_counter_done <= us_counter_done_x;
us_counter <= us_counter - 1;
end if;
end if;
- end process THE_US_COUNTER_PROC;
+ end process PROC_US_COUNTER;
us_counter_done_x <= '1' when (us_counter = b"000_0000") else '0';
-- Startup timer, generates inital reset
-- this times only runs at powerup!
---------------------------------------------------------------------------
- THE_START_TIMER_PROC: process
+ PROC_START_TIMER: process( CLK_IN )
begin
- wait until rising_edge(CLK_IN);
- if( timer(15) = '1' ) then
- timer <= timer;
- else
- timer <= timer + 1;
+ if( rising_edge(CLK_IN) ) then
+ if( timer(15) = '0' ) then
+ timer <= timer + 1;
+ end if;
end if;
- end process THE_START_TIMER_PROC;
+ end process PROC_START_TIMER;
-- asserted only at power up!
clear_n_i <= timer(15) when rising_edge(CLK_IN);
-
- CLEAR_OUT <= not clear_n_i;
-
- CLEAR_N_OUT <= clear_n_i;
---------------------------------------------------------------------------
-- these resets can be triggered
---------------------------------------------------------------------------
- THE_RESET_HANDLER: entity reset_handler
+ THE_RESET_HANDLER: entity work.reset_handler
port map(
CLEAR_IN => GLOBAL_RESET_IN,
CLEAR_N_IN => clear_n_i,
RESET_OUT => reset_i
);
- RESET_OUT <= reset_i;
- RESET_N_OUT <= not reset_i;
+ RESET_OUT <= reset_i;
+ RESET_N_OUT <= not reset_i;
- LED_RED_OUT <= not GLOBAL_RESET_IN;
- LED_GREEN_OUT <= not reset_i;
+ LED_RED_OUT <= not GLOBAL_RESET_IN;
+ LED_GREEN_OUT <= not reset_i;
+
+ CLEAR_OUT <= not clear_n_i;
+ CLEAR_N_OUT <= clear_n_i;
end architecture clock_reset_handler_arch;
USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.trb_net_std.all;
-use work.trb_net16_hub_func.all;
+--use work.trb_net16_hub_func.all;
package config is
library ieee;\r
-use ieee.std_logic_1164.all;\r
-use ieee.std_logic_arith.all;\r
-use ieee.std_logic_unsigned.all;\r
+ use ieee.std_logic_1164.all;\r
+ use ieee.numeric_std.all;\r
\r
library work;\r
\r
----------------------------------------------------------------\r
-- sample the async reset line and react only on a long pulse\r
----------------------------------------------------------------\r
- THE_ASYNC_SAMPLER_PROC: process( CLK_IN )\r
+ PROC_ASYNC_SAMPLER: process( CLK_IN )\r
begin\r
if( rising_edge(CLK_IN) ) then\r
async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n;\r
async_pulse <= comb_async_pulse;\r
end if;\r
- end process THE_ASYNC_SAMPLER_PROC;\r
+ end process PROC_ASYNC_SAMPLER;\r
\r
-- first two registers are clock domain transfer registers!\r
comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0';\r
----------------------------------------------------------------\r
-- \r
----------------------------------------------------------------\r
- THE_SYNC_PROC: process( CLK_IN )\r
+ PROC_SYNC: process( CLK_IN )\r
begin\r
if( rising_edge(CLK_IN) ) then\r
reset_pulse <= reset_pulse(0) & RESET_IN;\r
end if;\r
- end process THE_SYNC_PROC;\r
+ end process PROC_SYNC;\r
\r
----------------------------------------------------------------\r
-- one global reset counter\r
----------------------------------------------------------------\r
- THE_GLOBAL_RESET_PROC: process( CLK_IN )\r
+ PROC_GLOBAL_RESET: process( CLK_IN )\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( (async_pulse = '1') or (reset_pulse(1) = '1') ) then\r
reset_cnt <= reset_cnt + 1;\r
end if;\r
end if;\r
- end process THE_GLOBAL_RESET_PROC;\r
+ end process PROC_GLOBAL_RESET;\r
\r
--- reset <= not reset_cnt(reset_cnt'left);\r
reset <= not reset_cnt(reset_cnt'left) when rising_edge(CLK_IN);\r
\r
----------------------------------------------------------------\r
####################
-#Packages
+# Packages
add_file -vhdl -lib work "workdir/version.vhd"
add_file -vhdl -lib work "config.vhd"
-add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocols.vhd"
+
#Basic Infrastructure
add_file -vhdl -lib work "../../trb3sc/gbe_hub/reset_handler.vhd"
add_file -vhdl -lib work "../../trb3sc/gbe_hub/clock_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd"
+
#Fifos
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/gbe_tx_reset.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/inserter.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/remover.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_inserter.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_remover.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_rx_rb.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/sgl_ctrl.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_sgl_ctrl.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_main_control.vhd"
add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_mac_control.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_transmit_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/gbe_response_constructor_Forward.vhd"
#add_file -vhdl -lib work "../../trbnet/gbe_trb/base/parser.vhd"
end entity;
-architecture trb3sc_arch of trb3sc_gbe_hub is
+architecture trb3sc_gbe_hub_arch of trb3sc_gbe_hub is
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
-- BUG BUG BUG clk_sys NOT to be used here!
-- generates an adjustable period signal for sending DLMs
-- BUG: better use count down and preload
- THE_DLM_SEND_PROC: process( clk_sys )
+ PROC_DLM_SEND: process( clk_sys, reset_i )
begin
- if( rising_edge(clk_sys) ) then
+ if ( (reset_i = '1') ) then
+ dlm_ctr <= (others => '0');
+ elsif( rising_edge(clk_sys) ) then
inc_dlm_tag <= rst_dlm_ctr;
rst_dlm_ctr <= rst_dlm_ctr_x;
- if( (reset_i = '1') or (rst_dlm_ctr = '1') or (dlm_enable_int = '0') ) then
+ if( (rst_dlm_ctr = '1') or (dlm_enable_int = '0') ) then
dlm_ctr <= (others => '0');
elsif( dlm_enable_int = '1' ) then
dlm_ctr <= dlm_ctr + 1;
end if;
end if;
- end process THE_DLM_SEND_PROC;
+ end process PROC_DLM_SEND;
rst_dlm_ctr_x <= '1' when ((std_logic_vector(dlm_ctr) = dlm_period_int) and (dlm_enable_int = '1')) else '0';
-- DLM "tag" for blinking LEDs :)
- THE_DLM_TAG_CTR_PROC: process( clk_sys )
+ PROC_DLM_TAG_CTR: process( clk_sys )
begin
- if( rising_edge(clk_sys) ) then
- if( (reset_i = '1') or (dlm_enable_int = '0') ) then
+ if ( (reset_i = '1') ) then
+ dlm_tag_ctr <= (others => '0');
+ elsif( rising_edge(clk_sys) ) then
+ if( (dlm_enable_int = '0') ) then
dlm_tag_ctr <= (others => '0');
elsif( inc_dlm_tag = '1' ) then
dlm_tag_ctr <= dlm_tag_ctr + 1;
end if;
end if;
- end process THE_DLM_TAG_CTR_PROC;
+ end process PROC_DLM_TAG_CTR;
-- we use received information unless switched to local
dlm_inject_int <= rst_dlm_ctr when dlm_enable_int = '1' else dlm_rx_int;
---------------------------------------------------------------------------
-- FiFo controller
---------------------------------------------------------------------------
- THE_SGL_CTRL: entity sgl_ctrl
+ THE_GBE_SGL_CTRL: entity gbe_sgl_ctrl
port map(
CLK => master_clk,
RESET => reset_i,
---------------------------------------------------------------------------
-- Multiplexers for data streams
---------------------------------------------------------------------------
- THE_PIPELINING: for I in 0 to 9 generate
+ GEN_PIPELINING: for I in 0 to 9 generate
dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(master_clk);
- end generate THE_PIPELINING;
+ end generate GEN_PIPELINING;
- THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q )
+ PROC_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q )
begin
case dl_rx_port_mux is
when x"0" => switch_rx_data <= dl_rx_data_q(0);
when x"9" => switch_rx_data <= dl_rx_data_q(9);
when others => switch_rx_data <= (others => '0');
end case;
- end process THE_DL_RX_MUX;
+ end process PROC_DL_RX_MUX;
ul_tx_data <= switch_rx_data when ul_tx_port_sel = '1' else local_rx_data;
-- 8 : fifo_eof
-- 7..0: data
--- DBG(15 downto 0) <= debug_pcsd(15 downto 0);
DBG(31 downto 0) <= debug_pcsd(31 downto 0);
--- DBG(31 downto 16) <= debug_pcsc(111 downto 96);
DBG(32) <= '0';
DBG(33) <= master_clk;
---------------------------------------------------------------------------
-- GbE wrapper without med interface
---------------------------------------------------------------------------
- GBE : entity work.gbe_wrapper_fifo
+ THE_GBE_WRAPPER_FIFO : entity work.gbe_wrapper_fifo
generic map(
LINK_HAS_SLOWCTRL => '1',
LINK_HAS_DHCP => '1',
-------------------------------------------------------------------------------
-- SCTRL endpoint for GbE standalone
-------------------------------------------------------------------------------
- THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
+ THE_SCTRL_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl
generic map(
FIFO_TO_INT_DEPTH => 6,
FIFO_TO_APL_DEPTH => 6,
---------------------------------------------------------------------------
-- RSL for TX of SerDes, based on extRSL logic
---------------------------------------------------------------------------
- THE_MAIN_TX_RST: main_tx_reset_RS
+ THE_GBE_TX_RESET: entity gbe_tx_reset
port map (
CLEAR => clear_i,
CLK_REF => clk_sys,
LED_RJ_GREEN(0) <= not status_raw(0 * 8 + 7); -- A0
LED_RJ_RED(0) <= not status_raw(0 * 8 + 2);
-end architecture;
+end architecture trb3sc_gbe_hub_arch;
jspc29 / trb3sc.git / commitdiff