*** empty log message ***

diff --git a/cts.tex b/cts.tex
index 60acccb2ba1d6eb48bfa54ba538e03082df3d0c2..f5da192ae3c54efad4b2831592d5179b0545808c 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -8,6 +8,7 @@
 
 Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1) \\
 Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2) \\
+
 Register addresses from 0xA100 to 0xA100 + 26*500 (500 is number of samples per beam structure), the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}. First 8 is START next 8 is also START but perpendicular stripes. Next 8 is Veto and for the last two the source is selected by 0xA0C2 register.
 
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diff --git a/slowcontrol.tex b/slowcontrol.tex
index 88b956d2da584015df9bea11b311966987cc28dd..95fb3d694965bcd4e2ddae7dc3c55482a98986f0 100755 (executable)
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -488,7 +488,8 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}.
 29       & invert timing trigger \\
 28       & Single Event Upset Detection enable \\
 27       & Enable error correction in media interface \\
-26 -- 24 & reserved \\
+26       & Enable automatic reboot at network reset \\
+25 -- 24 & reserved \\
 23 -- 20 & data format \\
 19 -- 16 & reserved \\
 15 -- 0  & enable frontends \\