]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
change size of memory for circullar buffer.
authorTobias Weber <toweber86@gmail.com>
Thu, 30 Aug 2018 08:05:52 +0000 (10:05 +0200)
committerTobias Weber <toweber86@gmail.com>
Thu, 30 Aug 2018 08:05:52 +0000 (10:05 +0200)
mupix/Mupix8/cores/RAM_DP_8192_32.ipx [new file with mode: 0644]
mupix/Mupix8/cores/RAM_DP_8192_32.lpc [new file with mode: 0644]
mupix/Mupix8/cores/RAM_DP_8192_32.vhd [new file with mode: 0644]

diff --git a/mupix/Mupix8/cores/RAM_DP_8192_32.ipx b/mupix/Mupix8/cores/RAM_DP_8192_32.ipx
new file mode 100644 (file)
index 0000000..cbe011c
--- /dev/null
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="RAM_DP_8192_32" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2018 08 29 14:00:19.499" version="6.5" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+               <File name="" type="mem" modified="2018 08 29 14:00:19.000"/>
+               <File name="RAM_DP_8192_32.lpc" type="lpc" modified="2018 08 29 14:00:17.000"/>
+               <File name="RAM_DP_8192_32.vhd" type="top_level_vhdl" modified="2018 08 29 14:00:17.000"/>
+               <File name="RAM_DP_8192_32_tmpl.vhd" type="template_vhdl" modified="2018 08 29 14:00:17.000"/>
+               <File name="tb_RAM_DP_8192_32_tmpl.vhd" type="testbench_vhdl" modified="2018 08 29 14:00:17.000"/>
+  </Package>
+</DiamondModule>
diff --git a/mupix/Mupix8/cores/RAM_DP_8192_32.lpc b/mupix/Mupix8/cores/RAM_DP_8192_32.lpc
new file mode 100644 (file)
index 0000000..9b3148d
--- /dev/null
@@ -0,0 +1,56 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.5
+ModuleName=RAM_DP_8192_32
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/29/2018
+Time=14:00:17
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=8192
+RData=32
+WAddress=8192
+WData=32
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=0
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
+
+[FilesGenerated]
+=mem
+
+[Command]
+cmd_line= -w -n RAM_DP_8192_32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 13 -rwidth 32 -waddr_width 13 -wwidth 32 -rnum_words 8192 -wnum_words 8192 -cascade -1
diff --git a/mupix/Mupix8/cores/RAM_DP_8192_32.vhd b/mupix/Mupix8/cores/RAM_DP_8192_32.vhd
new file mode 100644 (file)
index 0000000..de8369a
--- /dev/null
@@ -0,0 +1,850 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.1.502
+-- Module  Version: 6.5
+--/opt/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n RAM_DP_8192_32 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 8192 -cascade -1 
+
+-- Wed Aug 29 14:00:17 2018
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity RAM_DP_8192_32 is
+    port (
+        WrAddress: in  std_logic_vector(12 downto 0); 
+        RdAddress: in  std_logic_vector(12 downto 0); 
+        Data: in  std_logic_vector(31 downto 0); 
+        WE: in  std_logic; 
+        RdClock: in  std_logic; 
+        RdClockEn: in  std_logic; 
+        Reset: in  std_logic; 
+        WrClock: in  std_logic; 
+        WrClockEn: in  std_logic; 
+        Q: out  std_logic_vector(31 downto 0));
+end RAM_DP_8192_32;
+
+architecture Structure of RAM_DP_8192_32 is
+
+    -- internal signal declarations
+    signal scuba_vhi: std_logic;
+    signal scuba_vlo: std_logic;
+
+    -- local component declarations
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component DP16KC
+        generic (GSR : in String; WRITEMODE_B : in String; 
+                WRITEMODE_A : in String; CSDECODE_B : in String; 
+                CSDECODE_A : in String; REGMODE_B : in String; 
+                REGMODE_A : in String; DATA_WIDTH_B : in Integer; 
+                DATA_WIDTH_A : in Integer);
+        port (DIA0: in  std_logic; DIA1: in  std_logic; 
+            DIA2: in  std_logic; DIA3: in  std_logic; 
+            DIA4: in  std_logic; DIA5: in  std_logic; 
+            DIA6: in  std_logic; DIA7: in  std_logic; 
+            DIA8: in  std_logic; DIA9: in  std_logic; 
+            DIA10: in  std_logic; DIA11: in  std_logic; 
+            DIA12: in  std_logic; DIA13: in  std_logic; 
+            DIA14: in  std_logic; DIA15: in  std_logic; 
+            DIA16: in  std_logic; DIA17: in  std_logic; 
+            ADA0: in  std_logic; ADA1: in  std_logic; 
+            ADA2: in  std_logic; ADA3: in  std_logic; 
+            ADA4: in  std_logic; ADA5: in  std_logic; 
+            ADA6: in  std_logic; ADA7: in  std_logic; 
+            ADA8: in  std_logic; ADA9: in  std_logic; 
+            ADA10: in  std_logic; ADA11: in  std_logic; 
+            ADA12: in  std_logic; ADA13: in  std_logic; 
+            CEA: in  std_logic; CLKA: in  std_logic; OCEA: in  std_logic; 
+            WEA: in  std_logic; CSA0: in  std_logic; CSA1: in  std_logic; 
+            CSA2: in  std_logic; RSTA: in  std_logic; 
+            DIB0: in  std_logic; DIB1: in  std_logic; 
+            DIB2: in  std_logic; DIB3: in  std_logic; 
+            DIB4: in  std_logic; DIB5: in  std_logic; 
+            DIB6: in  std_logic; DIB7: in  std_logic; 
+            DIB8: in  std_logic; DIB9: in  std_logic; 
+            DIB10: in  std_logic; DIB11: in  std_logic; 
+            DIB12: in  std_logic; DIB13: in  std_logic; 
+            DIB14: in  std_logic; DIB15: in  std_logic; 
+            DIB16: in  std_logic; DIB17: in  std_logic; 
+            ADB0: in  std_logic; ADB1: in  std_logic; 
+            ADB2: in  std_logic; ADB3: in  std_logic; 
+            ADB4: in  std_logic; ADB5: in  std_logic; 
+            ADB6: in  std_logic; ADB7: in  std_logic; 
+            ADB8: in  std_logic; ADB9: in  std_logic; 
+            ADB10: in  std_logic; ADB11: in  std_logic; 
+            ADB12: in  std_logic; ADB13: in  std_logic; 
+            CEB: in  std_logic; CLKB: in  std_logic; OCEB: in  std_logic; 
+            WEB: in  std_logic; CSB0: in  std_logic; CSB1: in  std_logic; 
+            CSB2: in  std_logic; RSTB: in  std_logic; 
+            DOA0: out  std_logic; DOA1: out  std_logic; 
+            DOA2: out  std_logic; DOA3: out  std_logic; 
+            DOA4: out  std_logic; DOA5: out  std_logic; 
+            DOA6: out  std_logic; DOA7: out  std_logic; 
+            DOA8: out  std_logic; DOA9: out  std_logic; 
+            DOA10: out  std_logic; DOA11: out  std_logic; 
+            DOA12: out  std_logic; DOA13: out  std_logic; 
+            DOA14: out  std_logic; DOA15: out  std_logic; 
+            DOA16: out  std_logic; DOA17: out  std_logic; 
+            DOB0: out  std_logic; DOB1: out  std_logic; 
+            DOB2: out  std_logic; DOB3: out  std_logic; 
+            DOB4: out  std_logic; DOB5: out  std_logic; 
+            DOB6: out  std_logic; DOB7: out  std_logic; 
+            DOB8: out  std_logic; DOB9: out  std_logic; 
+            DOB10: out  std_logic; DOB11: out  std_logic; 
+            DOB12: out  std_logic; DOB13: out  std_logic; 
+            DOB14: out  std_logic; DOB15: out  std_logic; 
+            DOB16: out  std_logic; DOB17: out  std_logic);
+    end component;
+    attribute MEM_LPC_FILE : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute RESETMODE : string; 
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_0_15 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_0_15 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_0_15 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_1_14 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_1_14 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_1_14 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_2_13 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_2_13 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_2_13 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_3_12 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_3_12 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_3_12 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_4_11 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_4_11 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_4_11 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_5_10 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_5_10 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_5_10 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_6_9 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_6_9 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_6_9 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_7_8 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_7_8 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_7_8 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_8_7 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_8_7 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_8_7 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_9_6 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_9_6 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_9_6 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_10_5 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_10_5 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_10_5 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_11_4 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_11_4 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_11_4 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_12_3 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_12_3 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_12_3 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_13_2 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_13_2 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_13_2 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_14_1 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_14_1 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_14_1 : label is "SYNC";
+    attribute MEM_LPC_FILE of RAM_DP_8192_32_0_15_0 : label is "RAM_DP_8192_32.lpc";
+    attribute MEM_INIT_FILE of RAM_DP_8192_32_0_15_0 : label is "";
+    attribute RESETMODE of RAM_DP_8192_32_0_15_0 : label is "SYNC";
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    RAM_DP_8192_32_0_0_15: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(1), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>open, DOB3=>open, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    RAM_DP_8192_32_0_1_14: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(3), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(2), DOB1=>Q(3), DOB2=>open, DOB3=>open, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    RAM_DP_8192_32_0_2_13: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(5), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(4), DOB1=>Q(5), DOB2=>open, DOB3=>open, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    RAM_DP_8192_32_0_3_12: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(7), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(6), DOB1=>Q(7), DOB2=>open, DOB3=>open, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    RAM_DP_8192_32_0_4_11: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(9), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(8), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(8), DOB1=>Q(9), DOB2=>open, DOB3=>open, 
+            DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, 
+            DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, 
+            DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, 
+            DOB17=>open);
+
+    RAM_DP_8192_32_0_5_10: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(11), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(10), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(10), DOB1=>Q(11), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_6_9: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(13), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(12), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(12), DOB1=>Q(13), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_7_8: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(15), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(14), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(14), DOB1=>Q(15), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_8_7: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(17), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(16), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(16), DOB1=>Q(17), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_9_6: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(19), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(18), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(18), DOB1=>Q(19), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_10_5: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(21), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(20), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(20), DOB1=>Q(21), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_11_4: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(23), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(22), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(22), DOB1=>Q(23), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_12_3: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(25), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(24), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(24), DOB1=>Q(25), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_13_2: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(27), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(26), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(26), DOB1=>Q(27), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    RAM_DP_8192_32_0_14_1: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(29), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(28), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(28), DOB1=>Q(29), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    RAM_DP_8192_32_0_15_0: DP16KC
+        generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", 
+        WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", 
+        REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=>  2, 
+        DATA_WIDTH_A=>  2)
+        port map (DIA0=>scuba_vlo, DIA1=>Data(31), DIA2=>scuba_vlo, 
+            DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo, 
+            DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, 
+            DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(30), 
+            DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, 
+            DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, 
+            ADA0=>scuba_vlo, ADA1=>WrAddress(0), ADA2=>WrAddress(1), 
+            ADA3=>WrAddress(2), ADA4=>WrAddress(3), ADA5=>WrAddress(4), 
+            ADA6=>WrAddress(5), ADA7=>WrAddress(6), ADA8=>WrAddress(7), 
+            ADA9=>WrAddress(8), ADA10=>WrAddress(9), 
+            ADA11=>WrAddress(10), ADA12=>WrAddress(11), 
+            ADA13=>WrAddress(12), CEA=>WrClockEn, CLKA=>WrClock, 
+            OCEA=>WrClockEn, WEA=>WE, CSA0=>scuba_vlo, CSA1=>scuba_vlo, 
+            CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, 
+            DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, 
+            DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, 
+            DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, 
+            DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, 
+            DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, 
+            DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, 
+            ADB1=>RdAddress(0), ADB2=>RdAddress(1), ADB3=>RdAddress(2), 
+            ADB4=>RdAddress(3), ADB5=>RdAddress(4), ADB6=>RdAddress(5), 
+            ADB7=>RdAddress(6), ADB8=>RdAddress(7), ADB9=>RdAddress(8), 
+            ADB10=>RdAddress(9), ADB11=>RdAddress(10), 
+            ADB12=>RdAddress(11), ADB13=>RdAddress(12), CEB=>RdClockEn, 
+            CLKB=>RdClock, OCEB=>RdClockEn, WEB=>scuba_vlo, 
+            CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, 
+            RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, 
+            DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, 
+            DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, 
+            DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, 
+            DOA17=>open, DOB0=>Q(30), DOB1=>Q(31), DOB2=>open, 
+            DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, 
+            DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, 
+            DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
+            DOB16=>open, DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of RAM_DP_8192_32 is
+    for Structure
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:DP16KC use entity ecp3.DP16KC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on