*** empty log message ***

diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd
index f1427c5b1db2f7f86adf51177535968ea5d55464..a1f1888bf324c6c4ace2f6b145455f9fe067cbc2 100644 (file)
--- a/design/mdc_oepb_pack.vhd
+++ b/design/mdc_oepb_pack.vhd
@@ -122,222 +122,14 @@ component mdc_addon_daq_bus_0
       LED_GOOD_OUT            : out std_logic);
   end component;
 
-  component pll_in25_out100 is
-    port (
-      CLK: in std_logic;
-      CLKOP: out std_logic;
-      LOCK: out std_logic
-      );
-  end component;
-
-  component trb_net16_med_ecp_fot is
-    port(
-      CLK    : in std_logic;
-      CLK_25 : in std_logic;
-      CLK_EN : in std_logic;
-      RESET  : in std_logic;
-
-      --Internal Connection
-      MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      MED_DATAREADY_IN   : in  std_logic;
-      MED_READ_OUT       : out std_logic;
-      MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-      MED_DATAREADY_OUT  : out std_logic;
-      MED_READ_IN        : in  std_logic;
-
-      --SFP Connection
-      TXP : out std_logic;
-      TXN : out std_logic;
-      RXP : in  std_logic;
-      RXN : in  std_logic;
-      SD  : in  std_logic;
-
-      -- Status and control port
-      STAT_OP            : out  std_logic_vector (15 downto 0);
-      CTRL_OP            : in  std_logic_vector (15 downto 0);
-      STAT_DEBUG         : out  std_logic_vector (63 downto 0);
-      CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
-      );
-  end component;
-
-  component adc_ltc2308_readout is
-    generic(
-      CLOCK_FREQUENCY : integer := 100 --MHz
-      );
-    port(
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
-
-      ADC_SCK       : out std_logic;
-      ADC_SDI       : out std_logic;
-      ADC_SDO       : in  std_logic;
-      ADC_CONVST    : out std_logic;
-
-      DAT_ADDR_IN          : in  std_logic_vector(5 downto 0);
-      DAT_READ_EN_IN       : in  std_logic;
-      DAT_WRITE_EN_IN      : in  std_logic;
-      DAT_DATA_OUT         : out std_logic_vector(31 downto 0);
-      DAT_DATA_IN          : in  std_logic_vector(31 downto 0);
-      DAT_DATAREADY_OUT    : out std_logic;
-      DAT_NO_MORE_DATA_OUT : out std_logic;
-      DAT_WRITE_ACK_OUT    : out std_logic;
-      DAT_UNKNOWN_ADDR_OUT : out std_logic;
-      DAT_TIMEOUT_IN       : in  std_logic;
-
-      STAT_VOLTAGES_OUT    : out std_logic_vector(31 downto 0)
-      );
-  end component;
-
-  component trb_net16_endpoint_hades_full is
-    generic (
-      USE_CHANNEL                  : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
-      IBUF_DEPTH                   : channel_config_t := (1,6,6,6);
-      FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
-      FIFO_TO_APL_DEPTH            : channel_config_t := (1,1,1,1);
-      IBUF_SECURE_MODE             : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      API_SECURE_MODE_TO_APL       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      API_SECURE_MODE_TO_INT       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
-      INIT_CAN_SEND_DATA           : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-      REPLY_CAN_SEND_DATA          : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-      REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-      USE_CHECKSUM                 : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
-      APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-      BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
-      REGIO_NUM_STAT_REGS      : integer range 0 to 6 := 3; --log2 of number of status registers
-      REGIO_NUM_CTRL_REGS      : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-      --standard values for output registers
-      REGIO_INIT_CTRL_REGS     : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0');
-      --set to 0 for unused ctrl registers to save resources
-      REGIO_USED_CTRL_REGS     : std_logic_vector(2**(3)-1 downto 0)    := "00000001";
-      --set to 0 for each unused bit in a register
-      REGIO_USED_CTRL_BITMASK  : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1');
-      REGIO_USE_DAT_PORT       : integer range 0 to 1 := c_YES;  --internal data port
-      REGIO_INIT_ADDRESS       : std_logic_vector(15 downto 0) := x"FFFF";
-      REGIO_INIT_UNIQUE_ID     : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-      REGIO_INIT_BOARD_INFO    : std_logic_vector(31 downto 0) := x"1111_2222";
-      REGIO_INIT_ENDPOINT_ID   : std_logic_vector(15 downto 0) := x"0001";
-      REGIO_COMPILE_TIME       : std_logic_vector(31 downto 0) := x"00000000";
-      REGIO_COMPILE_VERSION    : std_logic_vector(15 downto 0) := x"0001";
-      REGIO_HARDWARE_VERSION   : std_logic_vector(31 downto 0) := x"12345678";
-      REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR
-      CLOCK_FREQUENCY          : integer range 1 to 200 := 100
-      );
 
-    port(
-      --  Misc
-      CLK    : in std_logic;
-      RESET  : in std_logic;
-      CLK_EN : in std_logic;
 
-      --  Media direction port
-      MED_DATAREADY_OUT  : out std_logic;
-      MED_DATA_OUT       : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_IN        : in  std_logic;
-
-      MED_DATAREADY_IN   : in  std_logic;
-      MED_DATA_IN        : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-      MED_PACKET_NUM_IN  : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-      MED_READ_OUT       : out std_logic;
-
-      MED_STAT_OP_IN     : in  std_logic_vector(15 downto 0);
-      MED_CTRL_OP_OUT    : out std_logic_vector(15 downto 0);
-
-      -- LVL1 trigger APL
-      LVL1_TRG_TYPE_OUT      : out std_logic_vector(3 downto 0);
-      LVL1_TRG_RECEIVED_OUT  : out std_logic;
-      LVL1_TRG_NUMBER_OUT    : out std_logic_vector(15 downto 0);
-      LVL1_TRG_CODE_OUT      : out std_logic_vector(7 downto 0);
-      LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0);
-      LVL1_ERROR_PATTERN_IN  : in  std_logic_vector(31 downto 0) := x"00000000";
-      LVL1_TRG_RELEASE_IN    : in  std_logic := '0';
-
-
-      --Data Port
-      IPU_NUMBER_OUT       : out std_logic_vector (15 downto 0);
-      IPU_INFORMATION_OUT  : out std_logic_vector (7 downto 0);
-      --start strobe
-      IPU_START_READOUT_OUT: out std_logic;
-      --detector data, equipped with DHDR
-      IPU_DATA_IN          : in  std_logic_vector (31 downto 0);
-      IPU_DATAREADY_IN     : in  std_logic;
-      --no more data, end transfer, send TRM
-      IPU_READOUT_FINISHED_IN : in  std_logic;
-      --will be low every second cycle due to 32bit -> 16bit conversion
-      IPU_READ_OUT         : out std_logic;
-      IPU_LENGTH_IN        : in  std_logic_vector (15 downto 0);
-      IPU_ERROR_PATTERN_IN : in  std_logic_vector (31 downto 0);
-
-
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-      REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-      REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-      REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-      --following ports only used when using internal data port
-      REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
-      REGIO_READ_ENABLE_OUT     : out std_logic;
-      REGIO_WRITE_ENABLE_OUT    : out std_logic;
-      REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
-      REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
-      REGIO_DATAREADY_IN        : in  std_logic := '0';
-      REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
-      REGIO_WRITE_ACK_IN        : in  std_logic := '0';
-      REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
-      REGIO_TIMEOUT_OUT         : out std_logic;
-      --IDRAM is used if no 1-wire interface, onewire used otherwise
-      REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
-      REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-      REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
-      REGIO_IDRAM_WR_IN         : in  std_logic := '0';
-      REGIO_ONEWIRE_INOUT       : inout std_logic;
-      REGIO_ONEWIRE_MONITOR_IN  : in  std_logic;
-      REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
-
-      TRIGGER_MONITOR_IN        : in  std_logic;  --strobe when timing trigger received
-      GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
-      LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
-      TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
-      TIMER_US_TICK_OUT         : out std_logic;  --1 tick every microsecond
-
-      --Debugging & Status information
-      STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
-      STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
-      STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
-      MED_STAT_OP               : out std_logic_vector (15 downto 0);
-      CTRL_MPLEX                : in  std_logic_vector (31 downto 0);
-      IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0);
-      STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
-      STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0)
-      );
-  end component;
-
-  component ram_dp is
-    generic(
-      depth : integer := 3;
-      width : integer := 16
-      );
-    port(
-      CLK   : in  std_logic;
-      wr1   : in  std_logic;
-      a1    : in  std_logic_vector(depth-1 downto 0);
-      dout1 : out std_logic_vector(width-1 downto 0);
-      din1  : in  std_logic_vector(width-1 downto 0);
-      a2    : in  std_logic_vector(depth-1 downto 0);
-      dout2 : out std_logic_vector(width-1 downto 0)
-      );
+  component edge_to_pulse
+    port (
+      CLOCK         : in  std_logic;
+      ENABLE_CLK_IN : in  std_logic;
+      SIGNAL_IN     : in  std_logic;
+      PULSE_OUT     : out std_logic);
   end component;
 
-component edge_to_pulse
-  port (
-    CLOCK         : in  std_logic;
-    ENABLE_CLK_IN : in  std_logic;
-    SIGNAL_IN     : in  std_logic;
-    PULSE_OUT     : out std_logic);
-end component;
-
 end package mdc_oepb_pack;

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index 42cc7b74a5cf9456e39d130d321314825b2765d3..98129038ac68ec1dd72d959886a571672c692cea 100644 (file)
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -5,6 +5,7 @@ USE IEEE.numeric_std.ALL;
 library work;
 use work.trb_net_std.all;
 use work.mdc_oepb_pack.all;
+use work.trb_net_components.all;
 use work.version.all;
 
 entity mdc_oepb is
@@ -154,7 +155,7 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal direction_data_line_in_i : std_logic_vector(3 downto 0);
   signal motherboard_type_in_i : std_logic_vector(3 downto 0);
   signal pulse_begin_run_trigger_i : std_logic;
-  
+
 begin
 ---------------------------------------------------------------------
 -- PLL: 100 MHz
@@ -500,10 +501,10 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
 ---------------------------------------------------------------------
 -- 0xc0 0x0011 -> send begrun trigger to 1 short
 -- 0xc0 0x0021 -> send begrun trigger to 1 long
--- 0xc0 0x0C10 -> x"C" set calibration trigger, x"0" normal 
+-- 0xc0 0x0C10 -> x"C" set calibration trigger, x"0" normal
 -- 0xc0 0x1000 -> send NORMAL trigger
 -- 0xc0 0x1C00 -> send CALIBRATION trigger
-  
+
   PROC_GEN_TIMING : process(CLK_100)
     begin
       if rising_edge(CLK_100) then
@@ -512,7 +513,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
  --       pulse_begin_run_trigger_i <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
 
 --FEE definition
-        motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);  
+        motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);
         cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8);
 
       end if;