more description

diff --git a/cts.tex b/cts.tex
index 1a79340ee53948787c60a307d6c31d8cce83301d..04219df1c7add314be96a6f7c33dc0fafba609c5 100644 (file)
--- a/cts.tex
+++ b/cts.tex
@@ -45,10 +45,10 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic}
     \end{description}
   \item [0xA0C4 -- 0xA0C3] Enable inputs (order as on the  Fig.\ref{cts_logic})
   \item [0xA0C6 -- 0xA0C5] TS gating disable
-  \item [0xA0C8 -- 0xA0C7] Enable outputs
-  \item [0xA0D0 -- 0xA0C9] Downscale registers
-  \item [0xA0D8 -- 0xA0D1] Delay registers
-  \item [0xA0E0 -- 0xA0D9] Width registers
+  \item [0xA0C8 -- 0xA0C7] Enable outputs 
+  \item [0xA0D0 -- 0xA0C9] Downscale registers - $2^{value}$
+  \item [0xA0D8 -- 0xA0D1] Delay registers - $value * 1,25\,ns$
+  \item [0xA0E0 -- 0xA0D9] Width registers - $1,25 + value * 1,25\,ns$
   \item [0xA0E1] LVL2 EB IP table
     \begin{description}
      \item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected