Disabled unused ports on trb_hub.

All SYSCLK now to rx_half_clk, except SPI_RELOAD !!
Minor clock rename in media_interface

diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd
index d7fbf0a382c6800f84196b0b94e9ece52b390af3..33e14899201912ae7b1dff1135bd4e4efdfa5fa9 100644 (file)
--- a/code/med_ecp3_sfp_4_sync_down.vhd
+++ b/code/med_ecp3_sfp_4_sync_down.vhd
@@ -471,7 +471,7 @@ generated_logic     : for i in 0 to 3 generate
        -------------------------------------------------             
        THE_RX_CONTROL : rx_control
        port map(
-               CLK_200                        => rx_full_clk(i),       --clk_200_i(i), --PL!
+               CLK_200                        => clk_200_txdata,       --clk_200_i(i), --PL!
                CLK_100                        => SYSCLK,
                RESET_IN                       => rst(i),               --CLEAR, PL!
 

diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd
index 353c15f10edd2255c9f92737419e7f8af2a7e477..99cce96aba9559b5ea0ef25fc7f12fcf66cc8593 100644 (file)
--- a/code/med_ecp3_sfp_sync_up.vhd
+++ b/code/med_ecp3_sfp_sync_up.vhd
@@ -98,10 +98,10 @@ end component;
 --signal clk_200_i         : std_logic;
 --signal clk_200_internal  : std_logic;
 signal clk_200_osc         : std_logic;
-signal rx_full_clk_ch3         : std_logic;
-signal rx_half_clk_ch3         : std_logic;
-signal tx_full_clk_ch3         : std_logic;
-signal tx_half_clk_ch3         : std_logic;
+signal rx_full_clk             : std_logic;
+signal rx_half_clk             : std_logic;
+signal tx_full_clk             : std_logic;
+signal tx_half_clk             : std_logic;
 
 signal tx_data           : std_logic_vector(7 downto 0);
 signal tx_k              : std_logic;
@@ -199,10 +199,10 @@ begin
 
 clk_200_osc                    <= OSCCLK;
 
-RX_HALF_CLK_OUT        <= rx_half_clk_ch3;
-RX_FULL_CLK_OUT        <= rx_full_clk_ch3;
-TX_HALF_CLK_OUT        <= tx_half_clk_ch3;
-TX_FULL_CLK_OUT        <= tx_full_clk_ch3;\r
+RX_HALF_CLK_OUT        <= rx_half_clk;
+RX_FULL_CLK_OUT        <= rx_full_clk;
+TX_HALF_CLK_OUT        <= tx_half_clk;
+TX_FULL_CLK_OUT        <= tx_full_clk;\r
 RX_CDR_LOL_OUT         <= rx_cdr_lol;          -- !PL14082014
 
 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
@@ -216,7 +216,7 @@ rst                                 <=              (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigg
 
 
 --gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
---  clk_200_i        <= rx_full_clk_ch3;
+--  clk_200_i        <= rx_full_clk;
 --end generate;
 
 --gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
@@ -233,11 +233,11 @@ THE_SERDES : entity work.serdes_sync_upstream
     hdinn_ch3            => SD_RXD_N_IN,
     hdoutp_ch3           => SD_TXD_P_OUT,
     hdoutn_ch3           => SD_TXD_N_OUT,
-    txiclk_ch3           => rx_full_clk_ch3,   --clk_200_i,
-    rx_full_clk_ch3      => rx_full_clk_ch3,
-    rx_half_clk_ch3      => rx_half_clk_ch3,
-    tx_full_clk_ch3      => tx_full_clk_ch3,
-    tx_half_clk_ch3      => tx_half_clk_ch3,
+    txiclk_ch3           => rx_full_clk,       --clk_200_i,
+    rx_full_clk_ch3      => rx_full_clk,
+    rx_half_clk_ch3      => rx_half_clk,
+    tx_full_clk_ch3      => tx_full_clk,
+    tx_half_clk_ch3      => tx_half_clk,
     fpga_rxrefclk_ch3    => clk_200_osc,       --clk_200_internal,
     txdata_ch3           => tx_data,
     tx_k_ch3             => tx_k,
@@ -268,7 +268,7 @@ THE_SERDES : entity work.serdes_sync_upstream
     SCI_RD               => sci_read_i,
     SCI_WRN              => sci_write_i,
     
-    fpga_txrefclk        => rx_full_clk_ch3,   --clk_200_osc,  --clk_200_i,
+    fpga_txrefclk        => rx_full_clk,       --clk_200_osc,  --clk_200_i,
     tx_serdes_rst_c      => tx_serdes_rst,
     tx_pll_lol_qd_s      => tx_pll_lol,
     rst_qd_c             => rst_qd,
@@ -295,7 +295,7 @@ THE_RX_FSM : rx_reset_fsm
 THE_TX_FSM : tx_reset_fsm
   port map(
     RST_N           => rst_n,
-    TX_REFCLK       => rx_full_clk_ch3,        --clk_200_osc,  --clk_200_internal,                     -- allways running PL! 18-06 was clk_200_i
+    TX_REFCLK       => rx_full_clk,    --clk_200_osc,  --clk_200_internal,                     -- allways running PL! 18-06 was clk_200_i
     TX_PLL_LOL_QD_S => tx_pll_lol,
     RST_QD_C        => rst_qd,
     TX_PCS_RST_CH_C => tx_pcs_rst,
@@ -308,7 +308,7 @@ wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
 
 --Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
 PROC_ALLOW : process begin
-  wait until rising_edge(rx_full_clk_ch3);     --clk_200_osc); --clk_200_i);
+  wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);
   if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
     rx_allow <= '1';
   else
@@ -325,9 +325,9 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK);
 tx_allow_q <= tx_allow when rising_edge(SYSCLK);
 
 
-PROC_START_TIMER : process(rx_full_clk_ch3)    --clk_200_osc)  --clk_200_i)
+PROC_START_TIMER : process(rx_full_clk)        --clk_200_osc)  --clk_200_i)
 begin
-       if rising_edge(rx_full_clk_ch3) then --clk_200_osc) then
+       if rising_edge(rx_full_clk)     then --clk_200_osc) then
                if got_link_ready_i = '1' then
                        watchdog_timer  <= (others => '0');
                        if start_timer(start_timer'left) = '0' then
@@ -353,7 +353,7 @@ end process;
 -------------------------------------------------         
 THE_TX : soda_tx_control
        port map(
-               CLK_200                                         => rx_full_clk_ch3,     --clk_200_osc,  --clk_200_i,
+               CLK_200                                         => rx_full_clk, --clk_200_osc,  --clk_200_i,
                CLK_100                                         => SYSCLK,
                RESET_IN                                                => rst,         --CLEAR, PL!
 
@@ -390,7 +390,7 @@ LINK_PHASE_OUT              <= link_phase_S;                --PL!
 -------------------------------------------------             
 THE_RX_CONTROL : rx_control
   port map(
-    CLK_200                        => rx_full_clk_ch3, --clk_200_i, PL! 
+    CLK_200                        => rx_full_clk,     --clk_200_i, PL! 
     CLK_100                        => SYSCLK,
     RESET_IN                       => rst,             --CLEAR, PL!
 

diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd
index 21b88a7a885792b2960d72ba25bef401ceb92f93..7d8c29e0482c4f853d60a41d6d5375ed3f068135 100644 (file)
--- a/code/trb3_periph_sodahub.vhd
+++ b/code/trb3_periph_sodahub.vhd
@@ -263,7 +263,7 @@ begin
       CLEAR_IN      => '0',              -- reset input (high active, async)
       CLEAR_N_IN    => '1',              -- reset input (low active, async)
       CLK_IN        => clk_200_osc,                    -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_100_osc,        -- PLL/DLL remastered clock
+      SYSCLK_IN     => rxup_half_clk,          --clk_100_osc,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => GSR_N,          --pll_lock,         -- master PLL lock signal (async)   !PL 14082014
       RESET_IN      => '0', --general_reset_i, -- '0',              -- general reset signal (SYSCLK) --peter schakel
       TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
@@ -397,7 +397,7 @@ begin
 
 THE_SPI_RELOAD :  spi_flash_and_fpga_reload    --.flash_reboot_arch
   port map(
-    CLK_IN               => clk_100_osc,       --clk_sys_i,
+    CLK_IN               => clk_100_osc,
     RESET_IN             => reset_i,
     
     BUS_ADDR_IN          => spimem_addr,
@@ -431,8 +431,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
                IS_SYNC_SLAVE           => c_YES
                )
        port map(
-               OSCCLK                                  => clk_200_osc, --clk_200_i,
-               SYSCLK                                  => clk_100_osc, --clk_sys_i,
+               OSCCLK                                  => clk_200_osc,
+               SYSCLK                                  => clk_100_osc,         -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
                RESET                                           => reset_i,
                CLEAR                                           => clear_i,
                --Internal Connection for TrbNet data -> not used a.t.m.
@@ -490,9 +490,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
 
        A_SODA_HUB : soda_hub
                port map(
-                       SYSCLK                                  => rxup_half_clk,       --clk_100_osc,  --clk_sys_i,
-                       SODACLK                                 =>      rxup_full_clk,  --clk_soda_i,
---                     SODA_OUT_CLK                    =>      txdn_full_clk,  -- This is 4 clocks !!
+                       SYSCLK                                  => rxup_half_clk,
+                       SODACLK                                 =>      rxup_full_clk,
                        RESET                                           => reset_i,
                        CLEAR                                           => clear_i,
                        CLK_EN                                  => '1',
@@ -534,8 +533,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
                                )
                        port map(
                                OSC_CLK                                                                                 => clk_200_osc,
-                               TX_DATACLK                                                                              => rxup_full_clk,       --clk_soda_i,   --clk_raw_internal, --clk_200_i,
-                               SYSCLK                                                                                  => clk_100_osc, --clk_sys_i,
+                               TX_DATACLK                                                                              => rxup_full_clk,
+                               SYSCLK                                                                                  => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
                                RESET                                                                                           => downlink_reset,
                                CLEAR                                                                                           => downlink_clear,
                                ---------------------------------------------------------------------------------------------------------------------------------------------------------
@@ -694,6 +693,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
 ---------------------------------------------------------------------------
 -- TRB-Hub
 ---------------------------------------------------------------------------
+       med_stat_op(3*16+15 downto 3*16) <= x"0007";            --       !PL telling the hub that this board is inactive        08192014
+       med_stat_op(5*16+15 downto 5*16) <= x"0007";            --       !PL telling the hub that this board is inactive        08192014\r
 
        TRB_HUB : trb_net16_hub_base
        generic map (

diff --git a/soda_hub.ldf b/soda_hub.ldf
new file mode 100644 (file)
index 0000000..e628cc1
--- /dev/null
+++ b/soda_hub.ldf
@@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.0" title="soda_hub" device="LFE3-150EA-8FN672C" default_implementation="soda_hub">
+    <Options>
+        <Option name="HDL type" value="VHDL"/>
+    </Options>
+    <Implementation title="soda_hub" dir="soda_hub" description="soda_hub" synthesis="synplify" default_strategy="Strategy1">
+        <Options top="trb3_periph_sodahub"/>
+        <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_hub.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/med_ecp3_sfp_4_sync_down.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/dff_re.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
+            <Options/>
+        </Source>
+        <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="code/trb3_periph_sodahub.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="trb3_periph_sodahub"/>
+        </Source>
+        <Source name="code/trb3_periph_hub.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="code/soda_hub_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
+            <Options/>
+        </Source>
+        <Source name="soda_hub.lpf" type="Logic Preference" type_short="LPF">
+            <Options/>
+        </Source>
+        <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal">
+            <Options/>
+        </Source>
+        <Source name="trb3_soda_hub.xcf" type="Programming Project File" type_short="Programming">
+            <Options/>
+        </Source>
+    </Implementation>
+    <Strategy name="Strategy1" file="soda_hub1.sty"/>
+</BaliProject>