Adding new port to endpoint for external slow control bus master for debug and loadin...

diff --git a/trb_net16_endpoint_hades_full_handler_record.vhd b/trb_net16_endpoint_hades_full_handler_record.vhd
index a1866867b2fc277ca45b4721100481c9868cf657..98f9d21afff2d8638cfcb60e58373a80751419b8 100644 (file)
--- a/trb_net16_endpoint_hades_full_handler_record.vhd
+++ b/trb_net16_endpoint_hades_full_handler_record.vhd
@@ -19,7 +19,6 @@ entity trb_net16_endpoint_hades_full_handler_record is
     ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
     BROADCAST_BITMASK            : std_logic_vector(7 downto 0)  := x"FF";
     REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
     REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;
     TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
     --Configure data handler
@@ -58,9 +57,12 @@ entity trb_net16_endpoint_hades_full_handler_record is
     --internal data port
     BUS_RX                       : out CTRLBUS_RX;
     BUS_TX                       : in  CTRLBUS_TX;
-
+    --Data port - external master (e.g. Flash or Debug)
+    BUS_MASTER_IN                : out CTRLBUS_TX;
+    BUS_MASTER_OUT               : in  CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+    BUS_MASTER_ACTIVE            : in  std_logic := '0';
     --Onewire
-    ONEWIRE_INOUT                : inout std_logic;  --temperature sensor
+    ONEWIRE_INOUT                : inout std_logic;
     --Config endpoint id, if not statically assigned
     REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector (15 downto 0) := (others => '0');
     TIMERS_OUT                   : out TIMERS;
@@ -82,8 +84,6 @@ end entity;
 
 
 
-
-
 architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endpoint_hades_full_handler_record is
 
   signal lvl1_data_valid_i       : std_logic;
@@ -120,7 +120,7 @@ architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endp
 --   signal stat_strobe_i           : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
 --   signal ctrl_strobe_i           : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
 
-  signal regio_rx, dbuf_rx, info_rx, stat_handler_rx, stat_buffer_rx : CTRLBUS_RX;
+  signal regio_rx, dbuf_rx, info_rx, stat_handler_rx, stat_buffer_rx, handlerbus_rx : CTRLBUS_RX;
   signal regio_tx, dbuf_tx, info_tx, stat_handler_tx, stat_buffer_tx : CTRLBUS_TX;
 
   signal time_global_i           : std_logic_vector (31 downto 0);
@@ -134,11 +134,12 @@ architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endp
   signal stat_handler_i          : std_logic_vector (127 downto 0);
   signal stat_data_buffer_level  : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0);
   signal stat_header_buffer_level: std_logic_vector (31 downto 0);
-
+  signal iobuf_data_count        : std_logic_vector (32*4-1 downto 0);
+  
   signal info_rd_nack    : std_logic;
   signal info_wr_nack    : std_logic;
   
-  signal info_registers          : std_logic_vector_array_32(0 to 3);  
+  signal info_registers          : std_logic_vector_array_32(0 to 4);  
   signal stat_handler_registers  : std_logic_vector_array_32(0 to 2);  
   
   signal debug_data_handler_i    : std_logic_vector(31 downto 0);
@@ -159,6 +160,7 @@ architecture trb_net16_endpoint_hades_full_handler_record_arch of trb_net16_endp
   signal fee_trg_statusbits_in : std_logic_vector(32*DATA_INTERFACE_NUMBER-1 downto 0);
   
   signal max_event_size            : std_logic_vector(15 downto 0);
+  signal buffer_disable            : std_logic_vector(15 downto 0);  
   signal new_max_size              : std_logic_vector(15 downto 0);
 
 begin
@@ -248,16 +250,16 @@ begin
       STAT_REG_STROBE            => open,
       CTRL_REG_STROBE            => open,
       
-      REGIO_ADDR_OUT         =>  regio_rx.addr, --regio_addr_out,
-      REGIO_READ_ENABLE_OUT  =>  regio_rx.read, --regio_read_enable_out,
-      REGIO_WRITE_ENABLE_OUT =>  regio_rx.write, --regio_write_enable_out,
-      REGIO_DATA_OUT         =>  regio_rx.data, --regio_data_out,
-      REGIO_DATA_IN          =>  regio_tx.data, --regio_data_in,
-      REGIO_DATAREADY_IN     =>  regio_tx.ack, --regio_dataready_in,
-      REGIO_NO_MORE_DATA_IN  =>  regio_tx.nack, --regio_no_more_data_in,
-      REGIO_WRITE_ACK_IN     =>  regio_tx.ack, --regio_write_ack_in,
-      REGIO_UNKNOWN_ADDR_IN  =>  regio_tx.unknown, --regio_unknown_addr_in,
-      REGIO_TIMEOUT_OUT      =>  regio_rx.timeout, --regio_timeout_out,
+      REGIO_ADDR_OUT         =>  regio_rx.addr, 
+      REGIO_READ_ENABLE_OUT  =>  regio_rx.read, 
+      REGIO_WRITE_ENABLE_OUT =>  regio_rx.write,
+      REGIO_DATA_OUT         =>  regio_rx.data, 
+      REGIO_DATA_IN          =>  regio_tx.data, 
+      REGIO_DATAREADY_IN     =>  regio_tx.ack,
+      REGIO_NO_MORE_DATA_IN  =>  regio_tx.nack, 
+      REGIO_WRITE_ACK_IN     =>  regio_tx.ack,
+      REGIO_UNKNOWN_ADDR_IN  =>  regio_tx.unknown,
+      REGIO_TIMEOUT_OUT      =>  regio_rx.timeout,
 
       REGIO_ONEWIRE_INOUT        => ONEWIRE_INOUT,
       REGIO_ONEWIRE_MONITOR_IN   => '0',
@@ -278,6 +280,7 @@ begin
       MED_STAT_OP                => open,
       CTRL_MPLEX                 => (others => '0'),
       IOBUF_CTRL_GEN             => (others => '0'),
+      IOBUF_DATA_COUNT           => iobuf_data_count,
       STAT_ONEWIRE               => open,
       STAT_ADDR_DEBUG            => open,
       STAT_TRIGGER_OUT           => STAT_TRIGGER_OUT,      
@@ -295,6 +298,9 @@ TIMERS_OUT.uid          <= unique_id_i;
 -- RegIO Bus Handler
 ---------------------------------------------------------------------------
 
+  handlerbus_rx <= regio_rx when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT;
+  BUS_MASTER_IN <= regio_tx;
+
   THE_INTERNAL_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
     generic map(
       PORT_NUMBER                => 5,
@@ -305,7 +311,7 @@ TIMERS_OUT.uid          <= unique_id_i;
       CLK         => CLK,
       RESET       => RESET,
 
-      REGIO_RX    => regio_rx,
+      REGIO_RX    => handlerbus_rx,
       REGIO_TX    => regio_tx,
 
       BUS_RX(0)   => BUS_RX,
@@ -327,7 +333,7 @@ TIMERS_OUT.uid          <= unique_id_i;
 
 THE_HANDLER_INFO_REGS : bus_register_handler
   generic map(
-    BUS_LENGTH => 4
+    BUS_LENGTH => 5
     )
   port map(
     RESET            => RESET,
@@ -352,6 +358,7 @@ info_registers(3) <=   std_logic_vector(to_unsigned(TRG_RELEASE_AFTER_DATA,1))
                      & "0000000"
                      & std_logic_vector(to_unsigned(HEADER_BUFFER_FULL_THRESH,16)) 
                      & std_logic_vector(to_unsigned(HEADER_BUFFER_DEPTH,8));
+info_registers(4) <= x"0000" & buffer_disable;                     
 
   proc_maxeventsize : process begin
     wait until rising_edge(CLK);
@@ -359,10 +366,15 @@ info_registers(3) <=   std_logic_vector(to_unsigned(TRG_RELEASE_AFTER_DATA,1))
     info_wr_nack <= info_rx.write;
     if RESET = '1' then
       max_event_size <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16));
+      buffer_disable <= (others => '0');
     elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "001" then
       max_event_size  <= info_rx.data(15 downto 0);
       info_tx.wack <= '1';
-      info_tx.nack <= '0';
+      info_wr_nack <= '0';
+    elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "100" then
+      buffer_disable  <= info_rx.data(15 downto 0);
+      info_tx.wack <= '1';
+      info_wr_nack <= '0';
     end if;
   end process;                     
 
@@ -440,6 +452,7 @@ stat_handler_registers(2) <= stat_handler_i(95 downto 64);
 
       TMG_TRG_ERROR_IN           => tmg_trg_error_i,
       MAX_EVENT_SIZE_IN          => max_event_size,
+      BUFFER_DISABLE_IN          => buffer_disable,      
       --Status Registers
       STAT_DATA_BUFFER_LEVEL     => stat_data_buffer_level,
       STAT_HEADER_BUFFER_LEVEL   => stat_header_buffer_level,

diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd
index e09ac059b57e3d336c0d1e438ef20f627a6098a8..71d0c0abfe156b9c9db474a954a12f5ebcd3a89a 100644 (file)
--- a/trb_net_onewire.vhd
+++ b/trb_net_onewire.vhd
@@ -37,6 +37,7 @@ architecture trb_net_onewire_arch of trb_net_onewire is
                    WRITE_START, WRITE_WAIT, READ_BIT, READ_READ_ROM, SEND_CONV_TEMP,
                    READ_CONV_TEMP, SEND_READ_TEMP, READ_READ_TEMP);
   signal state, next_state : state_t;
+  signal reset_i : std_logic;
   signal state_bits : std_logic_vector(3 downto 0);
   signal timecounter : integer range 0 to MAX_COUNTER;
   signal bitcounter  : integer range 0 to 127;
@@ -63,7 +64,7 @@ begin
 
   ONEWIRE <= '0' when output = '0' else '1' when strong_pullup = '1' else 'Z';
   input <= ONEWIRE;
-
+  reset_i <= RESET when rising_edge(CLK);
 
 
   PROC_REG_MONITOR : process(CLK)
@@ -290,7 +291,7 @@ begin
   process(CLK)
     begin
       if rising_edge(CLK) then
-        if RESET = '1' then
+        if reset_i = '1' then
           send_bit <= '0';
           output_tmp <= '0';
           recv_bit <= '0';
@@ -313,7 +314,7 @@ begin
     process(CLK)
       begin
         if rising_edge(CLK) then
-          if RESET = '1' then
+          if reset_i = '1' then
             send_rom <= '1';
             conv_temp <= '0';
             reading_temp <= '0';
@@ -339,7 +340,7 @@ begin
   process(CLK)
     begin
       if rising_edge(CLK) then
-        if RESET = '1' then
+        if reset_i = '1' then
           buf_TEMP_OUT <= (others => '0');
           ram_addr <= (others => '0');
           buf_STAT <= '0';