FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
- USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
- APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO;
+ APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO
);
port(
CLK : in std_logic;
RESET : in std_logic;
CLK_EN : in std_logic;
- INT_INIT_DATAREADY_IN: in std_logic;
- INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_INIT_READ_OUT: out std_logic; --always reading
+ INT_INIT_DATAREADY_IN : in std_logic;
+ INT_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_INIT_READ_OUT : out std_logic;
- INT_REPLY_DATAREADY_OUT: out std_logic;
- INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_IN: in std_logic;
+ INT_REPLY_DATAREADY_OUT : out std_logic;
+ INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_IN : in std_logic;
- INT_REPLY_DATAREADY_IN: in std_logic;
- INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- INT_REPLY_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INT_REPLY_READ_OUT: out std_logic;
+ INT_REPLY_DATAREADY_IN : in std_logic;
+ INT_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ INT_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ INT_REPLY_READ_OUT : out std_logic;
--apl init channel
- INIT_APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- INIT_APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- INIT_APL_DATAREADY_IN: in std_logic;
+ APL_INIT_DATA_IN : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_INIT_PACKET_NUM_IN : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_INIT_DATAREADY_IN : out std_logic;
--apl reply sending
- APL_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "application to network"
- APL_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_DATAREADY_IN: in std_logic; -- Data word is valid and should be transmitted
- APL_READ_OUT: out std_logic; -- Stop transfer, the fifo is full
- APL_SHORT_TRANSFER_IN: in std_logic; --
- APL_DTYPE_IN: in std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEND_IN: in std_logic; -- Release sending of the data
+ APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_DATAREADY_IN : in std_logic;
+ APL_READ_OUT : out std_logic;
+ APL_SHORT_TRANSFER_IN : in std_logic;
+ APL_DTYPE_IN : in std_logic_vector (3 downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
+ APL_SEND_IN : in std_logic;
-- reply receiving
- APL_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word "network to application"
- APL_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- APL_TYP_OUT: out std_logic_vector (2 downto 0); -- Which kind of data word: DAT, HDR or TRM
- APL_DATAREADY_OUT: out std_logic; -- Data word is valid and might be read out
- APL_READ_IN: in std_logic; -- Read data word
+ APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ APL_TYP_OUT : out std_logic_vector (2 downto 0);
+ APL_DATAREADY_OUT : out std_logic;
+ APL_READ_IN : in std_logic;
-- APL Control port
- APL_RUN_OUT: out std_logic; -- Data transfer is running
- APL_MY_ADDRESS_IN: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_LOOPBACK: in std_logic;
-
+ APL_RUN_OUT : out std_logic;
+ APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
+ APL_LOOPBACK : in std_logic;
+
+ STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
+ STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
);
end entity;
signal next_INT_REPLY_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal next_INT_REPLY_DATAREADY_OUT: std_logic;
signal sbuf_free, sbuf_next_READ: std_logic;
- signal next_INT_REPLY_READ_OUT, reg_INT_REPLY_READ_OUT: std_logic;
+ signal reg_INT_REPLY_READ_OUT: std_logic;
signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
signal combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0);
signal combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0);
signal registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0);
- signal current_combined_header, current_registered_trailer, current_combined_trailer, current_data : std_logic_vector(15 downto 0);
+ signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0);
signal update_registered_trailer: std_logic;
signal master_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal send_trm_wrong_addr, next_send_trm_wrong_addr : std_logic;
type PAS_API_TO_APL_STATE_T is (sa_IDLE, sa_INACTIVE);
signal state_to_apl, next_state_to_apl : PAS_API_TO_APL_STATE_T;
signal next_fifo_was_not_empty, fifo_was_not_empty : std_logic;
begin
+
+ APL_INIT_DATAREADY_IN <= INT_INIT_DATAREADY_IN;
+ APL_INIT_DATA_IN <= INT_INIT_DATA_IN;
+ APL_INIT_PACKET_NUM_IN <= INT_INIT_PACKET_NUM_IN;
+ INT_INIT_READ_OUT <= '1';
+
---------------------------------------
-- fifo to internal
---------------------------------------
FULL_OUT => fifo_to_int_full,
EMPTY_OUT => fifo_to_int_empty
);
- end generate;
STAT_FIFO_TO_INT(2 downto 0) <= fifo_to_int_data_in(2 downto 0);
STAT_FIFO_TO_INT(3) <= fifo_to_int_write;
---------------------------------------
- process(current_combined_header, current_registered_trailer, current_combined_trailer, current_data, out_select)
+ process(current_combined_header, current_registered_trailer, current_data, out_select)
begin
case out_select is
when HDR => next_INT_REPLY_DATA_OUT <= current_combined_header;
process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1,
- combined_trailer_F1, combined_header_F2, registered_trailer_F2, combined_trailer_F2,
- combined_header_F3, registered_trailer_F3, combined_trailer_F3)
+ combined_header_F2, registered_trailer_F2,
+ combined_header_F3, registered_trailer_F3)
begin
case master_counter is
when "01" =>
to_apl : process(fifo_to_apl_full, reg_INT_REPLY_READ_OUT, INT_REPLY_DATAREADY_IN, fifo_to_apl_empty,
fifo_to_apl_packet_num_out, state_to_apl, reg_APL_TYP_OUT, reg_APL_PACKET_NUM_OUT,
sbuf_to_apl_free, INT_REPLY_DATA_IN, INT_REPLY_PACKET_NUM_IN,
- reg_APL_DATAREADY_OUT, REPLY_running, fifo_to_apl_read_before, throw_away,state_to_int )
+ reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int )
begin
reg_INT_REPLY_READ_OUT <= not fifo_to_apl_full;
fifo_to_apl_write <= reg_INT_REPLY_READ_OUT and INT_REPLY_DATAREADY_IN;
fifo_to_apl_read <= '0';
next_APL_DATAREADY_OUT <= '0';
next_state_to_apl <= state_to_apl;
- next_send_trm_wrong_addr <= '0';
throw_away <= '0';
- REPLY_start <= '0';
- REPLY_end <= '0';
+ slave_start <= '0';
+ slave_end <= '0';
case state_to_apl is
when sa_IDLE =>
+ slave_start <= fifo_to_apl_write;
if APL_WRITE_4_PACKETS = 0 then
next_APL_DATAREADY_OUT <= fifo_to_apl_read_before and (or_all(fifo_to_apl_packet_num_out)) and sbuf_to_apl_free;
throw_away <= not or_all(fifo_to_apl_packet_num_out);
fifo_to_apl_read <= not fifo_to_apl_empty and not (fifo_to_apl_read_before and not sbuf_to_apl_free and not throw_away);
if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT = "11" and sbuf_to_apl_free = '1' then
next_state_to_apl <= sa_INACTIVE;
- REPLY_end <= '1';
+ slave_end <= '1';
end if;
when sa_INACTIVE =>
if state_to_int = INACTIVE then
---------------------------------------
--state machine for direction to INT
---------------------------------------
- to_int : process(state_to_int, send_trm_wrong_addr, APL_SHORT_TRANSFER_IN, APL_SEND_IN,
- REPLY_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before,
- state_to_apl, REPLY_start)
+ to_int : process(state_to_int, APL_SHORT_TRANSFER_IN, APL_SEND_IN, slave_start,
+ master_counter, sbuf_free, fifo_to_int_empty, sequence_counter, fifo_to_int_read_before,
+ state_to_apl, master_start, fifo_was_not_empty)
begin
next_state_to_int <= state_to_int;
update_registered_trailer <= '0';
next_INT_REPLY_DATAREADY_OUT <= '0';
next_sequence_counter <= sequence_counter;
fifo_to_int_read <= '0';
- REPLY_start <= '0';
- REPLY_end <= '0';
+ master_start <= '0';
+ master_end <= '0';
next_fifo_was_not_empty <= fifo_was_not_empty or not fifo_to_int_empty;
case state_to_int is
when INACTIVE =>
- if API_TYPE = 0 then
- if REPLY_start = '1' then
- next_state_to_int <= IDLE;
- elsif send_trm_wrong_addr = '1' then
- next_state_to_int <= SEND_SHORT;
- end if;
- else --API_TYPE = 1
- if state_to_apl = sa_INACTIVE then
- next_state_to_int <= IDLE;
- end if;
+ if slave_start = '1' then
+ next_state_to_int <= IDLE;
end if;
when IDLE =>
next_fifo_was_not_empty <= '0';
if APL_SEND_IN = '1' then
- REPLY_start <= '1';
+ master_start <= '1';
if APL_SHORT_TRANSFER_IN = '1' then
next_state_to_int <= SEND_SHORT;
else
when SEND_HEADER =>
out_select <= HDR;
next_INT_REPLY_DATAREADY_OUT <= sbuf_free;
- if REPLY_counter = "11" and sbuf_free = '1' then
+ if master_counter = "11" and sbuf_free = '1' then
next_state_to_int <= RUNNING;
end if;
when RUNNING =>
- fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(REPLY_counter);
- next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(REPLY_counter));
+ fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter);
+ next_INT_REPLY_DATAREADY_OUT <= sbuf_free and (fifo_to_int_read_before or not or_all(master_counter));
if APL_SEND_IN = '0' and fifo_was_not_empty = '1' then -- terminate the transfer
update_registered_trailer <= '1';
- if fifo_to_int_empty = '1' and REPLY_counter = "11" and sbuf_free = '1' then
+ if fifo_to_int_empty = '1' and master_counter = "11" and sbuf_free = '1' then
next_state_to_int <= SEND_TRAILER; -- immediate stop
else
next_state_to_int <= SHUTDOWN; -- send rest of data / padding
end if;
end if;
when SHUTDOWN =>
- fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(REPLY_counter);
+ fifo_to_int_read <= not fifo_to_int_empty and sbuf_free and or_all(master_counter);
next_INT_REPLY_DATAREADY_OUT <= sbuf_free and
- ((fifo_to_int_read_before or not or_all(REPLY_counter)) or --write data from fifo
- (fifo_to_int_empty and or_all(REPLY_counter))); --fill with padding words
- if REPLY_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then
+ ((fifo_to_int_read_before or not or_all(master_counter)) or --write data from fifo
+ (fifo_to_int_empty and or_all(master_counter))); --fill with padding words
+ if master_counter = "11" and fifo_to_int_empty = '1' and sbuf_free = '1' then
next_state_to_int <= SEND_TRAILER;
end if;
when SEND_TRAILER =>
out_select <= TRM;
next_INT_REPLY_DATAREADY_OUT <= sbuf_free;
- if REPLY_counter = "11" and sbuf_free = '1' then
+ if master_counter = "11" and sbuf_free = '1' then
next_state_to_int <= INACTIVE;
next_sequence_counter <= sequence_counter +1;
- REPLY_end <= '1';
+ master_end <= '1';
end if;
end case;
end process;
begin
if rising_edge(CLK) then
if RESET = '1' then
- if API_TYPE = 0 then
- state_to_apl <= sa_IDLE;
- state_to_int <= INACTIVE;
- else
- state_to_apl <= sa_INACTIVE;
- state_to_int <= IDLE;
- end if;
+ state_to_apl <= sa_IDLE;
+ state_to_int <= INACTIVE;
--reg_INT_SLAVE_READ_OUT <= '0';
- send_trm_wrong_addr <= '0';
sequence_counter <= (others => '0');
fifo_was_not_empty <= '0';
else
state_to_apl <= next_state_to_apl;
state_to_int <= next_state_to_int;
--reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
- send_trm_wrong_addr <= next_send_trm_wrong_addr;
sequence_counter <= next_sequence_counter;
fifo_was_not_empty <= next_fifo_was_not_empty;
end if;
--
---------------------------------------
- --get target address from active APL
- gentarget1: if API_TYPE = 1 generate
- combined_header_F2 <= APL_TARGET_ADDRESS_IN;
- end generate;
--save target address for passive api
- gentarget0: if API_TYPE = 0 generate
- reg_hdr_f1: process(CLK)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- combined_header_F2 <= (others => '1');
- elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then
- combined_header_F2 <= fifo_to_apl_data_out;
- end if;
+ reg_hdr_f1: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ combined_header_F2 <= (others => '1');
+ elsif current_fifo_to_apl_packet_type = TYPE_HDR and fifo_to_apl_packet_num_out = "01" then
+ combined_header_F2 <= fifo_to_apl_data_out;
end if;
- end process;
- end generate;
+ end if;
+ end process;
-- combine the next header
combined_header_F1 <= APL_MY_ADDRESS_IN;
combined_header_F3(15 downto 14) <= (others => '0'); -- LAY
-- connect receiver
fifo_to_apl_data_in <= INT_REPLY_DATA_IN;
fifo_to_apl_packet_num_in <= INT_REPLY_PACKET_NUM_IN;
- INT_SLAVE_READ_OUT <= reg_INT_REPLY_READ_OUT;
+ INT_REPLY_READ_OUT <= reg_INT_REPLY_READ_OUT;
RUN_OUT_gen : process(CLK)
begin
if RESET = '1' then
APL_RUN_OUT <= '0';
else
- if API_TYPE = 0 then
- if slave_start = '1' then
- APL_RUN_OUT <= '1';
- elsif slave_running = '0' and state_to_int = INACTIVE then
- APL_RUN_OUT <= '0';
- end if;
- else --API_TYPE = 1
- if master_start = '1' then
- APL_RUN_OUT <= '1';
- elsif master_running = '0' and state_to_apl = sa_INACTIVE then
- APL_RUN_OUT <= '0';
- end if;
+ if slave_start = '1' then
+ APL_RUN_OUT <= '1';
+ elsif slave_running = '0' and state_to_int = INACTIVE then
+ APL_RUN_OUT <= '0';
end if;
end if;
end if;
jspc29 / trbnet.git / commitdiff