added picture of trb3sc patch

diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex
index 28131a28cd3d518e72d4e5c85b934f38f7515da5..6ad1242bb22a5f981a0a1b3822492d0345f6a0bd 100644 (file)
--- a/trb3/Trb3scBasics.tex
+++ b/trb3/Trb3scBasics.tex
@@ -102,10 +102,18 @@ By default, the use of Serdes channels is as follows:
 The TrbNet uplink (either Sfp or backplane) is synchronous, i.e. no clock tolerance compensation is enabled. Hence, both boards connected with the link must share a common clock source. For low-accuracy applications, the clock can be recovered from the optical link. In this case, no additional clock distribution is needed. If running in a crate, clock recovery is available, but not necessary as the backplane distributes a clock signal to all boards connected.
 
 \subsubsection{Modifications}
+   \begin{figure}
+      \begin{center}
+         \includegraphics[width=0.7\textwidth]{figures/trb3scpatch.png}
+         \caption[Trb3sc Patch]{Trb3sc patch to display status of clock input switch}
+         \label{fig:trb3scpatch}
+      \end{center}
+   \end{figure}
+
 The following changes compared to the original schematics are to be made:
 \begin{description*}
   \item [R12, R14] 270 Ohm, LED is too dim
   \item [R13, R15] 680 Ohm, LED is too dim
   \item [R16, R17] 680 Ohm, LED is too bright
-  \item [Patchwire] Disconnect R14 from 2.5V (rotate by 90°), patchwire to Pin 2 of switch - green LED shows status of clock select
+  \item [Patchwire] Disconnect R14 from 2.5V (rotate by 90°), patchwire to Pin 2 of switch - green LED shows status of clock select. See picture.
 \end{description*}
\ No newline at end of file

diff --git a/trb3/figures/trb3scpatch.png b/trb3/figures/trb3scpatch.png
new file mode 100644 (file)
index 0000000..56a35f3
Binary files /dev/null and b/trb3/figures/trb3scpatch.png differ