fixed write enable bug for decoder bypass

diff --git a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
index 69f02ce34dc80fbe47ef5f78ff59610d87d21149..94eb9eb94fbe9d36198170e5141678afde6fa4ad 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
+++ b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
@@ -123,7 +123,7 @@ architecture rtl of MupixTRBReadout is
       counterB_out  : out std_logic_vector(D_W - 1 downto 0);  -- last counter value link B
       counterC_out  : out std_logic_vector(D_W - 1 downto 0)   -- last counter value link C
     );
-  end component DataDecoder
+  end component DataDecoder;
 
   component ReadoutController
     generic(
@@ -214,7 +214,7 @@ begin
 
   start_readout <= start_readout_slow_to_buffer or trb_trigger;
 
-  FiFoDataMux_1 : entity work.FiFoDataMux
+  FiFoDataMux_1 : FiFoDataMux
     generic map (
       g_datawidth  => g_datawidthfifo,
       g_inputs     => g_mupix_links,
@@ -253,9 +253,9 @@ begin
       LINKS => g_mupix_links
     )
     port map (
-      clk           => clk
+      clk           => clk,
       reset         => reset_reg,
-      bypass        => converter_bypass_i,
+      bypass        => decoder_bypass_i,
       datain        => mupix_filter_dataout_i,
       datain_valid  => mupix_filter_dataout_valid_i,
       counterA_in   => mupix_filter_counterA_i,
@@ -266,10 +266,10 @@ begin
       dataout_valid => decoder_dataout_valid_i,
       counterA_out  => decoder_counterA_i,
       counterB_out  => decoder_counterB_i,
-      counterC_out  => decoder_counterC_i,
+      counterC_out  => decoder_counterC_i
     );
 
-  cycl_buffer_1 : entity work.CircularMemory
+  cycl_buffer_1 : CircularMemory
     generic map(
       g_datawidth    => g_datawidthtrb,
       g_addresswidth => g_cyc_mem_address_width,
@@ -293,7 +293,7 @@ begin
       outword_freq => cycl_outword_freq
       );
 
-  readout_controller_1 : entity work.ReadoutController
+  readout_controller_1 : ReadoutController
     generic map(
       g_datawidth    => g_datawidthtrb,
       g_addresswidth => g_cyc_mem_address_width
@@ -495,4 +495,4 @@ begin
   dataout    <= readout_controller_data_out;
   data_valid <= readout_controller_data_valid;
 
-end architecture;
+end rtl;

diff --git a/mupix/Mupix8/sources/Datapath/PixelAddressDecode.vhd b/mupix/Mupix8/sources/Datapath/PixelAddressDecode.vhd
index d518afc7352fd7ad6b82ff74e4cd32a2a6469e4d..5e6acb90551e1d955356e1d6050db5b8f3ba8b18 100644 (file)
--- a/mupix/Mupix8/sources/Datapath/PixelAddressDecode.vhd
+++ b/mupix/Mupix8/sources/Datapath/PixelAddressDecode.vhd
@@ -1,6 +1,6 @@
 -----------------------------------------------------------
 -- Decoding of pixel address of Mupix 8 to physical address
--- T.Weber
+-- T.Weber, R. Hagdorn
 -- Ruhr University Bochum
 -----------------------------------------------------------
 library IEEE;
@@ -67,6 +67,7 @@ begin  -- architecture rtl
         if bypass = '1' then
           col_out <= col_in;
           row_out <= row_in;
+          valid_o <= ena;
         else
           col_out <= col_i;
           row_out <= row_i;

diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj
index c9f2dca9b1aac4217a538cfb9be07a490afa55ef..c076d0a025a127d6e1805b52a4596945bb2470d1 100644 (file)
--- a/mupix/Mupix8/trb3_periph.prj
+++ b/mupix/Mupix8/trb3_periph.prj
@@ -198,6 +198,9 @@ add_file -vhdl -lib "work" "sources/Datapath/DataWidthConversion.vhd"
 add_file -vhdl -lib "work" "sources/Datapath/MuPixUnpacker.vhd"
 add_file -vhdl -lib "work" "sources/Datapath/LinkSynchronizer.vhd"
 add_file -vhdl -lib "work" "sources/Datapath/DataFilter.vhd"
+add_file -vhdl -lib "work" "sources/Datapath/DataDecoder.vhd"
+add_file -vhdl -lib "work" "sources/Datapath/PixelAddressDecode.vhd"
+add_file -vhdl -lib "work" "sources/Datapath/Gray2Binary.vhd"
 
 add_file -vhdl -lib "work" "sources/Simulation/DatasourceSelector.vhd"
 add_file -vhdl -lib "work" "sources/Simulation/FrameGeneratorMux.vhd"