maxtot_timer <= maxtot_timer - 1;
else
edge_rising_valid <= '0';
- count_edges3 <= count_edges3 + 1;
+ if edge_rising_valid = '1' then
+ count_edges3 <= count_edges3 + 1;
+ end if;
end if;
process begin
wait until rising_edge(CLK_TDC);
- if RESET_IN = '1' then
- count_edges1 <= (others => '0');
- elsif hit_buffer_write = '1' then
+ if hit_buffer_write = '1' then
count_edges1 <= count_edges1 + 1;
end if;
end process;
process begin
wait until rising_edge(CLK_TDC);
- if RESET_IN = '1' then
- count_edges2 <= (others => '0');
- elsif count_spike_en = '1' then
+ if count_spike_en = '1' then
count_edges2 <= count_edges2 + 1;
end if;
end process;
STATUS_OUT(31 downto 0) <= x"00" & std_logic_vector(count_edges1) when rising_edge(CLK_SYS);
STATUS_OUT(63 downto 32) <= x"00" & std_logic_vector(count_edges2) when rising_edge(CLK_SYS);
STATUS_OUT(71 downto 64) <= "00" & hit_buffer_level when rising_edge(CLK_SYS);
-STATUS_OUT(95 downto 72) <= std_logic_vector(count_edges3) when rising_edge(CLK_SYS);
-STATUS_OUT(127 downto 96) <= std_logic_vector(count_edges4) when rising_edge(CLK_SYS);
+STATUS_OUT(95 downto 72) <= x"00" & std_logic_vector(count_edges3(15 downto 0)) when rising_edge(CLK_SYS);
+STATUS_OUT(127 downto 96) <= x"0000" & std_logic_vector(count_edges4(15 downto 0)) when rising_edge(CLK_SYS);
----------------------------------------------------------------------