*** empty log message ***

diff --git a/xilinx/virtex4/fifo/fifo_var_oreg.vhd b/xilinx/virtex4/fifo/fifo_var_oreg.vhd
index 92399ea32d8af1dc28e6486a3cf3ea134cfa0e67..205615bc66708f5271b4940620524bfb361b8ce4 100644 (file)
--- a/xilinx/virtex4/fifo/fifo_var_oreg.vhd
+++ b/xilinx/virtex4/fifo/fifo_var_oreg.vhd
@@ -105,17 +105,17 @@ begin
   gen_36_32k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 15  generate
     THE_FIFO :  fifo_36x32k_oreg
       port map(
-        Data                   =>  Data,
-        Clock                  =>  Clock,
-        WrEn                   =>  WrEn,
-        RdEn                   =>  RdEn,
-        Reset                  =>  Reset,
-        AmFullThresh           =>  AmFullThresh,
-        Q                      =>  Q,
-        WCNT                   =>  WCNT(14 downto 0),
-        Empty                  =>  Empty,
-        Full                   =>  Full,
-        AlmostFull             =>  AlmostFull
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(14 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
         );
   end generate;
 
@@ -123,23 +123,20 @@ begin
   gen_18_512 : if FIFO_WIDTH = 18 and FIFO_DEPTH = 9  generate
     THE_FIFO :  fifo_18x512_oreg
       port map(
-        Data                   =>  Data,
-        Clock                  =>  Clock,
-        WrEn                   =>  WrEn,
-        RdEn                   =>  RdEn,
-        Reset                  =>  Reset,
-        AmFullThresh           =>  AmFullThresh,
-        Q                      =>  Q,
-        WCNT                   =>  WCNT(8 downto 0),
-        Empty                  =>  Empty,
-        Full                   =>  Full,
-        AlmostFull             =>  AlmostFull
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(8 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
         );
   end generate;
 
 
 
-
-
-
 end architecture;
\ No newline at end of file