-- gk 07.10.10
signal pc_eos : std_logic;
+-- gk 09.12.10
+signal frame_delay : std_logic_vector(31 downto 0);
+
begin
stage_ctrl_regs <= STAGE_CTRL_REGS_IN;
GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid, -- gk 26.04.10
GBE_DELAY_OUT => pc_delay,
GBE_ALLOW_LARGE_OUT => allow_large, -- gk 21.07.10
+ GBE_FRAME_DELAY_OUT => frame_delay, -- gk 09.12.10
-- gk 28.07.10
MONITOR_BYTES_IN => bytes_sent_ctr,
MONITOR_SENT_IN => monitor_sent,
-- ports for user logic
RESET => RESET,
CLK => CLK,
- MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
PC_WR_EN_IN => pc_wr_en,
PC_DATA_IN => pc_data,
PC_READY_OUT => pc_ready,
PC_QUEUE_DEC_IN => pc_queue_dec,
PC_MAX_FRAME_SIZE_IN => pc_max_frame_size,
PC_DELAY_IN => pc_delay, -- gk 28.04.10
+ MULT_EVT_ENABLE_IN => use_multievents, -- gk 06.10.10
-- NEW PORTS
FC_WR_EN_OUT => fc_wr_en,
FC_DATA_OUT => fc_data,
FLAGS_OFFSET_IN => fc_flags_offset,
TTL_IN => fc_ttl,
PROTOCOL_IN => fc_protocol,
+ FRAME_DELAY_IN => frame_delay, -- gk 09.12.10
-- ports for packetTransmitter
RD_CLK => serdes_clk_125,
FT_DATA_OUT => ft_data,
FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);\r
TTL_IN : in std_logic_vector(7 downto 0);\r
PROTOCOL_IN : in std_logic_vector(7 downto 0);\r
+ FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10\r
-- ports for packetTransmitter\r
RD_CLK : in std_logic; -- 125MHz clock!!!\r
FT_DATA_OUT : out std_logic_vector(8 downto 0);\r
type constructStates is (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,\r
TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,\r
SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,\r
- UDP_CS, SAVE_DATA, CLEANUP);\r
+ UDP_CS, SAVE_DATA, CLEANUP, DELAY);\r
signal constructCurrentState, constructNextState : constructStates;\r
signal bsm_constr : std_logic_vector(7 downto 0);\r
attribute sys_encoding of constructCurrentState: signal is "safe,gray";\r
\r
signal fpf_reset : std_logic; -- gk 01.01.01\r
\r
+-- gk 09.12.10\r
+signal delay_ctr : std_logic_vector(31 downto 0);\r
+signal frame_delay_reg : std_logic_vector(31 downto 0);\r
+\r
begin\r
\r
-- Fakes\r
end process constructMachineProc;\r
\r
--find next state of construct machine\r
-constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX )\r
+constructMachine: process( constructCurrentState, START_OF_DATA_IN, END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, delay_ctr, FRAME_DELAY_IN )\r
begin\r
constructNextState <= constructCurrentState;\r
if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0\r
constructNextState <= CLEANUP;\r
end if;\r
when CLEANUP =>\r
- constructNextState <= IDLE;\r
+ constructNextState <= DELAY; -- gk 10.12.10 IDLE;\r
+\r
+ -- gk 09.12.10\r
+ when DELAY =>\r
+ if (delay_ctr = FRAME_DELAY_IN) then\r
+ constructNextState <= IDLE;\r
+ else\r
+ constructNextState <= DELAY;\r
+ end if;\r
+\r
when others =>\r
constructNextState <= IDLE;\r
end case;\r
end if;\r
end process constructMachine;\r
\r
+-- gk 09.12.10\r
+delayCtrProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (constructCurrentState = IDLE) or (constructCurrentState = CLEANUP) then\r
+ delay_ctr <= (others => '0');\r
+ elsif (constructCurrentState = DELAY) then\r
+ delay_ctr <= delay_ctr + x"1";\r
+ end if;\r
+\r
+ frame_delay_reg <= FRAME_DELAY_IN;\r
+ end if;\r
+end process delayCtrProc;\r
+\r
\r
bsmConstrProc : process(constructCurrentState)\r
begin\r
when UDP_CS => cur_max <= 1; bsm_constr <= x"12";\r
when SAVE_DATA => cur_max <= 0; bsm_constr <= x"13";\r
when CLEANUP => cur_max <= 0; bsm_constr <= x"14";\r
+ when DELAY => cur_max <= 0; bsm_constr <= x"15";\r
when others => cur_max <= 0; bsm_constr <= x"1f";\r
end case;\r
end process;\r
begin\r
if (RESET = '1') or (LINK_OK_IN = '0') then -- gk 01.10.10\r
fpf_wr_en <= '0';\r
- elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then\r
+ elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) and (constructCurrentState /= DELAY) then\r
fpf_wr_en <= '1';\r
elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then\r
fpf_wr_en <= '1';\r
when UDP_CS => fpf_data <= udp_checksum(15 - headers_int_counter * 8 downto 8 - headers_int_counter * 8);\r
when SAVE_DATA => fpf_data <= DATA_IN;\r
when CLEANUP => fpf_data <= x"ab";\r
+ when DELAY => fpf_data <= x"ac";\r
when others => fpf_data <= x"00";\r
end case;\r
end process fpfDataProc;\r
PC_QUEUE_DEC_IN : in std_logic_vector(31 downto 0); -- swap\r
PC_MAX_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); -- DO NOT SWAP\r
PC_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 28.04.10\r
+ MULT_EVT_ENABLE_IN : in std_logic; -- gk 08.11.10\r
+ PC_END_OF_SUB_IN : in std_logic; -- gk 08.10.11\r
-- FrameConstructor ports\r
FC_WR_EN_OUT : out std_logic;\r
FC_DATA_OUT : out std_logic_vector(7 downto 0);\r
end component;\r
\r
-- FIFO for SubEventHeader information\r
-component fifo_2048x8 is\r
+-- gk 06.12.10 component fifo_2048x8 is\r
+component fifo_16kx8 is\r
port (\r
Data : in std_logic_vector(7 downto 0); \r
WrClock : in std_logic; \r
signal load_eod : std_logic;\r
signal load_eod_q : std_logic;\r
\r
+-- gk 08.11.11\r
+signal df_eod : std_logic;\r
+\r
+-- gk 04.12.10\r
+signal first_sub_in_multi : std_logic;\r
+signal from_divide_state : std_logic;\r
+signal disable_prep : std_logic;\r
+\r
begin\r
\r
-- Fakes\r
DATA_FIFO : fifo_64kx9\r
port map(\r
Data(7 downto 0) => PC_DATA_IN,\r
- Data(8) => PC_END_OF_DATA_IN,\r
+ Data(8) => df_eod, --PC_END_OF_DATA_IN, -- gk 08.11.10\r
WrClock => CLK,\r
RdClock => CLK,\r
WrEn => df_wr_en,\r
Full => df_full\r
);\r
\r
+-- gk 08.11.10\r
+df_eod <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (PC_END_OF_DATA_IN = '1'))\r
+ or ((MULT_EVT_ENABLE_IN = '1') and (PC_END_OF_SUB_IN = '1'))\r
+ else '0';\r
+\r
LOAD_EOD_PROC : process(CLK)\r
begin\r
if rising_edge(CLK) then\r
case constructCurrentState is\r
when CIDLE =>\r
constr_state <= x"0";\r
- if( PC_WR_EN_IN = '1' ) then\r
+ --if( PC_WR_EN_IN = '1' ) then\r
+ -- gk 04.12.10\r
+ if (PC_START_OF_SUB_IN = '1') then\r
constructNextState <= SAVE_DATA;\r
else\r
constructNextState <= CIDLE;\r
end if;\r
end process queueSizeProc;\r
\r
-\r
--***********************\r
-- LOAD DATA COMBINED WITH HEADERS INTO FC, QUEUE TRANSMISSION\r
--***********************\r
when PREP_DATA =>\r
load_state <= x"5";\r
loadNextState <= LOAD_DATA;\r
+-- when LOAD_DATA =>\r
+-- load_state <= x"6";\r
+-- if (bytes_loaded = max_frame_size - 1) then\r
+-- loadNextState <= DIVIDE;\r
+-- -- gk 26.07.10\r
+-- -- close packet after one event loaded\r
+-- elsif (load_eod_q = '1') then\r
+-- loadNextState <= LOAD_TERM;\r
+-- -- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded\r
+-- -- if (size_left = x"00000021") then -- and there is no more data, only termination left\r
+-- -- -- gk 21.07.10\r
+-- -- if (PC_SKIP_TERM_IN = '0') then\r
+-- -- loadNextState <= LOAD_TERM; -- add termination and close packet\r
+-- -- else\r
+-- -- loadNextState <= CLEANUP;\r
+-- -- end if;\r
+-- -- else -- there is more data in fifo\r
+-- -- loadNextState <= LOAD_SUB; -- add another subevent\r
+-- -- end if;\r
+-- else\r
+-- loadNextState <= LOAD_DATA;\r
+-- end if;\r
+ -- gk 04.12.10\r
when LOAD_DATA =>\r
load_state <= x"6";\r
if (bytes_loaded = max_frame_size - 1) then\r
loadNextState <= DIVIDE;\r
- -- gk 26.07.10\r
- -- close packet after one event loaded\r
+ -- gk 07.10.10\r
elsif (load_eod_q = '1') then\r
- loadNextState <= LOAD_TERM;\r
--- elsif (sub_bytes_loaded = sub_size_loaded) then -- if all subevent bytes are loaded\r
--- if (size_left = x"00000021") then -- and there is no more data, only termination left\r
--- -- gk 21.07.10\r
--- if (PC_SKIP_TERM_IN = '0') then\r
--- loadNextState <= LOAD_TERM; -- add termination and close packet\r
--- else\r
--- loadNextState <= CLEANUP;\r
--- end if;\r
--- else -- there is more data in fifo\r
--- loadNextState <= LOAD_SUB; -- add another subevent\r
--- end if;\r
+ if (MULT_EVT_ENABLE_IN = '1') then\r
+ if (size_left < x"0000_0030") then\r
+ loadNextState <= LOAD_TERM;\r
+ else\r
+ loadNextState <= LOAD_SUB;\r
+ end if;\r
+ else\r
+ loadNextState <= LOAD_TERM;\r
+ end if;\r
else\r
loadNextState <= LOAD_DATA;\r
end if;\r
end case;\r
end process loadMachine;\r
\r
+-- gk 04.12.10\r
+firstSubInMultiProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') or (loadCurrentState = LOAD_TERM) then\r
+ first_sub_in_multi <= '1';\r
+ elsif (loadCurrentState = LOAD_DATA) then\r
+ first_sub_in_multi <= '0';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+-- gk 04.12.10\r
+fromDivideStateProc : process(CLK)\r
+begin\r
+ if rising_edge(CLK) then\r
+ if (RESET = '1') then\r
+ from_divide_state <= '0';\r
+ elsif (loadCurrentState = DIVIDE) then\r
+ from_divide_state <= '1';\r
+ elsif (loadCurrentState = PREP_DATA) then\r
+ from_divide_state <= '0';\r
+ end if;\r
+ end if;\r
+end process fromDivideStateProc;\r
+\r
dividePositionProc : process(CLK)\r
begin\r
if rising_edge(CLK) then\r
elsif (bytes_loaded = max_frame_size - 1) then\r
if (loadCurrentState = LIDLE) then\r
divide_position <= "00";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
elsif (loadCurrentState = LOAD_DATA) then\r
+ -- gk 05.12.10\r
-- gk 26.07.10\r
- if (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
+ if (MULT_EVT_ENABLE_IN = '0') and (load_eod_q = '1') then -- if termination is about to be loaded divide on term\r
divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (load_eod_q = '1') then\r
+ if (size_left > x"0000_0028") then\r
+ divide_position <= "01";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ else\r
+ divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
+ end if;\r
else\r
divide_position <= "00"; -- still data loaded divide on data\r
--- if (sub_bytes_loaded = sub_size_loaded) and (size_left = x"00000021") then\r
--- divide_position <= "11";\r
--- elsif (sub_bytes_loaded = sub_size_loaded) and (size_left /= x"00000021") then\r
--- divide_position <= "01";\r
--- else\r
--- divide_position <= "00";\r
+ disable_prep <= '1'; -- gk 05.12.10\r
end if;\r
elsif (loadCurrentState = LOAD_SUB) then\r
if (all_int_ctr = 15) then\r
divide_position <= "00";\r
+ disable_prep <= '1'; -- gk 05.12.10\r
else\r
divide_position <= "01";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
end if;\r
elsif (loadCurrentState = LOAD_TERM) then\r
divide_position <= "11";\r
+ disable_prep <= '0'; -- gk 05.12.10\r
end if;\r
+ elsif (loadCurrentState = PREP_DATA) then -- gk 06.12.10 reset disable_prep\r
+ disable_prep <= '0';\r
end if;\r
end if;\r
end process dividePositionProc;\r
end process shfRdEnProc;\r
\r
\r
-fcWrEnProc : process(loadCurrentState, RESET)\r
+fcWrEnProc : process(loadCurrentState, RESET, first_sub_in_multi, from_divide_state, MULT_EVT_ENABLE_IN, divide_position, disable_prep)\r
begin\r
if (RESET = '1') then -- gk 31.05.10\r
fc_wr_en <= '0';\r
fc_wr_en <= '1';\r
elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then\r
fc_wr_en <= '1';\r
+ -- gk 04.12.10\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
+ fc_wr_en <= '1';\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
+ fc_wr_en <= '1';\r
else\r
fc_wr_en <= '0';\r
end if;\r
bytes_loaded <= x"0000";\r
elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_TERM) then\r
bytes_loaded <= bytes_loaded + x"1";\r
+ -- gk 05.12.10\r
+-- elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') then\r
+-- bytes_loaded <= bytes_loaded + x"1";\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (first_sub_in_multi = '0') and (from_divide_state = '0') and (disable_prep = '0') then\r
+ bytes_loaded <= bytes_loaded + x"1";\r
+ elsif (MULT_EVT_ENABLE_IN = '1') and (loadCurrentState = PREP_DATA) and (from_divide_state = '1') and ((divide_position = "00") or (divide_position = "01")) and (disable_prep = '0') then\r
+ bytes_loaded <= bytes_loaded + x"1";\r
end if;\r
end if;\r
end process bytesLoadedProc;\r
-- SUBEVENT HEADERS WRITE AND READ\r
--***********************\r
\r
-SUBEVENT_HEADERS_FIFO : fifo_2048x8\r
+SUBEVENT_HEADERS_FIFO : fifo_16kx8 -- gk 06.12.10 fifo_2048x8\r
port map(\r
Data => shf_data,\r
WrClock => CLK,\r
GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
GBE_ALLOW_LARGE_OUT : out std_logic;
+ GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10
-- gk 28.07.10
MONITOR_BYTES_IN : in std_logic_vector(31 downto 0);
MONITOR_SENT_IN : in std_logic_vector(31 downto 0);
signal delay : std_logic_vector(31 downto 0); -- gk 28.04.10
signal allow_large : std_logic; -- gk 21.07.10
signal reset_fifo : std_logic; -- gk 28.09.10
+signal frame_delay : std_logic_vector(31 downto 0); -- gk 09.12.10
begin
GBE_DELAY_OUT <= delay; -- gk 28.04.10
GBE_ALLOW_LARGE_OUT <= allow_large; -- gk 21.07.10
--DBG_RESET_FIFO_OUT <= reset_fifo; -- gk 28.09.10
+ GBE_FRAME_DELAY_OUT <= frame_delay; -- gk 09.12.10
end if;
end process OUT_PROC;
subevent_id <= x"0000_00cf";
subevent_dec <= x"0002_0001";
queue_dec <= x"0003_0062";
- max_packet <= x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
+ max_packet <= x"0000_ea60"; --x"0000_fde8"; --x"0000_fde8"; -- 65k --x"0000_fde8"; -- tester
min_packet <= x"0000_0007"; -- gk 20.07.10
max_frame <= x"0578";
use_gbe <= '0'; --'1'; -- gk 27.08.10 -- blocks the transmission until gbe gets configured
DBG_FIFO_RD_EN_OUT <= '0';
allow_large <= '0'; -- gk 21.07.10
reset_fifo <= '0'; -- gk 28.09.10
+ frame_delay <= x"0000_0000"; -- gk 09.12.10
elsif (BUS_WRITE_EN_IN = '1') then
case BUS_ADDR_IN is
allow_large <= '1';
end if;
+ -- gk 09.12.10
+ when x"0d" =>
+ frame_delay <= BUS_DATA_IN;
+
-- gk 28.09.10
when x"fe" =>
if (BUS_DATA_IN = x"ffff_ffff") then
DBG_FIFO_RD_EN_OUT <= '0';
allow_large <= allow_large;
reset_fifo <= reset_fifo; -- gk 28.09.10
+ frame_delay <= frame_delay;
end case;
else
reset_values <= '0';
data_out <= x"0000_0001";
end if;
+ -- gk 09.12.10
+ when x"0d" =>
+ data_out <= frame_delay;
+
-- gk 01.06.10
when x"e0" =>
data_out <= DBG_IPU2GBE1_IN;
PC_DATA_OUT : out std_logic_vector (7 downto 0);
PC_READY_IN : in std_logic;
PC_SOS_OUT : out std_logic;
+ PC_EOS_OUT : out std_logic; -- gk 08.11.10
PC_EOD_OUT : out std_logic;
PC_SUB_SIZE_OUT : out std_logic_vector(31 downto 0);
PC_TRIG_NR_OUT : out std_logic_vector(31 downto 0);
signal found_empty_evt_comb : std_logic;
signal found_empty_evt_ctr : std_logic_vector(31 downto 0);
+-- gk 06.10.10
+signal message_size : std_logic_vector(31 downto 0);
+
+-- gk 07.12.10
+signal prev_bank_select : std_logic_vector(3 downto 0);
+signal first_event : std_logic;
+
begin
BANK_SELECT_OUT <= bank_select; -- gk 27.03.10
end if;
end process loadMachineProc;
-loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting)
+loadMachine : process( loadCurrentState, sf_aempty, remove_done, read_done, padding_needed, PC_READY_IN, load_sub_done, pc_sub_size, MIN_MESSAGE_SIZE_IN, MAX_MESSAGE_SIZE_IN, pc_trig_nr, first_run_trg, endpoint_addr, first_run_addr, load_eod, event_waiting, bank_select, prev_bank_select)
begin
loadNextState <= LIDLE;
rst_rem_ctr_comb <= '0';
when LIDLE =>
state2 <= x"0";
-- gk 23.07.10
- if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10
+ --if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then -- gk 06.08.10
+ -- gk 04.12.10
+ if( (sf_aempty = '0') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then
loadNextState <= INIT;
rst_rem_ctr_comb <= '1';
rst_regs_comb <= '1';
state2 <= x"1";
loadNextState <= REMOVE;
rem_phase_comb <= '1';
+-- when REMOVE =>
+-- state2 <= x"2";
+-- if( remove_done = '1' ) then
+-- loadNextState <= WAIT_TO_REMOVE;
+-- inc_trg_ctr_comb <= '1';
+-- else
+-- loadNextState <= REMOVE;
+-- rem_phase_comb <= '1';
+-- end if;
+ -- gk 03.12.10
when REMOVE =>
state2 <= x"2";
if( remove_done = '1' ) then
- loadNextState <= WAIT_TO_REMOVE;
+ -- gk 06.10.10
+ if (MULT_EVT_ENABLE_IN = '1') then
+ if (message_size + pc_sub_size < MAX_MESSAGE_SIZE_IN) then
+ -- gk 07.12.10
+ if (first_event = '0') and (prev_bank_select /= bank_select) then -- check if event builder address changed, if so close the current packet
+ loadNextState <= WAIT_PC;
+ else
+ loadNextState <= WAIT_TO_REMOVE;
+ end if;
+ else
+ loadNextState <= WAIT_PC;
+ end if;
+ else
+ loadNextState <= WAIT_TO_REMOVE;
+ end if;
inc_trg_ctr_comb <= '1';
else
loadNextState <= REMOVE;
rem_phase_comb <= '1';
end if;
+
when WAIT_TO_REMOVE =>
if (rem_ctr = x"a") then
loadNextState <= DECIDE;
state2 <= x"9";
loadNextState <= CALCC;
pad_data_comb <= '1';
+-- when CALCC =>
+-- state2 <= x"a";
+-- loadNextState <= CLOSE;
+-- pc_eod_comb <= '1';
+ -- gk 04.12.10
when CALCC =>
state2 <= x"a";
- loadNextState <= CLOSE;
+ if (MULT_EVT_ENABLE_IN = '1') then
+ loadNextState <= LIDLE;
+ else
+ loadNextState <= CLOSE;
+ end if;
pc_eod_comb <= '1';
when CLOSE =>
state2 <= x"b";
loadNextState <= WAIT_PC;
rst_regs_comb <= '1';
+-- when WAIT_PC =>
+-- state2 <= x"c";
+-- if( PC_READY_IN = '1' ) then
+-- loadNextState <= LIDLE;
+-- else
+-- loadNextState <= WAIT_PC;
+-- end if;
+ -- gk 03.12.10
when WAIT_PC =>
state2 <= x"c";
if( PC_READY_IN = '1' ) then
- loadNextState <= LIDLE;
+ -- gk 06.10.10
+ if (MULT_EVT_ENABLE_IN = '1') then
+ loadNextState <= WAIT_TO_REMOVE;
+ else
+ loadNextState <= LIDLE;
+ end if;
else
loadNextState <= WAIT_PC;
end if;
end case;
end process loadMachine;
+-- gk 07.10.10
+PC_EOS_OUT <= '1' when (MULT_EVT_ENABLE_IN = '1') and (pc_eod = '1') else '0';
+
-- gk 25.07.10
INVALID_STATS_PROC : process(CLK)
begin
begin
if rising_edge( CLK ) then
-- gk 29.03.10
- if( (RESET = '1') or (rst_regs = '1') ) then
+ if ((RESET = '1') or (rst_regs = '1')) then
bank_select <= "0000";
-- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"2")) then
bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
end if;
end if;
end process bank_select_proc;
+-- gk 07.12.10
+first_event_proc : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') or (loadCurrentState = WAIT_PC) then
+ first_event <= '1';
+ elsif (remove_done = '1') then
+ first_event <= '0';
+ end if;
+ end if;
+end process first_event_proc;
+
+-- gk 07.12.10
+prev_bank_proc : process(CLK)
+begin
+ if (RESET = '1') or (loadCurrentState = WAIT_PC) then
+ prev_bank_select <= "0000";
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"3") and (first_event = '1')) then
+ prev_bank_select <= bank_select;
+ end if;
+end process prev_bank_proc;
+
-- gk 29.03.10
start_config_proc : process( CLK )
begin
if rising_edge( CLK ) then
- if( (RESET = '1') or (config_done = '1') or (rst_regs = '1') ) then
+ if ((RESET = '1') or (config_done = '1') or (rst_regs = '1')) then
start_config <= '0';
- elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then -- gk 01.06.10
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"2") and (first_event = '1')) then -- gk 01.06.10
start_config <= '1';
end if;
end if;
end if;
end process THE_SUB_SIZE_PROC;
+-- gk 06.10.10
+MESSAGE_SIZE_PROC : process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (RESET = '1') then
+ message_size <= x"0000_0028";
+ elsif ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1')) then
+ message_size <= x"0000_0028";
+ elsif ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1')) then
+ message_size <= x"0000_0028";
+ elsif (pc_sos = '1') then
+ message_size <= message_size + pc_sub_size + x"10"; -- gk 06.12.10 add 16B for subevent headers
+ end if;
+ end if;
+end process MESSAGE_SIZE_PROC;
+
-- gk 25.07.10
ENDP_ADDRESS_PROC : process(CLK)
begin
dbg_bs_proc : process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
+ if (RESET = '1') then
debug(15 downto 12) <= (others => '0');
- elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
+ elsif ((sf_rd_en = '1') and (rem_ctr = x"3")) then
debug(15 downto 12) <= bank_select;
end if;
end if;
end process dbg_bs_proc;
debug(16) <= config_done;
-debug(17) <= remove_done;
+debug(17) <= '0'; --remove_done;
debug(18) <= read_done;
debug(19) <= padding_needed;
CTS_LENGTH_OUT <= cts_length;
PC_SOS_OUT <= pc_sos;
-PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q;
+--PC_EOD_OUT <= pc_eod; -- gk 26.07.10 --pc_eod_q;
+PC_EOD_OUT <= '1' when ((MULT_EVT_ENABLE_IN = '0') and (pc_eod = '1'))
+ or ((MULT_EVT_ENABLE_IN = '1') and (message_size + pc_sub_size >= MAX_MESSAGE_SIZE_IN) and (remove_done = '1'))
+ -- gk 07.12.10
+ or ((MULT_EVT_ENABLE_IN = '1') and (prev_bank_select /= bank_select) and (remove_done = '1'))
+ else '0'; -- gk 07.10.10
PC_DATA_OUT <= pc_data_q;
PC_WR_EN_OUT <= pc_wr_en_qq;
FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0);
TTL_IN : in std_logic_vector(7 downto 0);
PROTOCOL_IN : in std_logic_vector(7 downto 0);
+ FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- gk 09.12.10
-- ports for packetTransmitter
RD_CLK : in std_logic; -- 125MHz clock!!!
FT_DATA_OUT : out std_logic_vector(8 downto 0);
GBE_READOUT_CTR_VALID_OUT : out std_logic; -- gk 26.04.10
GBE_DELAY_OUT : out std_logic_vector(31 downto 0);
GBE_ALLOW_LARGE_OUT : out std_logic;
+ GBE_FRAME_DELAY_OUT : out std_logic_vector(31 downto 0); -- gk 09.12.10
-- gk 28.07.10
MONITOR_BYTES_IN : in std_logic_vector(31 downto 0);
MONITOR_SENT_IN : in std_logic_vector(31 downto 0);
jspc29 / trbnet.git / commitdiff