-The schematics of the new CTS AddOn can be found in \cite{CTS}.
+%The schematics of the new CTS AddOn can be found in \cite{CTS}.
Register addresses from 0xA000 to 0xA0ef is SCM FPGA (1)
Register addresses from 0xA0f0 to 0xA0ff is ECP2M FPGA (2)
-Register addresses from 0xA100 to 0xA100 + 10*Number of samples per beam structure (currently 50) is from SCM FPGA (1)
+Register addresses from 0xA100 to 0xA100 + 10*500 which is number of samples per beam structure, the histograms are created in the SCM FPGA (1) see fig. \ref{ctsbeam}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CTS Control Registers}
\begin{description}
\item [0xA0C0] LVL1 trigger settings:
\begin{description}
- \item[Bit 4 -- 0] If (4)=0 then standard trigger selection else trigger code = (3 downto 0)
- \item[Bit 5] MDC calibration trigger enable
- \item[Bit 6] Force update Shower pedestals trigger (write ..1..0)
- \item[Bit 7] Disable Shower pedestals update (generated once during each spill off)
+ \item[Bit 4 -- 0] If bit 4 = 0 then standard trigger selection, else trigger code = bits 3 down to 0
+ \item[Bit 5] MDC calibration trigger enable - send each second
+ \item[Bit 6] Force update Shower pedestals trigger (write 1..0)
+ \item[Bit 7] Disable Shower pedestals update (update is generated once during each spill off)
\item[Bit 8] Enable Shower calibration trigger
- \item[Bit 9] Enable test trigger 0xE
- \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register xxx
- \item[Bit 15] Enable beam inhibit to make system silent(only cal trigger are accepted) when there is no beam - look into beam inhibit signal settings register xxx
- \item[Bit 16] Enable TOF/RPC to be a Start signal
- \item[Bit 23 -- 20] Set width for VETO signal used for anti-coincidence logic - $value * 1.25\,ns$
+ \item[Bit 9] Enable test trigger 0xE which is send each second
+ \item[Bit 10] Disable all triggers
+ \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register 0xA0DD
+ \item[Bit 15] Enable beam inhibit to make system silent when there is no beam (only cal trigger are accepted) - look into beam inhibit signal settings register 0xA0DD
+ \item[Bit 16] Enable TOF/RPC multiplicity signnals to be treated as a Start signal see Fig.\ref{cts_logic}
+ \item[Bit 23 -- 20] Set width for VETO signal used for anti cincoincidence logic - $value * 1.25\,ns$
\item[Bit 28] Select source for beam structure A - 0 Start, 1 RPC/TOF
\item[Bit 29] Select source for beam structure B - 0 Start, 1 RPC/TOF
\item[Bit 30] When set to '1' it generates RICH special APV trigger (double pulse on RICH connector) - edge sensitive 0 -> 1
- \item[Bit 31] Enable trigger line test, this works together with self trigger (set the required frequency)
+ \item[Bit 31] Enable trigger line test, this works together with self trigger pulser (set the required frequency)
\end{description}
\item [0xA0C1] LVL1/LVL2 trigger settings:
\begin{description}
- \item[Bit 16 -- 12] Delay (to the feasts trigger) of MDCB (MDC 3/4) trigger = value * 20 ns
+ \item[Bit 16 -- 12] Delay (from the fastes trigger) of MDCB (MDC 3/4) trigger = value * 20 ns
\item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns
\item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns
\end{description}
\item [0xA0C2] Multiplexers output select:
\begin{description}
- \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the Fig.\ref{cts_logic})
+ \item[Bit 7 -- 0] Selects the output signal for LVDS OUT(4) (the order like on the fig.\ref{cts_logic}) to see internal FPGA signals after diferent stages of signal processing
\begin{description}
- \item 35 - 0 After one clock
- \item 71 - 36 After delay
- \item 72 - 107 After set width
- \item 126 - 108 empty
- \item 127 - start signal used for anti-coincidence logic (after OR)
- \item 128 - veto signal used for anti-coincidence logic (after Width S.)
- \item 129 - inconsistency signal
+ \item 7 - 0, After one clock Start 7 - 0 (first address 0x0)
+ \item 15 - 8 After one clock Veto 7 - 0 (0x8)
+ \item 21 - 16 After one clock TOF 6 - 1 (0x10)
+ \item 27 - 22 After one clock RPC 6 - 1 (0x16)
+ \item 35 - 28 After one clock PT 8 - 1 (0x1C)
+ \item 43 - 36 After delay Start 7 - 0 (0x24)
+ \item 51 - 44 After delay Veto 7 - 0 (0x2C)
+ \item 57 - 52 After delay TOF 6 - 1 (0x34)
+ \item 63 - 58 After delay RPC 6 - 1 (0x3A)
+ \item 71 - 64 After delay PT 8 - 1 (0x40)
+ \item 80 - 72 Multiplicity 2 opposite sectors, 3 no neighbour, 2 no neighbour, 6, 5, 4, ..1 (0x48)
+ \item 87 - 81 Empty
+ \item 93 - 88 TOF sectors after width (0x58)
+ \item 99 - 94 RPC sectors after width (0x5E)
+ \item 107 - 100 PT signals after width (0x64)
+ \item 126 - 108 not used (reserved for output) (0x6C)
+ \item 127 - start signal used for anti coincidence (0x7F)
+ \item 128 - veto signal (after setting witdh 0xA0C0(23 -- 20)) used for anti coincidence (0x80)
+ \item 129 - anti coincidence signal (0x81)
+ \item 255 - 130 not used
\end{description}
\item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4))
- \item[Bit 31 -- 28] Data version set into the data stream from the CTS (see CTS data structure chapter)
+ \item[Bit 31 -- 28] Data version set into the data stream from the CTS (see a CTS data structure chapter)
\end{description}
- \item [0xA0C4 -- 0xA0C3] Enable inputs (order as on the Fig.\ref{cts_logic})
+ \item [0xA0C4 -- 0xA0C3] Enable CTS trigger inputs (order as on the Fig.\ref{cts_logic})
\item [0xA0C5] TS gating disable
\item [0xA0C6] Global time offset for 8 START channels used for beam structure
- \item [0xA0C7] Enable outputs
- \item [0xA0C8] Sample period for 8 START channels - $value*100ns$ for individual start beam structure
- \item [0xA0D0 -- 0xA0C9] Downscale registers - $2^{value}$
- \item [0xA0D8 -- 0xA0D1] Delay registers - $value * 1,25\,ns$
- \item [0xA0D9] -- time offset for beam structure A (after BEAM START signal)
+ \item [0xA0C7] Enable trigger outputs
+ \item [0xA0C8] Sample period for 8 START channels - $value*100ns$ for individual start beam structure see fig. \ref{ctsbeam}
+ \item [0xA0D0 -- 0xA0C9] Registers for downscaling incoming signals, only $2^{value}$ is passing.
+ \item [0xA0D8 -- 0xA0D1] Registers for making a delay of the signal - $value * 1,25\,ns$
+ \item [0xA0D9] -- time offset for beam structure A (after BEAM START signal)
\item [0xA0DA] -- time offset for beam structure B (after BEAM START signal)
\item [0xA0DB] -- Sample period for beam structure A - $value*100ns$
\item [0xA0DC] -- Sample period for beam structure B - $value*100NM$
\item [0xA0DD] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$
- \item [0xA0E3] Self trigger
+ \item [0xA0E3] Pulser for triggering the system with different frequencies
\begin{description}
\item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $
\end{description}
\item[Bit 6 -- 0] LVL1 trigger information(6 -- 0)
\item[Bit 13 -- 8] LVL1 trigger information(13 -- 8)
\end{description}
- \item [0xA0E7 -- 0xA0E5] Large delay registers - $value * 5\,ns$
- \item [0xA0EC -- 0xA0E8] Width registers - $5 + value * 4\,ns$
+ \item [0xA0E7 -- 0xA0E5] Delay the signals with large values - $value * 5\,ns$
+ \item [0xA0EC -- 0xA0E8] Set width of the signals - $5 + value * 4\,ns$
% \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
% \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set
\item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data
\item[Bit 23 -- 0] Number of events per EB
\end{description}
\item [0xA0F2] Mask for making busy based on LVL1 information sent back from the endpoints (when set to 1 and if LVL1 info is also 1 the busy will be created)
-\end{description}
+ \item [0xA0F3] Special treatment of calibration triggers
+ \begin{description}
+ \item[Bit 3 -- 0] Which EB is used as a destination for the calibration triggers
+ \item[Bit 11 -- 4] Selecting ('1') which calibration events should go to chosen EB. Bit 4 corresponds to cal trigger 0x8, bit 5 0x9, bit 6 0xA ...bit 10 0xE, bit 11 0xF
+ \end{description}
+ \end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{CTS Status Registers}
\end{description}
\item[0xA131 - 0xA100] - beam structure A
\item[0xA163 - 0xA132] - beam structure B
- \item[0xA195 - 0xA1C7] - Start structure input 1
+ \item[0xA195 - 0xA164] - beam structure B
+ \item[0xA1C7 - 0xA195] - Start structure input 1
\item[0xA1F9 - 0xA1C8] - Start structure input 2
\item[0xA22B - 0xA1FA] - Start structure input 3
\item[0xA25D - 0xA22C] - Start structure input 4
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