The current system clock configuration is shown on two LEDs on the front-panel.
\begin{itemize*}
\item The board has own 200 MHz and 125 MHz oscillators. The internal 200 MHz will be selected if there is no external clock available at power-up.
- \item A external clock can be fed in via the RJ-45 connector (left, pair 2) or from the backplane. The source is selected with a switch. At power-up the board searches for an external clock on the selected input. If none is found, the internal is used.
+ \item A external clock can be fed in via the RJ-45 connector (inner connector, pair 2) or from the backplane. The source is selected with a switch. At power-up the board searches for an external clock on the selected input. If none is found, the internal clock is used.
\item The system clock can be recovered from the SFP1 input signal. This is selected at compile-time (only in special setups).
\end{itemize*}
\begin{itemize*}
\item The default reference time input is pair 1 on the inner RJ-45 on the front-panel
\item The reference time can be supplied from the backpanel, selected by the switch (same as clock setting)
- \item The outer RJ-45 supports four trigger output signals.
+ \item The outer RJ-45 supports four trigger output signals. Note the order of channels which doesn't match the numbering in the GUI: Pair 1,2,3,4 are trigger logic outputs 2,3,0,1.
\end{itemize*}
\subsection{CTS: Reference time / Trigger Input/Output}
\begin{itemize*}
\item The default reference time output is on pair 1 on the outer RJ-45 on the front-panel
- \item The inner RJ-45 supports two trigger input signals on pairs 3 and 4.
+ \item The inner RJ-45 supports two trigger input signals on pairs 3 and 4. These are named "trig\_rj[N]" in the CTS GUI
+ \item The outer RJ-45 can have different functions depending on the CTS design in use:
+ \begin{itemize*}
+ \item Pair 2: Input for MBS or R3B serial trigger signals. Reset signal for timestamp generator
+ \item Pair 3: R3B trigger signal output. Output of CTS Monitor \#0.
+ \item Pair 4: Output of CTS Monitor \#1. Trigger Busy signal in few designs
+ \end{itemize*}
\end{itemize*}
6 & SPI CE\\
7 & I2C SDA\\
8 & I2C SCL\\
- 9 & \\
- 10 & \\
+ 9 & Debug UART RX\\
+ 10 & Debug UART TX\\
11 & 3.3V\\
12 & 3.3V\\
13 & GND\\
SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 8 is reserved for HDR\_IO.
-Optionally, a LCD can be connected. In this case SPI channel 8 is not used.
\subsection{Serial Links}
By default, SFP1 (inner) is used for GbE, SFP2 for TrbNet (outer).