package body trb_net_std is
+ type CTRLBUS_TX is record
+ data : std_logic_vector(31 downto 0);
+ ack : std_logic;
+ unknown : std_logic;
+ nack : std_logic;
+ end record;
+
+ type CTRLBUS_RX is record
+ data : std_logic_vector(31 downto 0);
+ addr : std_logic_vector(15 downto 0);
+ write : std_logic;
+ read : std_logic;
+ timeout : std_logic;
+ end record;
+
function and_all (arg : std_logic_vector)
return std_logic is
variable tmp : std_logic := '1';