i hate module generators.

diff --git a/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
index fbd431502c2a1282a3555221dd2f2c79411c2d3e..5c6d93338b357c79d92b15c50d1961a56afb11b2 100755 (executable)
--- a/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
+++ b/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
@@ -9,7 +9,7 @@ use IEEE.std_logic_1164.all;
 \r
 entity PCSC is\r
 GENERIC(\r
-  CONFIG_FILE : String  := "serdes_gbe_2.txt"\r
+  CONFIG_FILE : String  := "serdes_gbe_all.txt"\r
   );\r
 port (\r
   HDINN0             : in std_logic;\r
@@ -1272,8 +1272,8 @@ library IEEE, STD;
 use IEEE.std_logic_1164.all;\r
 use STD.TEXTIO.all;\r
 \r
-entity serdes_gbe_2 is\r
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_gbe_2.txt");\r
+entity serdes_gbe_all is\r
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_gbe_all.txt");\r
  port (\r
    core_txrefclk : in std_logic;\r
    core_rxrefclk : in std_logic;\r
@@ -1389,9 +1389,9 @@ entity serdes_gbe_2 is
    refck2core : out std_logic;\r
    ffs_plol : out std_logic);\r
 \r
-end serdes_gbe_2;\r
+end serdes_gbe_all;\r
 \r
-architecture serdes_gbe_2_arch of serdes_gbe_2 is\r
+architecture serdes_gbe_all_arch of serdes_gbe_all is\r
 \r
 component VLO\r
 port (\r
@@ -2263,4 +2263,4 @@ BEGIN
 END PROCESS;\r
 --synopsys translate_on\r
 \r
-end serdes_gbe_2_arch ;\r
+end serdes_gbe_all_arch ;\r