*** empty log message ***

diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c
index 8247c3f90fc0bb1b00d329140fb198ee2a68379d..5c02b3104f9f52a0ba94b9f4917393c96923f4eb 100644 (file)
--- a/libtrbnet/trbnet.c
+++ b/libtrbnet/trbnet.c
@@ -352,7 +352,7 @@ static int trb_fifo_read(uint8_t channel,
   unsigned int dataCtr = 0;
   int packageCtr = -1;
   unsigned int endPointCtr = 0;
-
+  
   unsigned int timeout = 0;
 
   /* Determin FIFO-Address */
@@ -379,8 +379,8 @@ static int trb_fifo_read(uint8_t channel,
   }
 
   if (timeout >= MAX_TIME_OUT) {
-    trb_errno = TRB_FIFO_TIMEOUT;
     trb_fifo_flush(channel);
+    trb_errno = TRB_FIFO_TIMEOUT;
     return -1;
   }
 
@@ -714,22 +714,26 @@ static int trb_fifo_read(uint8_t channel,
     }
 
     /* Read Next Word */
+    if (headerType == HEADER_TRM) {
+      break;
+    }
     if (trb_dma == 1) {
       tmp++;
     } else {
-     timeout = 0;
-     do {
-      read32_from_FPGA(fifoBuffer, tmp);
-    } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT));
+      timeout = 0;
+      do {
+       read32_from_FPGA(fifoBuffer, tmp);
+      } while (((*tmp & MASK_FIFO_VALID) == 0) && (++timeout < MAX_TIME_OUT));
+      
       if (timeout >= MAX_TIME_OUT) {
-      trb_errno = TRB_FIFO_TIMEOUT;
-      trb_fifo_flush(channel);
-      return -1;
-     }
+       trb_fifo_flush(channel);
+       trb_errno = TRB_FIFO_TIMEOUT;
+       fprintf(stderr,"timeout\n");
+       return -1;
+      }
     }
   }
-
-
+  
   /* Copy StatusBits and Sequenze of TerminationPackage */
   trb_term.status_common = package.F2;
   trb_term.status_channel =  package.F1;