changing ecp5 fifo name to ecp3 for compatibility

diff --git a/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst
new file mode 100644 (file)
index 0000000..78f3412
--- /dev/null
+++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.cst
@@ -0,0 +1,3 @@
+Date=01/11/2016
+Time=11:48:07
+

diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc
similarity index 100%
rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc
rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc

diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc
similarity index 85%
rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc
rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc
index 133ab93c53d4a4109773e53ccc24a97eee7f326a..0ac45ac12f06438c03a24c7f2f573949815cb0a6 100644 (file)
--- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.lpc
+++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.lpc
@@ -13,11 +13,11 @@ CoreType=LPM
 CoreStatus=Demo
 CoreName=FIFO_DC
 CoreRevision=5.8
-ModuleName=lattice_ecp5_fifo_18x16_dualport_oreg
+ModuleName=lattice_ecp3_fifo_18x16_dualport_oreg
 SourceFormat=vhdl
 ParameterFileVersion=1.0
-Date=01/04/2016
-Time=13:35:37
+Date=01/11/2016
+Time=11:48:07
 
 [Parameters]
 Verilog=0
@@ -50,4 +50,4 @@ WDataCount=0
 EnECC=0
 
 [Command]
-cmd_line= -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7
+cmd_line= -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7

diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx
similarity index 96%
rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx
rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx
index 1aea6d1a1aca0ac77919a369a5f42b3fb7b6522b..1a899bbc4500078201c731e73049f8da99dd2064 100644 (file)
--- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.sbx
+++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.sbx
@@ -1,4 +1,4 @@
-<!DOCTYPE lattice_ecp5_fifo_18x16_dualport_oreg>
+<!DOCTYPE lattice_ecp3_fifo_18x16_dualport_oreg>
 <lattice:project mode="SingleComponent">
     <spirit:component>
         <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
@@ -10,7 +10,7 @@
                 <spirit:name>Diamond_Simulation</spirit:name>
                 <spirit:group>simulation</spirit:group>
                 <spirit:file>
-                    <spirit:name>./lattice_ecp5_fifo_18x16_dualport_oreg.vhd</spirit:name>
+                    <spirit:name>./lattice_ecp3_fifo_18x16_dualport_oreg.vhd</spirit:name>
                     <spirit:fileType>vhdlSource</spirit:fileType>
                 </spirit:file>
             </spirit:fileset>
@@ -18,7 +18,7 @@
                 <spirit:name>Diamond_Synthesis</spirit:name>
                 <spirit:group>synthesis</spirit:group>
                 <spirit:file>
-                    <spirit:name>./lattice_ecp5_fifo_18x16_dualport_oreg.vhd</spirit:name>
+                    <spirit:name>./lattice_ecp3_fifo_18x16_dualport_oreg.vhd</spirit:name>
                     <spirit:fileType>vhdlSource</spirit:fileType>
                 </spirit:file>
             </spirit:fileset>
@@ -38,8 +38,8 @@
         <spirit:vendorExtensions>
             <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
             <lattice:synthesis>synplify</lattice:synthesis>
-            <lattice:date>2016-01-04.01:35:39 PM</lattice:date>
-            <lattice:modified>2016-01-04.01:35:39 PM</lattice:modified>
+            <lattice:date>2016-01-11.11:48:08 AM</lattice:date>
+            <lattice:modified>2016-01-11.11:48:08 AM</lattice:modified>
             <lattice:diamond>3.6.0.83.4</lattice:diamond>
             <lattice:language>VHDL</lattice:language>
             <lattice:attributes>
@@ -109,11 +109,11 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Date</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">01/11/2016</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>ModuleName</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">lattice_ecp5_fifo_18x16_dualport_oreg</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">lattice_ecp3_fifo_18x16_dualport_oreg</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
@@ -125,7 +125,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Time</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">13:35:37</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">11:48:07</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>VendorName</lattice:lpckey>
@@ -247,7 +247,7 @@
                 <lattice:lpcsection lattice:name="Command"/>
                 <lattice:lpcentry>
                     <lattice:lpckey>cmd_line</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">-w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7</lattice:lpcvalue>
                 </lattice:lpcentry>
             </lattice:lpc>
             <lattice:groups/>
@@ -256,7 +256,7 @@
     <spirit:design>
         <spirit:vendor>LATTICE</spirit:vendor>
         <spirit:library>LOCAL</spirit:library>
-        <spirit:name>lattice_ecp5_fifo_18x16_dualport_oreg</spirit:name>
+        <spirit:name>lattice_ecp3_fifo_18x16_dualport_oreg</spirit:name>
         <spirit:version>1.0</spirit:version>
         <spirit:componentInstances/>
         <spirit:adHocConnections/>

diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
similarity index 98%
rename from lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd
rename to lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
index 61a801ba1227bc9393677c1695bbab9825a7d4b7..d1ce8ab731b46044132d6cac2ecaa4f4500b11b3 100644 (file)
--- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.vhd
+++ b/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd
@@ -1,15 +1,15 @@
 -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4
 -- Module  Version: 5.8
---/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp5_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.fdc 
+--/d/jspc29/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n lattice_ecp3_fifo_18x16_dualport_oreg -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 16 -width 18 -rwidth 18 -regout -no_enable -reset_rel SYNC -pe -1 -pf 7 -fdc /d/jspc22/trb/git/trbnet/lattice/ecp5/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.fdc 
 
--- Mon Jan  4 13:35:39 2016
+-- Mon Jan 11 11:48:08 2016
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 library ecp5um;
 use ecp5um.components.all;
 
-entity lattice_ecp5_fifo_18x16_dualport_oreg is
+entity lattice_ecp3_fifo_18x16_dualport_oreg is
     port (
         Data: in  std_logic_vector(17 downto 0); 
         WrClock: in  std_logic; 
@@ -22,9 +22,9 @@ entity lattice_ecp5_fifo_18x16_dualport_oreg is
         Empty: out  std_logic; 
         Full: out  std_logic; 
         AlmostFull: out  std_logic);
-end lattice_ecp5_fifo_18x16_dualport_oreg;
+end lattice_ecp3_fifo_18x16_dualport_oreg;
 
-architecture Structure of lattice_ecp5_fifo_18x16_dualport_oreg is
+architecture Structure of lattice_ecp3_fifo_18x16_dualport_oreg is
 
     -- internal signal declarations
     signal invout_1: std_logic;
@@ -159,7 +159,7 @@ architecture Structure of lattice_ecp5_fifo_18x16_dualport_oreg is
     attribute MEM_LPC_FILE : string; 
     attribute MEM_INIT_FILE : string; 
     attribute GSR : string; 
-    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp5_fifo_18x16_dualport_oreg.lpc";
+    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc";
     attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
     attribute GSR of FF_57 : label is "ENABLED";
     attribute GSR of FF_56 : label is "ENABLED";

diff --git a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst b/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst
deleted file mode 100644 (file)
index ca5c7e3..0000000
--- a/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport_oreg/lattice_ecp5_fifo_18x16_dualport_oreg.cst
+++ /dev/null
@@ -1,3 +0,0 @@
-Date=01/04/2016
-Time=13:35:37
-