slow control table is updated - cu

diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex
index f878f41d49aefadee45e2ed936a14e152efe079a..9faa1f2fee28d3947cdec21a7b0e0b067933803e 100644 (file)
--- a/trb3/TdcSlowControl.tex
+++ b/trb3/TdcSlowControl.tex
@@ -6,13 +6,13 @@ A set of control registers are assigned in order to access the basic controls, e
       \hline
       Address  & \multicolumn{1}{c|}{Name}     & Bits  & \multicolumn{1}{c|}{Explanation}\\
       \hline \hline
-      \multirow{10}{*}{0xc0}   & \multirow{10}{*}{Basic controls}      & 3-0   & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
+      \multirow{11}{*}{0xc0}   & \multirow{11}{*}{Basic controls}      & 3-0   & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\
                                &                                       & 4     & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\
                                &                                       & 11-5  & reserved.\\
                                &                                       & 12    & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\
                                &                                       & 31-13 & reserved.\\
       \hline
-      \multirow{8}{*}{0xc1}    & \multirow{8}{*}{Trigger window}       & 10-0  & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
+      \multirow{10}{*}{0xc1}   & \multirow{10}{*}{Trigger window}      & 10-0  & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\
                                &                                       & 15-11 & reserved.\\
                                &                                       & 26-16 & Defines the trigger window width after the trigger with granularity of 5~ns. \textbf{ATTENTION! Minimum value can be set is x"00f".}\\
                                &                                       & 30-27 & reserved.\\
@@ -23,6 +23,9 @@ A set of control registers are assigned in order to access the basic controls, e
       \hline
       0xc3                     & Channel enable 2                      & 31-0  & Enable signals for the channels 33-64.\\
       \hline
+      \multirow{3}{*}{0xc4}    & \multirow{3}{*}{Channel hit scaler control}   & 7-0   & Defines the channel number of the scaler register (Status register 0x90).\\
+                                &                                       & 31-8  & reserved.\\
+      \hline
     \end{tabularx}
   \caption{The control registers of the TDC.}
   \label{tab:tdcControlReg}
@@ -117,14 +120,16 @@ A set of control registers are assigned in order to access the basic controls, e
       \hline
       Address  & \multicolumn{1}{c|}{Name}     & Bits  & \multicolumn{1}{c|}{Explanation}\\
       \hline \hline
-      \multirow{2}{*}{0x80}    & \multirow{2}{3.5cm}{Basic controls}   & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
-                               &                                       & 31-8  & reserved\\ \hline
+      \multirow{5}{*}{0x80}    & \multirow{5}{3.5cm}{Basic controls}   & 7-0   & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\
+                               &                                       & 15-8  & Implemented channel number.\\
+                               &                                       & 16    & Reference time synchronised to 100~MHz TrbNet clock.\\
+                               &                                       & 31-17 & reserved\\ \hline
       0x81                     & Empty channels 1                      & 31-0  & Empty signals of the channels 32-1\\ \hline
       0x82                     & Empty channels 2                      & 31-0  & Empty signals of the channels 64-33\\ \hline
       \multirow{6}{*}{0x83}    & \multirow{6}{3.5cm}{Trigger window controls}  & 10-0  & Trigger window width before the trigger with granularity of 5~ns\\
                                &                                       & 15-11 & reserved\\
                                &                                       & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\
-                               &                                       & 15-11 & reserved\\ \hline
+                               &                                       & 31-27 & reserved\\ \hline
       \multirow{2}{*}{0x84}    & \multirow{2}{3.5cm}{Trigger number}   & 23-0  & Number of valid triggers received\\
                                &                                       & 31-24 & reserved\\ \hline
       \multirow{2}{*}{0x85}    & \multirow{2}{3.5cm}{Valid timing trigger number}      & 23-0  & Number of valid timing triggers received\\
@@ -161,10 +166,12 @@ A set of control registers are assigned in order to access the basic controls, e
                                &                                       & 31-24 & reserved\\ \hline
       \multirow{2}{*}{0x8f}    & \multirow{2}{3.5cm}{Release Number}   & 23-0  & Number of release signals sent\\
                                &                                       & 31-24 & reserved\\ \hline
+      \multirow{3}{*}{0x90}    & \multirow{3}{3.5cm}{Channel Scaler}   & 23-0  & Number of hits detected by a channel. Channel number is controlled with register 0xc4\\
+                               &                                       & 31-24 & reserved\\ \hline
     \end{tabularx}
   \caption{The status registers of the TDC. (Continue)}
   \label{tab:tdcStatusReg2}
   \end{center}
 \end{table}
 
-The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}.
\ No newline at end of file
+The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1} and Table \ref{tab:tdcStatusReg2}.