}
-\abstract{The TRB3 features four FPGA-based TDCs with $<20$\,ps
+\abstract{The TRB3 features four FPGA-based TDCs with ${<20}$\,ps
RMS time precision between two channels and $256+4+4$ channels in
total. One central FPGA provides flexible trigger functionality and
GbE connectivity including powerful slow control. We present recent
\end{figure}
Usually, in each of the four peripheral FPGAs a tapped delay line TDC
-is implemented with $<20$\,ps RMS time precision between two channels
+is implemented with ${<20}$\,ps RMS time precision between two channels
providing $64$ channels plus one reference channel, see
\cref{sec:tdc}. The TDCs are typically used for leading edge
measurements or---by using the TDC channels in pairs---one can
firmwares on the command line to high-level control via web2.0
technologies, see \cref{sec:software}. This is complemented by
comprehensive specifications and documentations \cite{trb-web}
-provided by the large user base from the experiments HADES and PANDA
+provided by the large user base including the experiments HADES/CBM and PANDA
at GSI in Darmstadt, Germany.
In \cref{sec:frontends} existing front-ends and applications are
beamtimes are summarised in which the TRB3 platform has been
successfully deployed.
-\section{Precise Time Digitisation in FPGA}\label{sec:tdc}
+\section{Precise Time Digitisation in FPGAs}\label{sec:tdc}
One key component of the TRB3 is the $64+1$ channel time-to-digital converter
(TDC) implemented in the peripheral FPGAs of the TRB3 with a time precision
\subsection{Central Trigger System and Slow Control}
The TRB3 firmwares as part of the HADES experiment use the TrbNet
-\cite{michel-twepp2011} for asynchronous read-out and busy-release
-scheme trigger distribution. Its configuration can be transparently
-controlled via command line tools including bindings to PERL.
-Furthermore, a Central Trigger System was developed
-\cite{penschuck-bachelor}, which provides an user-friendly interface
-with web2.0 interactivity (\cref{fig:trb3}b). The maximum trigger rate
-is $700$\,kHz and owing to its modular design, external trigger
-information can be easily integrated. Currently, modules for the
-experiments CBM \cite{cbm-web} and A2@MAMI \cite{a2-web} decoding the
-trigger event numbers are available.
+\cite{michel-twepp2011} for asynchronous read-out and busy-release scheme
+trigger distribution. Its configuration can be transparently controlled via
+command line tools including bindings to Perl. Furthermore, a Central Trigger
+System was developed \cite{penschuck-bachelor}, which provides an
+user-friendly interface with web2.0 interactivity (\cref{fig:trb3}b). The
+maximum accepted trigger rate of a TRB3 system is $700$\,kHz and owing to the
+modular design of the CTS, external trigger information can be easily
+integrated. Currently, modules for the experiments CBM \cite{cbm-web} and
+A2@MAMI \cite{a2-web} decoding the trigger event numbers are available.
\subsection{TDC Delay Line Calibration and Data Stream Unpacking}
front-end board following the COME\&KISS principle
(\cref{fig:padiwa}). It uses the LVDS input buffers of a Lattice
MachXO2 FPGA to realise a leading edge discriminator for $16$ analogue
-input signals. Besides that, few standard components like $10$x MMIC
-wideband amplifiers and RC low-passes are used to generate the
+input signals. Besides that, few standard components like the MMIC BGA2802
+($20dB$ wideband amplifiers) and RC low-pass filters are used to generate the
threshold voltages via PWM. Using test pulses with an amplitude of
$500$\,$\mu$V and a length of $6$\,ns, a time precision of the full
system including the TRB3 of $23$\,ps was measured
\cite{ugur-twepp2012}. This front-end has been successfully used in
-the test beamtimes, see \cref{sec:juelich,sec:mainz}.
+beamtimes, see \cref{sec:juelich,sec:mainz}.
\subsection{Charge-to-width Front-end for HADES ECAL}
\quad
\begin{minipage}{0.4\linewidth}
\centering
- \includegraphics[width=\textwidth]{gfx/frontends/qdc-schem}\\
+ \includegraphics[width=\textwidth]{gfx/frontends/padiwa-amps1-schematics}\\
(b)
\end{minipage}
\caption{The Charge-to-Width front-end for HADES ECAL. (a) The
detector (\cref{fig:qdc}). It is based on the experience with the PaDiWa board
and provides $8$ input channels (using in total $32$ FPGA TDC channels for two
leading edges and two trailing edges for each input channel) with a charge
-precision of $0.2$\,\% and a high dynamic range of $250$.
+precision of $0.2$\,\% and a high dynamic range of $250$. The board is
+currently in assembly.
\subsection{n-XYTER ASIC for HADES Pion Tracker}
The TRB3 can also be used as an infrastructure to read out specialised
-integrated solutions using the peripheral FPGAs, for example to
-provide a timing reference, transport the acquired data to the
-eventbuilder and slow control configuration of the chip. This was
-realised for the n-XYTER ASIC, which provides the timestamp and the
-pulse height of self-triggered $128$ channels. In this case, the
-integration of the read-out and slow control (e.\,g. trigger windows) on
-the peripheral FPGA was easily achieved due to the well-documented
-VHDL interfaces of the TRB3 platform.
+integrated solutions using the peripheral FPGAs, for example to provide a
+timing reference, transport the acquired data to the eventbuilder and
+configuration of the attached ASIC via slow control. This was realised for the
+n-XYTER ASIC, which provides the digital timestamp and the analoge pulse height of
+self-triggered $128$ channels. In this case, the integration of the read-out
+and slow control (e.\,g. trigger windows) on the peripheral FPGA was easily
+achieved due to the well-documented VHDL interfaces of the TRB3 platform.
+The peripheral FPGA also reads out the ADC for the digitization of the pulse
+height information.
\section{J\"{u}lich Test Beamtime 2012}\label{sec:juelich}
Cherenkov photon detection for PaDiWa with respect to the NINO ASIC,
as seen in the hit patterns, which is probably caused by differences
in the amplification stage (the gain of the latter is $100$ times
-larger). However, the TRB3 provided a stable platform for a successful
+larger **Comment Michael**: I think we can not state that, as we don't know
+the internal structure of the NINO and the physical threshold of the NINO
+discriminators. You can say that the gain is more than a factor of 10 higher....).
+However, the TRB3 provided a stable platform for a successful
test beamtime.
\section{Outlook and Future Developments}\label{sec:outlook}
Finally, we present some planned or ongoing extensions of the
-platform. The detection of leading and trailing edge in a single TDC
+platform: The detection of leading and trailing edge in a single TDC
channel, which doubles the number of channels per board for timestamp
and width measurements. This feature is highly desired for the
described charge-to-width front-end. The temperature independence of
the PaDiWa thresholds and of the TDC calibration is currently
-investigated. There are also two further front-end developments:
+investigated. There are also several further front-end developments:
Integration of the MuPix ASIC for the PANDA luminosity detector and
-the SPADIC ASIC for a TPC in Mainz. Since both ASICs use the CBMnet
+the SPADIC ASIC for a TPC in Mainz. An ~50 channel 10bit 65MSPS ADC AddOn (4
+can be put in one TRB3) is in the layout phase. Since both ASICs use the CBMnet
protocol, an implementation of CBMnet on the TRB3 was started.
Furthermore, an extension of TrbNet with defined propagation delays of
trigger signals for PANDA is being developed and tested.
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