ADC: Make sim work on non-Frankfurt systems, dont forget to actually create the vsim...

diff --git a/ADC/sim/adcprocessor.mpf b/ADC/sim/adcprocessor.mpf
index 26e19eccd7da89c2f8bed5c10c1c7f6a3edf512a..d3ca33b2408f9a6b5ef0607b67eaace304bb431f 100644 (file)
--- a/ADC/sim/adcprocessor.mpf
+++ b/ADC/sim/adcprocessor.mpf
@@ -59,7 +59,7 @@ mc2_lib = $MODEL_TECH/../mc2_lib
 ;mvc_lib = $MODEL_TECH/../mvc_lib
 
 work = work
-ecp3 = /d/jspc29/lattice/diamond/3.2_x64/ispfpga/vhdl/data/ecp3/mti/work
+ecp3 = lattice-diamond/ispfpga/vhdl/data/ecp3/mti/work
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.
@@ -1754,7 +1754,7 @@ Project_File_5 = tb_adcprocessor.vhd
 Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418825986 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_6 = ../../../trbnet/trb_net_std.vhd
 Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409927354 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_7 = /d/jspc22/trb/git/trb3/ADC/cores/mulacc2.vhd
+Project_File_7 = ../cores/mulacc2.vhd
 Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1418830031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_8 = txt_util.vhd
 Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1409066711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002

diff --git a/ADC/sim/lattice-diamond b/ADC/sim/lattice-diamond
new file mode 120000 (symlink)
index 0000000..5a510ac
--- /dev/null
+++ b/ADC/sim/lattice-diamond
@@ -0,0 +1 @@
+lattice-diamond-frankfurt
\ No newline at end of file

diff --git a/ADC/sim/lattice-diamond-frankfurt b/ADC/sim/lattice-diamond-frankfurt
new file mode 120000 (symlink)
index 0000000..d5141dd
--- /dev/null
+++ b/ADC/sim/lattice-diamond-frankfurt
@@ -0,0 +1 @@
+/d/jspc29/lattice/diamond/3.2_x64
\ No newline at end of file

diff --git a/ADC/sim/lattice-diamond-gsi b/ADC/sim/lattice-diamond-gsi
new file mode 120000 (symlink)
index 0000000..3df92e0
--- /dev/null
+++ b/ADC/sim/lattice-diamond-gsi
@@ -0,0 +1 @@
+/opt/lattice/diamond/2.0
\ No newline at end of file