]> jspc29.x-matter.uni-frankfurt.de Git - padiwa.git/commitdiff
Using TRB_CLK(1) for all ADC CSBs signals
authorAndreas Neiser <neiser@kph.uni-mainz.de>
Thu, 24 Jul 2014 14:27:40 +0000 (16:27 +0200)
committerAndreas Neiser <neiser@kph.uni-mainz.de>
Thu, 24 Jul 2014 14:27:40 +0000 (16:27 +0200)
adc_addon/adc_addon.vhd

index 8669caa89b64cb8090a392cc721b7a9387a32ff9..30ee4db7cd97b25094aab336352780aa5f210489 100644 (file)
@@ -212,7 +212,7 @@ architecture adc_addon_arch of adc_addon is
        signal enable_cfg_flash : std_logic;
 
 
-       signal adc_csb_reg : std_logic_vector(12 downto 1) := x"000";
+       --signal adc_csb_reg : std_logic_vector(12 downto 1) := x"000";
 
 begin
 
@@ -382,7 +382,7 @@ begin
                if spi_channel_i(4) = '0' then
                        case spi_channel_i(3 downto 0) is
                                when x"0" => spi_reg20_i <= x"00" & b"000" & leds;
-                               when x"1" => spi_reg20_i <= x"0" & adc_csb_reg;
+        --when x"1" => spi_reg20_i <= x"0" & adc_csb_reg;
                                when others => null;
                        end case;
                else
@@ -401,13 +401,14 @@ begin
                if spi_write_i(2) = '1' then
                        case spi_channel_i(3 downto 0) is
                                when x"0" => leds <= spi_data_i(4 downto 0);
-                               when x"1" => adc_csb_reg <= spi_data_i(11 downto 0);
+                               --when x"1" => adc_csb_reg <= spi_data_i(11 downto 0);
                                when others => null;
                        end case;
                end if;
        end process;
 
-       adc_csb <= not adc_csb_reg; -- active low!
+       adc_csb <= (others => '0') when SPI_TRB_CLK(1) = '0' else (others => '1');
+       --not adc_csb_reg; -- active low!
 
 ---------------------------------------------------------------------------
 -- Rest of the I/O