\item[\portname{Regio\_\-init\_\-address}] The initial network address of the board. Should always be set to a value higher than 0xF000 but lower than 0xFF00. N.B.: This value is currently ignored by the Linux toolchain on Lattice devices.
\item[\portname{Regio\_\-init\_\-board\_\-info}] The value to store in the board information register. This register has not yet been defined.
\item[\portname{Regio\_\-init\_\-endpoint\_\-id}] The endpoint id. Typically a number counting the FPGAs on one PCB (more precise: counting the FPGA connected to one temperature sensor) starting with 1. Exception: The FPGA responsible for readout mostly gets the endpoint id 0.
- \item[\portname{Regio\_\-compile\_\-time}] The unix time stamp when the design has been compiled.
+ \item[\portname{Regio\_\-compile\_\-time}] The unix time stamp when the design has been compiled.
\item[\portname{Regio\_\-compile\_\-version}] A version number defining the version of code. No global definition has been made.
\item[\portname{Regio\_\-hardware\_\-version}] The type of hardware. See table \ref{HardwareInformation} for details.
\item[\portname{Regio\_\-use\_\-1wire\_\-interface}] Selects which type of 1-wire interface to use. Values are c\_\-No (no 1-wire interface), c\_\-Yes (1-wire chip is connected directly to this FPGA) or c\_\-Monitor (1-wire chip is connected to another FPGA with the 1-wire monitor output connected to this FPGA)
\item The data ports are always read (and sent on the IPU channel) in order. That means, data interface 0 is the first to be sent, afterwards 0 and so on. Data Interfaces with a length of 0 are skipped.
\item If you want to add a debug header in front of the data, you can simply specify one more data port than needed for the real data and feed the header into data interface 0. Likewise, a trailer can be added by writing to the uppermost data interface
\item If the readout is controlled by one central instance, the not needed \portname{Fee\_\-trg\_\-*} can be set to fixed values as long as at least one input is used with the correct behaviour. The unused \portname{Fee\_\-trg\_\-release\_\-in} should be kept at '1' and the corresponding \portname{Fee\_\-trg\_\-statusbits\_\-in} should be kept at all bits set to 0.
+ \item A timing trigger will always be followed by a strobe on \portname{Lvl1\_\-valid\_\-timing\_\-trg\_\-out} (in case the endpoint is not currently waiting for a LVL1 trigger belonging to a previous timing trigger and the timing trigger pulse was not too short) or a high level \portname{Lvl1\_\-invalid\_\-trg\_\-out} in case of an error. Either of these ports will be set within 100 ns after the timing trigger has been received.
+ \item \portname{Lvl1\_\-invalid\_\-trg\_\-out} will stay high until the CTS resetted the trigger state machine or the next valid trigger has been received.
+ \item \portname{Lvl1\_\-valid\_\-notiming\_\-trg\_\-out} will be high within 20 ns after a valid timing-trigger-less trigger packet has been received.
+ \item \portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out} will rise typically about 2 us after a timing trigger or about 20 ns after a timing-trigger-less trigger.
\end{itemize}
\hline\hline
7100 - 710F & Data Buffer Status & Status of the data buffers, one register for each data buffer defined \\
7110 & LVL1 Buffer Status & Status of the LVL1 header / data buffer \\
+7200 & LVL1 release status & Release-flag for each of the data channel \\
+7201 & Data Handler Debug & Debug register of the data handler \\
+7202 & IPU Handler Status & IPU handler status register (see table \ref{endpointipuhandlerstatus}\\
\hline
\end{tabularx}
\caption{Register Map of the full endpoint containing data handlers.}
\end{center}
\end{table}
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\section{Common Error and Status Bits}
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-For each transmission there are 32 bits that give a rough overview of the status of the boards and transport error information. The meaning of the upper 16 bit depends on the channel while the lower 16 bit are the same on all channels. Their meaning is given in table \ref{commonerrorbits}. From these bits, only bit 4 can be set by the user, the rest is generated inside the network.
-
-
-\begin{table}
+\begin{table}[htbp]
\begin{center}
-\begin{tabularx}{\textwidth}{|c|c|C|}
+\begin{tabularx}{\textwidth}{|c|C|}
\hline
-\textbf{Bits} & \textbf{Name} & \textbf{Description} \\
+\textbf{Bit} & \textbf{Description} \\
\hline\hline
-0 & endpoint reached & At least one endpoint has been addressed by the transfer. If not set, no endpoint with the given address exists in the network. \\
-1 & collision detected & Used in the (theoretical) case that two active endpoints send data at the same time. The initial transfer this reply belongs to has been lost. \\
-2 & word missing & There was a mismatch between an internal packet counter and the length transported in an EOB packet.\\
-3 & checksum mismatch & There was a mismatch between an internally generated checksum and one received with a EOB or TRM packet. \\
-4 & don't understand & The addressed endpoint does not know how to treat the incoming data. \\
-5 & buffer mismatch & The numbers of sent EOB and received ACK do not match. \\
-6 & answer missing & An endpoint connected to a hub did not send an answer. \\
-7 - 15 & t.b.d & Bits not yet used. Reserved. \\
+3 - 0 & State bits. 0: IDLE, 1: WaitForLength, 2: GotLength, 3: SendDHDR, 4: ReadData, 5: EndReadout\\
+11 - 4 & Reserved\\
+12 & Error flag - event not found\\
+13 & Error flag - event has missing data\\
+14 & Error flag - synchronisation \\
+15 & Error flag - endpoint not configured\\
+31 - 16 & Reserved\\
\hline
\end{tabularx}
-\caption{Common Error- and Status information contained in the network termination packet on all channels}
-\label{commonerrorbits}
+\caption{Definition of bits in register 0x7202}
+\label{endpointipuhandlerstatus}
\end{center}
\end{table}
\subsection{The IPU User Interface}
The ports on the IPU interface are described in the following list. An exemplary timing diagram can be found in figure \ref{fig:ipudatauserinterface}:
\begin{description}
- \item[IPU\_NUMBER\_OUT] (16 bit) Number of the requested event. Is valid while \portname{IPU\_START\_READOUT} is high.
- \item[IPU\_READOUT\_TYPE\_OUT] (4 bit) Reserved bits to select how data should be handled, i.e. LVL2 trigger decision. Is valid while \portname{IPU\_START\_READOUT} is high.
- \item[IPU\_INFORMATION\_OUT] (8 bit) Additional reserved bits to transport detailed configuration for this readout. Bit 3 -- 0 are used to select one Eventbuilder from a table of up to 16 MAC/IP/Port combinations in SubEventBuilders. Is valid while \portname{IPU\_START\_READOUT} is high.
- \item[IPU\_START\_READOUT\_OUT] The rising edge shows that a readout request has been received. While signal is high \portname{IPU\_NUMBER}, \portname{IPU\_TYPE} and \portname{IPU\_INFORMATION} are valid. The falling edge comes after the user set \portname{IPU\_\-READOUT\_\-FINSISHED} and the endpoint finished sending data.
- \item[IPU\_DATA\_IN] (32 bit) The port on which the application sends data to the network / event builder.
- \item[IPU\_DATAREADY\_IN] Shows that data on \portname{IPU\_DATA} is valid
- \item[IPU\_READ\_OUT] High when the IPU interface is able to read data on \portname{IPU\_DATA}. Data is actually read when \portname{IPU\_DATAREADY} and \portname{IPU\_READ} are high at the same time.
- \item[IPU\_READOUT\_FINISHED\_IN] Set by the user for one clock cycle after the last data word has been read by the ipu interface.
- \item[IPU\_LENGTH\_IN] (16 bit) Length of data, counted in 32 bit words. Has to be valid from the first rising edge of \portname{IPU\_DATAREADY} until one clock cycle after \portname{IPU\_READ\_OUT} is set as well.
- \item[IPU\_ERROR\_PATTERN\_IN] (32 bit) Status and error information bits. Has to be valid while \portname{IPU\_READOUT\_FINISHED} is high.
+ \item[IPU\_\-NUMBER\_\-OUT] (16 bit) Number of the requested event. Is valid while \portname{Ipu\_\-start\_\-readout} is high.
+ \item[IPU\_\-READOUT\_\-TYPE\_\-OUT] (4 bit) Reserved bits to select how data should be handled, i.e. LVL2 trigger decision. Is valid while \portname{Ipu\_\-start\_\-readout} is high.
+ \item[IPU\_\-INFORMATION\_\-OUT] (8 bit) Additional reserved bits to transport detailed configuration for this readout. Bit 3 -- 0 are used to select one Eventbuilder from a table of up to 16 MAC/IP/Port combinations in SubEventBuilders. Is valid while \portname{Ipu\_\-start\_\-readout} is high.
+ \item[IPU\_\-START\_\-READOUT\_\-OUT] The rising edge shows that a readout request has been received. While signal is high \portname{Ipu\_\-number}, \portname{Ipu\_\-type} and \portname{Ipu\_\-information} are valid. The falling edge comes after the user set \portname{Ipu\_\-\-readout\_\-\-finsished} and the endpoint finished sending data.
+ \item[IPU\_\-DATA\_\-IN] (32 bit) The port on which the application sends data to the network / event builder.
+ \item[IPU\_\-DATAREADY\_\-IN] Shows that data on \portname{Ipu\_\-data} is valid
+ \item[IPU\_\-READ\_\-OUT] High when the IPU interface is able to read data on \portname{Ipu\_\-data}. Data is actually read when \portname{IPU\_\-DATAREADY} and \portname{Ipu\_\-read} are high at the same time.
+ \item[IPU\_\-READOUT\_\-FINISHED\_\-IN] Set by the user for one clock cycle after the last data word has been read by the ipu interface.
+ \item[IPU\_\-LENGTH\_\-IN] (16 bit) Length of data, counted in 32 bit words. Has to be valid from the first rising edge of \portname{IPU\_\-DATAREADY} until one clock cycle after \portname{Ipu\_\-read\_\-out} is set as well.
+ \item[IPU\_\-ERROR\_\-PATTERN\_\-IN] (32 bit) Status and error information bits. Has to be valid while \portname{IPU\_\-READOUT\_\-FINISHED} is high.
\end{description}
\begin{figure}
\centering
\includegraphics[width=0.9\textheight, angle= 90]{triggerinterface.png}
- \caption[Timing Diagram: LVL1 Trigger Interface]{LVL1 Trigger Interface timing}
+ \caption[Timing Diagram: LVL1 Trigger Interface]{LVL1 Trigger Interface timing. Port TrgReceived is now named TrgDataValid.}
\label{fig:triggerinterface}
\end{figure}
\begin{description}
- \item [\portname{Lvl1\_valid\_timing\_trg\_out}] A timing trigger has been received and the internal state machine marked it as valid. Typically set 2 to 5 clock cycles after \portname{trg\_timing\_trg\_received\_in} was high.
- \item [\portname{Lvl1\_valid\_notiming\_trg\_out}] A valid timing-trigger-less LVL1 trigger has been received. Typically high 1 to 2 clock cycles after the rising edge of \portname{Lvl1\_trg\_data\_valid\_out}.
- \item [\portname{Lvl1\_invalid\_trg\_out}] A trigger (either timing trigger or LVL1 trigger) has been received which has been marked invalid by the internal state machine. E.g. to timing triggers without a LVL1 trigger or a LVL1 trigger without preceeding timing trigger has been detected.
- \item [\portname{Lvl1\_trg\_type\_out}] The trigger type, similar to the old system.
- \item [\portname{Lvl1\_trg\_data\_valid\_out}] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_Trg\_Release}. While high, \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-mation} are valid.
- \item [\portname{Lvl1\_trg\_number\_out}] (16 bit) Trigger number.
- \item [\portname{Lvl1\_trg\_code\_out}] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream.
- \item [\portname{Lvl1\_trg\_information\_out}] (24 bit) Additional information about trigger as explained in the corresponding section.
- \item [\portname{Lvl1\_error\_pattern\_in}] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-Trg\_\-Release} is high.
- \item [\portname{Lvl1\_trg\_release\_in}] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release'').
- \item [\portname{Lvl1\_int\_trg\_number\_out}] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-Trg\_\-Received} goes down.
- \item [\portname{trg\_timing\_trg\_received\_in}] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_Int\_Trg\_Number\_Out}.
+ \item [\portname{Lvl1\_\-valid\_\-timing\_\-trg\_\-out}] A timing trigger has been received and the internal state machine marked it as valid. Typically set 2 to 5 clock cycles after \portname{trg\_\-timing\_\-trg\_\-received\_\-in} was high.
+ \item [\portname{Lvl1\_\-valid\_\-notiming\_\-trg\_\-out}] A valid timing-trigger-less LVL1 trigger has been received. Typically high 1 to 2 clock cycles after the rising edge of \portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}.
+ \item [\portname{Lvl1\_\-invalid\_\-trg\_\-out}] A trigger (either timing trigger or LVL1 trigger) has been received which has been marked invalid by the internal state machine. E.g. to timing triggers without a LVL1 trigger or a LVL1 trigger without preceeding timing trigger has been detected.
+ \item [\portname{Lvl1\_\-trg\_\-type\_\-out}] The trigger type, similar to the old system.
+ \item [\portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_\-Trg\_\-Release}. While high, all trigger information ports, namely \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_\-Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-ma\-tion} are valid.
+ \item [\portname{Lvl1\_\-trg\_\-number\_\-out}] (16 bit) Trigger number.
+ \item [\portname{Lvl1\_\-trg\_\-code\_\-out}] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream.
+ \item [\portname{Lvl1\_\-trg\_\-information\_\-out}] (24 bit) Additional information about trigger as explained in the corresponding section.
+ \item [\portname{Lvl1\_\-error\_\-pattern\_\-in}] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-\-Trg\_\-\-Release} is high.
+ \item [\portname{Lvl1\_\-trg\_\-release\_\-in}] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release'').
+ \item [\portname{Lvl1\_\-int\_\-trg\_\-number\_\-out}] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-\-Trg\_\-\-Received} goes down.
+ \item [\portname{trg\_\-timing\_\-trg\_\-received\_\-in}] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_\-Int\_\-Trg\_\-Number\_\-Out}.
\end{description}
\subsection{Status and Error Bits}
1 - 6 & t.b.d. & Not yet defined \\
7 & no timing trigger & Marks a LVL1 trigger which was not preceded by a timing trigger (e.g. calibration) \\
8 - 10 & RICH & RICH data configuration bits \\
-11 - 13 & Shower & 11: update pedestals, 12: calibrate even (0) or odd (1) channels, 13: tbd\\
+11 - 13 & Shower & 11: tbd, 12: tbd, 13: tbd\\
14 - 16 & MDC & 14: data format select (0: debug, 1: compressed (2 hits in 1 word))\\
17 - 23 & t.b.d. & Not yet defined \\
\hline
\clearpage
-\part{Endpoint and Channels}
+\part{Endpoints}
\section{The Endpoint}
\input{endpoint}
\clearpage
+\part{The Channels}
+\section{Common Features}
+ \input{commonfeatures}
+
\section{Channel 0: LVL1 Trigger}
\input{lvl1trigger}
\section{Network Hubs}
\input{hubs}
+\clearpage
+\section{Gigabit Ethernet}
+ \input{gbe}
+
\clearpage
\part{Software}
\end{table}
\subsubsection{MDC Optical Endpoint Voltage Monitoring}
-
+The ADC monitoring most voltages on each OEP can be accessed using register addresses 0x8000 to 0x803F. The memory map is given in table \ref{MDCOEPADCMemoryMap}, the voltages connected in table \ref{MDCOEPADCChannels}.
\begin{table}[hb]
\begin{center}
From the hardware point of view, the bits in the data word can be renamed to make their relationship to the hardware on the Shower AddOn board clearer. This is shown in table \ref{showerdatahardware}.
-For most pedestal triggers there is no ADC data sent to the Eventbuilders. Here, either an empty event or an event containing one or more status information words are sent. Only when the real pedestal value is calculated (e.g. after taking 64 pedestal values) these values are sent inside the event data. This is triggered by the CTS which also controls the time when the pedestal calculation is being done.
\begin{table}
\begin{center}
\hline
\textbf{Address} & \textbf{Name} & \textbf{Description} \\
\hline\hline
-A000 - ABFF & Thresh./Ped. Mem.& Memory for pedestal and threshold values, see table \ref{ShowerADCMemory} \\
+A000 - A5FF & Thresh./Ped. Mem.& Memory for pedestal and threshold values, see table \ref{ShowerADCMemory} \\
D000 & SPI Status Reg. & see section SPI Flash \\
D001 & SPI Control Reg. & see section SPI Flash \\
D100 - D13F & SPI Data Mem. & see section SPI Flash \\
\hline\hline
4 - 0 & Column & Column of detector \\
7 - 5 & Channel & ADC Channel \\
-8 & Ped/Thresh & 1: pedestals, 0: thresholds \\
-11 - 9 & ADC & ADC Number \\
+10 - 8 & ADC & ADC Number \\
\hline
\end{tabularx}
-\caption{Memory map for ADC pedestals and thresholds on Shower AddOn2}
+\caption{Memory map for ADC pedestals on Shower AddOn2. Bit 10 to 5 address one of 48 memory blocks, each having a depth of 32, addressed by bits 4 to 0.}
\label{ShowerADCMemory}
\end{center}
\end{table}
-Data in memory for ADC pedestals is 16 bit wide and contains the current value of the pedestal adder, i.e. its value depends on the time when it is read relative to the number of pedestal triggers already sent. This memory is read-only from slow control and will be written by the automatic pedestal logic only.
+Data in memory for ADC pedestals is 16 bit wide and contains the current value of the pedestals. During a pedestal trigger, its value is not constant since it is used to add up the 64 measurements for each frontend pad. At all other times, the value stored in the memory is the sum of all 64 pedestal measurements. Thus, the real pedestal value can be found in bits 15 to 6. When the trigger logic is idle, this memory can be read and written from slow control, otherwise access is limited to the trigger logic itself.
-The threshold memory contains 10 bit data for each pad in the frontends. To be able to switch off / override automatic pedestal calculation, this memory is read/write from slow control and read/write from the internal logic. An arbiter controls the write access, i.e. writing from slow control is only possible while the LVL1 busy signal is low. According to the specification, the logic will respond with a ``no more data'' signal on slow control, while LVL1 busy is high.
\paragraph{Onewire}
-The temperature sensor on each board is connected to the following ports. In case no temperature sensor is connected directly, the generic setting \genericname{Regio\_Use\_1wire\_Interface} has to be set accordingly.
+The temperature sensor on each board is connected to the following ports. In case no temperature sensor is connected directly, the generic setting \genericname{Regio\_\-Use\_\-1wire\_\-Interface} has to be set accordingly.
\begin{description}
\item[\portname{Regio\_Onewire\_Inout}] Direct connection to a 1-wire temperature sensor
\item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of \portname{read\_enable} and \portname{write\_enable} is high.
\item[\portname{Regio\_Read\_Enable\_Out}] Read enable strobe.
\item[\portname{Regio\_Write\_Enable\_Out}] Write enable strobe.
- \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when \portname{write\_enable} is high.
- \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when \portname{dataready\_in} is high.
+ \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when \portname{write\_\-enable} is high.
+ \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when \portname{dataready\_\-in} is high.
\item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May only be used after a strobe on \portname{read\_enable}.
\item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data to read from this address. After a write strobe: User is not able to handle more data on this address now.
\item[\portname{Regio\_Write\_Ack\_In}] User signal. Acknowledge after a strobe on \portname{write\_enable} and writing was successful.
\paragraph*{\$write timing trigger \$value} optional: \verb|$addr| \\
Sends a fake timing trigger using the slow control channel and the upper 16bit of control register 0 in all endpoints. \verb|$value| is the type of timing trigger in the range 0 to 15.
-
+\paragraph*{\$read endpoint data buffer status \\ \$read endp dat buf stat} optional: \verb|$addr|, \verb|raw| \\
+Reads the status of the data handler buffers of endpoint\_hades\_full\_handler. The decoded data is shown in table format with marks for each set bit according to table \ref{databufferdaqop}.
+
+\begin{table}[htbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|C|}
+\hline
+\textbf{Column} & \textbf{Description} \\
+\hline\hline
+Board & The network address of the board. \\
+Level & The fill level of the buffer - a 5 digit decimal number counting 32bit words inside the data buffer. The maximum value depends on the settings of the buffer. \\
+Buf & The number of the data buffer in case there is more than one data buffer specified. \\
+EMP & Empty flag of the buffer. \\
+AFL & Almost full flag of the buffer. The threshold has been set by generics in the VHDL code. \\
+FUL & Full flag of the data buffer. If this flag is set, an error occured due to a wrong buffer handling or wrong buffer settings. \\
+WRE & Write enable strobe to the buffer. \\
+IDL & Buffer handler state machine is idle, waiting for next trigger. \\
+BSY & Buffer handler state machine is waiting for and / or writing data from the FEE to the data buffer \\
+CLS & Buffer handler is waiting for busy release. The FEE already finished writing data to the buffer but LVL1 is still busy \\
+LEM & Length buffer is empty. This must always be the same as EMP of the LVL1 buffer. \\
+LFL & Length buffer is almost full. This must always be the same as AFL of the LVL1 buffer. \\
+LWR & Length buffer write enable strobe. This must always be the same as AFL of the LVL1 buffer. \\
+\hline
+\end{tabularx}
+\caption{Definition of columns in DaqOp output for the status register of data handler buffers.}
+\label{databufferdaqop}
+\end{center}
+\end{table}
+
+\paragraph*{\$read endpoint lvl1 buffer status \\ \$read endp lvl1 buf stat} optional: \verb|$addr|, \verb|raw| \\
+Reads the status of the data handler LVL1 buffers of endpoint\_hades\_full\_handler. The decoded data is shown similarly to the output for the data buffer status registers according to table \ref{databufferdaqop}. Here, not all columns are shown, i.e. there is no buffer number and no flags regarding a length buffer (which does not exist here).
\subsection{MDC}
jspc29 / daqdocu.git / commitdiff