bugs correction

diff --git a/cts_beam_structure.vhd b/cts_beam_structure.vhd
index 517ec25b4c2be3aecdafbb8625d4c999c5b645a5..d69336fec4e581d9880012c268cba21cca86d912 100644 (file)
--- a/cts_beam_structure.vhd
+++ b/cts_beam_structure.vhd
@@ -99,7 +99,7 @@ architecture cts_beam_structure of cts_beam_structure is
   signal structure_data_out_fsm, structure_data_out_i : std_logic_vector(31 downto 0);
   signal structure_finished : std_logic;
   signal special_data_rst, special_data_rst_fsm, special_data_up, special_data_up_fsm : std_logic;
-  signal special_data_cntr : std_logic_vector(12 downto 0);
+  signal special_data_cntr : std_logic_vector(13 downto 0);
   signal individual_cntrs_reset : std_logic;
 
   signal fifo_cntr : std_logic_vector(4 downto 0);
@@ -159,7 +159,7 @@ begin
       end if;
     end if;
   end process RESET_LENGTH_PROC;
-  
+
   THE_BEAM_INHIBIT_CNTR: up_down_counter  
     generic map (
         NUMBER_OF_BITS => 32)
@@ -274,7 +274,7 @@ begin
     if rising_edge(TRIGGER_CLK) then
       if RESET = '1' or start_sample_counter =  START_SAMPLE_NUMBER or reset_length = '1' then
         enable_start_sampling <= '0';
-      elsif start_delay_cntr = START_TIME_OFFSET_IN and structure_finished = '0' then
+      elsif start_delay_cntr = START_TIME_OFFSET_IN and structure_finished = '0' and readout_active = '0' then
         enable_start_sampling <= '1';
       end if;
     end if;
@@ -369,7 +369,7 @@ begin
 
   COUNTER_FOR_SPECIAL_DATA: up_down_counter
     generic map (
-        NUMBER_OF_BITS => 13)
+        NUMBER_OF_BITS => 14)
     port map (
         CLK       => LOCAL_CLK,
         RESET     => special_data_rst,
@@ -384,7 +384,7 @@ begin
         special_data_rst <= '1';
         fifo_cntr <= (others => '0');
         STRUCTURE_DATA_OUT <= start_q(0)(31 downto 0);
-      elsif special_data_cntr = START_SAMPLE_NUMBER then
+      elsif (special_data_cntr = START_SAMPLE_NUMBER - 1) and READ_STRUCTURE_IN = '1' then
         special_data_rst <= '1';
         fifo_cntr <= fifo_cntr + 1;
         STRUCTURE_DATA_OUT <= start_q(conv_integer(fifo_cntr+1))(31 downto 0);
@@ -401,7 +401,7 @@ begin
     if rising_edge(LOCAL_CLK) then
       if RESET = '1' or fifo_cntr  = HOW_MANY_HISTOGRAMS then
         readout_active <= '0';
-      elsif READ_STRUCTURE_START_IN = '1' then
+      elsif READ_STRUCTURE_START_IN = '1' and structure_finished = '1' then
         readout_active <= '1';
       else
         readout_active <= readout_active;
@@ -418,7 +418,7 @@ begin
       elsif  fifo_cntr  = HOW_MANY_HISTOGRAMS then
         special_data_up <= '0';
         read_structure_finished_out_i <= '1';
-      elsif READ_STRUCTURE_START_IN = '1' and structure_finished = '1' then
+      elsif readout_active = '1' then
         special_data_up <= READ_STRUCTURE_IN;
         read_structure_finished_out_i <= '0';
       elsif READ_STRUCTURE_START_IN = '1' and structure_finished = '0' then        
@@ -431,6 +431,8 @@ begin
     end if;
   end process SPECIAL_DATA_UP_CNTR_PROC;
   
+  READ_STRUCTURE_FINISHED_OUT <= read_structure_finished_out_i;
+    
   SELECT_FIFO_TO_READ: for i in 0 to 25 generate
     SPECIAL_DATA_UP_CNTR_PROC : process (LOCAL_CLK, RESET)
     begin

diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd
index 8340d1984ca00783294e9dc27295ca5e96a38927..d830b9bca6509e7dd5600dff0a77a37dd5b05833 100644 (file)
--- a/cts_fpga1.vhd
+++ b/cts_fpga1.vhd
@@ -20,7 +20,7 @@ entity cts_fpga1 is
     REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FF01";
     REGIO_ENDPOINT_ID  : std_logic_vector(15 downto 0) := x"0001";
     CTS_NUMBER_IPU_DATA: integer range 0 to 9 :=2;
-    RW_REGISTERS_NUMBER  : integer range 0 to 49  := 36;
+    RW_REGISTERS_NUMBER  : integer range 0 to 49  := 38;
     R_REGISTERS_NUMBER   : integer range 0 to 105  := 103;
     TRIGGER_INPUTS_NUMBER : integer range 0 to 64 := 36;
     TRIGGER_OUTPUTS_NUMBER : integer range 0 to 64 := 19;

diff --git a/cts_fpga1_tb.vhd b/cts_fpga1_tb.vhd
index e0cb720c64e6a586e8c3fe977affdbea996b4d06..cc6c2a1fbebb0810d7a93ca0db33838fa4ab6f49 100644 (file)
--- a/cts_fpga1_tb.vhd
+++ b/cts_fpga1_tb.vhd
@@ -132,53 +132,54 @@ ARCHITECTURE behavior OF cts_fpga1_tb IS
   component cts_fpga1_test
     port (
       CLK_200_IN              : in    std_logic;
-      ADO_CLKOUT              : out   std_logic;
-      RESET_FPGA_1            : in    std_logic;
-      ADDON_RESET             : in    std_logic;
-      ADO_TTL                 : inout std_logic_vector(46 downto 0);
+--      ADO_CLKOUT              : out   std_logic;
+--      RESET_FPGA_1            : in    std_logic;
+--      ADDON_RESET             : in    std_logic;
+--      ADO_TTL                 : inout std_logic_vector(46 downto 0);
       FS_PE                   : inout std_logic_vector(9 downto 8);
 --      FFC                     : inout std_logic_vector(22 downto 0);
-      TRIG_IN                 : out   std_logic_vector(63 downto 0);
+      TRIG_OUT                 : out   std_logic_vector(31 downto 0);
       LVDS_OUT                : out   std_logic_vector(14 downto 0);
       LVDS_IN                 : in    std_logic;
-      PECL_OUT                : out   std_logic_vector(2 downto 0);
-      RICH_CLK_OUT            : out   std_logic;
-      RICH_RESERVED_OUT       : out   std_logic;
-      RICH_TIMING_OUT         : out   std_logic_vector(0 downto 0);
-      RICH_TRIGGER_OUT        : out   std_logic;
-      SPI_CLK_OUT             : out   std_logic;
-      SPI_CS_OUT              : out   std_logic;
-      SPI_SI_OUT              : out   std_logic;
-      SPI_SO_IN               : in    std_logic;
-      PROGRAMN_OUT            : out   std_logic;
-      LED_GREEN               : out   std_logic;
-      LED_ORANGE              : out   std_logic;
-      LED_RED                 : out   std_logic;
-      LED_YELLOW              : out   std_logic;
-      TRB2_OK_LED             : out   std_logic;
-      TRB2_RX_LED             : out   std_logic;
-      TRB2_TX_LED             : out   std_logic;
-      TRB3_OK_LED             : out   std_logic;
-      TRB3_RX_LED             : out   std_logic;
-      TRB3_TX_LED             : out   std_logic;
-      TRB2_LOS                : out   std_logic;
-      TRB2_MOD                : inout std_logic_vector(2 downto 0);
-      TRB2_TX_DIS             : out   std_logic;
-      TRB3_LOS                : out   std_logic;
-      TRB3_MOD                : inout std_logic_vector(2 downto 0);
-      TRB3_TX_DIS             : out   std_logic;
-      FAKE_SERDES_RXD_P_IN    : in    std_logic;
-      FAKE_SERDES_RXD_N_IN    : in    std_logic;
-      FAKE_SERDES_TXD_P_OUT   : out   std_logic;
-      FAKE_SERDES_TXD_N_OUT   : out   std_logic;
-      FAKE_SERDES_REFCLK_P_IN : in    std_logic;
-      FAKE_SERDES_REFCLK_N_IN : in    std_logic;
-      ONEWIRE_MONITOR_IN      : in    std_logic;
-      RS1                     : out   std_logic_vector(3 downto 0);
-      RS2                     : out   std_logic_vector(3 downto 0);
-      DIS1                    : out   std_logic_vector(2 downto 0);
-      DIS2                    : out   std_logic_vector(2 downto 0);
-      TEST_LINE               : out   std_logic_vector(31 downto 0));
+--      PECL_OUT                : out   std_logic_vector(2 downto 0);
+--      RICH_CLK_OUT            : out   std_logic;
+--      RICH_RESERVED_OUT       : out   std_logic;
+--      RICH_TIMING_OUT         : out   std_logic_vector(0 downto 0);
+--      RICH_TRIGGER_OUT        : out   std_logic;
+--      SPI_CLK_OUT             : out   std_logic;
+--      SPI_CS_OUT              : out   std_logic;
+--      SPI_SI_OUT              : out   std_logic;
+--      SPI_SO_IN               : in    std_logic;
+      PROGRAMN_OUT            : out   std_logic
+--      LED_GREEN               : out   std_logic;
+--      LED_ORANGE              : out   std_logic;
+--      LED_RED                 : out   std_logic;
+--      LED_YELLOW              : out   std_logic;
+--      TRB2_OK_LED             : out   std_logic;
+--      TRB2_RX_LED             : out   std_logic;
+--      TRB2_TX_LED             : out   std_logic;
+--      TRB3_OK_LED             : out   std_logic;
+--      TRB3_RX_LED             : out   std_logic;
+--      TRB3_TX_LED             : out   std_logic;
+--      TRB2_LOS                : out   std_logic;
+--      TRB2_MOD                : inout std_logic_vector(2 downto 0);
+--      TRB2_TX_DIS             : out   std_logic;
+--      TRB3_LOS                : out   std_logic;
+--      TRB3_MOD                : inout std_logic_vector(2 downto 0);
+--      TRB3_TX_DIS             : out   std_logic;
+--      FAKE_SERDES_RXD_P_IN    : in    std_logic;
+--      FAKE_SERDES_RXD_N_IN    : in    std_logic;
+--      FAKE_SERDES_TXD_P_OUT   : out   std_logic;
+--      FAKE_SERDES_TXD_N_OUT   : out   std_logic;
+--      FAKE_SERDES_REFCLK_P_IN : in    std_logic;
+--      FAKE_SERDES_REFCLK_N_IN : in    std_logic;
+--      ONEWIRE_MONITOR_IN      : in    std_logic;
+--      RS1                     : out   std_logic_vector(3 downto 0);
+--      RS2                     : out   std_logic_vector(3 downto 0);
+--      DIS1                    : out   std_logic_vector(2 downto 0);
+--      DIS2                    : out   std_logic_vector(2 downto 0);
+--      TEST_LINE               : out   std_logic_vector(31 downto 0)
+      );
   end component;
 
   
@@ -320,7 +321,7 @@ ARCHITECTURE behavior OF cts_fpga1_tb IS
   signal TEST_ADO_TTL                 : std_logic_vector(46 downto 0);
   signal TEST_FS_PE                   : std_logic_vector(9 downto 8);
 --  signal TEST_FFC                     : std_logic_vector(22 downto 0);
-  signal TEST_TRIG_IN                 : std_logic_vector(63 downto 0);
+  signal TEST_TRIG_IN                 : std_logic_vector(31 downto 0);
   signal TEST_LVDS_OUT                : std_logic_vector(14 downto 0);
   signal TEST_LVDS_IN                 : std_logic;
   signal TEST_PECL_OUT                : std_logic_vector(2 downto 0);
@@ -487,53 +488,54 @@ BEGIN
   THE_CTS_FPGA1_TEST: cts_fpga1_test
     port map (
       CLK_200_IN              => TEST_CLK_200_IN,
-      ADO_CLKOUT              => TEST_ADO_CLKOUT,
-      RESET_FPGA_1            => TEST_RESET_FPGA_1,
-      ADDON_RESET             => TEST_ADDON_RESET,
-      ADO_TTL                 => TEST_ADO_TTL,
+--      ADO_CLKOUT              => TEST_ADO_CLKOUT,
+--      RESET_FPGA_1            => TEST_RESET_FPGA_1,
+--      ADDON_RESET             => TEST_ADDON_RESET,
+--      ADO_TTL                 => TEST_ADO_TTL,
       FS_PE                   => TEST_FS_PE,
 --      FFC                     => TEST_FFC,
-      TRIG_IN                 => TEST_TRIG_IN,
+      TRIG_OUT                 => TEST_TRIG_IN,
       LVDS_OUT                => TEST_LVDS_OUT,
       LVDS_IN                 => TEST_LVDS_IN,
-      PECL_OUT                => TEST_PECL_OUT,
-      RICH_CLK_OUT            => TEST_RICH_CLK_OUT,
-      RICH_RESERVED_OUT       => TEST_RICH_RESERVED_OUT,
-      RICH_TIMING_OUT         => TEST_RICH_TIMING_OUT,
-      RICH_TRIGGER_OUT        => TEST_RICH_TRIGGER_OUT,
-      SPI_CLK_OUT             => TEST_SPI_CLK_OUT,
-      SPI_CS_OUT              => TEST_SPI_CS_OUT,
-      SPI_SI_OUT              => TEST_SPI_SI_OUT,
-      SPI_SO_IN               => TEST_SPI_SO_IN,
-      PROGRAMN_OUT            => TEST_PROGRAMN_OUT,
-      LED_GREEN               => TEST_LED_GREEN,
-      LED_ORANGE              => TEST_LED_ORANGE,
-      LED_RED                 => TEST_LED_RED,
-      LED_YELLOW              => TEST_LED_YELLOW,
-      TRB2_OK_LED             => TEST_TRB2_OK_LED,
-      TRB2_RX_LED             => TEST_TRB2_RX_LED,
-      TRB2_TX_LED             => TEST_TRB2_TX_LED,
-      TRB3_OK_LED             => TEST_TRB3_OK_LED,
-      TRB3_RX_LED             => TEST_TRB3_RX_LED,
-      TRB3_TX_LED             => TEST_TRB3_TX_LED,
-      TRB2_LOS                => TEST_TRB2_LOS,
-      TRB2_MOD                => TEST_TRB2_MOD,
-      TRB2_TX_DIS             => TEST_TRB2_TX_DIS,
-      TRB3_LOS                => TEST_TRB3_LOS,
-      TRB3_MOD                => TEST_TRB3_MOD,
-      TRB3_TX_DIS             => TEST_TRB3_TX_DIS,
-      FAKE_SERDES_RXD_P_IN    => TEST_FAKE_SERDES_RXD_P_IN,
-      FAKE_SERDES_RXD_N_IN    => TEST_FAKE_SERDES_RXD_N_IN,
-      FAKE_SERDES_TXD_P_OUT   => TEST_FAKE_SERDES_TXD_P_OUT,
-      FAKE_SERDES_TXD_N_OUT   => TEST_FAKE_SERDES_TXD_N_OUT,
-      FAKE_SERDES_REFCLK_P_IN => TEST_FAKE_SERDES_REFCLK_P_IN,
-      FAKE_SERDES_REFCLK_N_IN => TEST_FAKE_SERDES_REFCLK_N_IN,
-      ONEWIRE_MONITOR_IN      => TEST_ONEWIRE_MONITOR_IN,
-      RS1                     => TEST_RS1,
-      RS2                     => TEST_RS2,
-      DIS1                    => TEST_DIS1,
-      DIS2                    => TEST_DIS2,
-      TEST_LINE               => TEST_TEST_LINE);
+--      PECL_OUT                => TEST_PECL_OUT,
+--      RICH_CLK_OUT            => TEST_RICH_CLK_OUT,
+--      RICH_RESERVED_OUT       => TEST_RICH_RESERVED_OUT,
+--      RICH_TIMING_OUT         => TEST_RICH_TIMING_OUT,
+--      RICH_TRIGGER_OUT        => TEST_RICH_TRIGGER_OUT,
+--      SPI_CLK_OUT             => TEST_SPI_CLK_OUT,
+--      SPI_CS_OUT              => TEST_SPI_CS_OUT,
+--      SPI_SI_OUT              => TEST_SPI_SI_OUT,
+--      SPI_SO_IN               => TEST_SPI_SO_IN,
+      PROGRAMN_OUT            => TEST_PROGRAMN_OUT
+--      LED_GREEN               => TEST_LED_GREEN,
+--      LED_ORANGE              => TEST_LED_ORANGE,
+--      LED_RED                 => TEST_LED_RED,
+--      LED_YELLOW              => TEST_LED_YELLOW,
+--      TRB2_OK_LED             => TEST_TRB2_OK_LED,
+--      TRB2_RX_LED             => TEST_TRB2_RX_LED,
+--      TRB2_TX_LED             => TEST_TRB2_TX_LED,
+--      TRB3_OK_LED             => TEST_TRB3_OK_LED,
+--      TRB3_RX_LED             => TEST_TRB3_RX_LED,
+--      TRB3_TX_LED             => TEST_TRB3_TX_LED,
+--      TRB2_LOS                => TEST_TRB2_LOS,
+--      TRB2_MOD                => TEST_TRB2_MOD,
+--      TRB2_TX_DIS             => TEST_TRB2_TX_DIS,
+--      TRB3_LOS                => TEST_TRB3_LOS,
+--      TRB3_MOD                => TEST_TRB3_MOD,
+--      TRB3_TX_DIS             => TEST_TRB3_TX_DIS,
+--      FAKE_SERDES_RXD_P_IN    => TEST_FAKE_SERDES_RXD_P_IN,
+--      FAKE_SERDES_RXD_N_IN    => TEST_FAKE_SERDES_RXD_N_IN,
+--      FAKE_SERDES_TXD_P_OUT   => TEST_FAKE_SERDES_TXD_P_OUT,
+--      FAKE_SERDES_TXD_N_OUT   => TEST_FAKE_SERDES_TXD_N_OUT,
+--      FAKE_SERDES_REFCLK_P_IN => TEST_FAKE_SERDES_REFCLK_P_IN,
+--      FAKE_SERDES_REFCLK_N_IN => TEST_FAKE_SERDES_REFCLK_N_IN,
+--      ONEWIRE_MONITOR_IN      => TEST_ONEWIRE_MONITOR_IN,
+--      RS1                     => TEST_RS1,
+--      RS2                     => TEST_RS2,
+--      DIS1                    => TEST_DIS1,
+--      DIS2                    => TEST_DIS2,
+--      TEST_LINE               => TEST_TEST_LINE
+      );
 
 -------------------------------------------------------------------------------
 -- beam inhibit in
@@ -618,7 +620,8 @@ BEGIN
 --     TRIG_IN(i)  <= triggers(i mod 4);
 --   end generate SEND_DIFF_TRIGG_RCTS;
 
-  TRIG_IN <= TEST_TRIG_IN;
+  TRIG_IN(31 downto 0) <= TEST_TRIG_IN;
+   TRIG_IN(63 downto 32) <= TEST_TRIG_IN;
 --  TRIG_IN(39 downto 32) <= TEST_TRIG_IN_B(55 downto 48);
    
 --  SEND_DIFF_TRIGG_RCTS: for i in 0 to 15 generate

diff --git a/cts_fpga1_test.vhd b/cts_fpga1_test.vhd
index 0b6a0fe272e1a9c018a7c5d3ff847cef9ab49108..719209fab393617396bdf917d792f0ea87d538ac 100644 (file)
--- a/cts_fpga1_test.vhd
+++ b/cts_fpga1_test.vhd
@@ -272,7 +272,8 @@ begin
       port map (
         clock     => CLK_200_IN,
         en_clk    => '1',
-        signal_in => hit_cntr(conv_integer(rw_register_i(i/4)(((i mod 4)+1)*8-1 downto (i mod 4)*8))),
+     --   signal_in => hit_cntr(conv_integer(rw_register_i(i/4)(((i mod 4)+1)*8-1 downto (i mod 4)*8))),
+        signal_in => hit_cntr(4),
         pulse     => start_pulses(i));    
 
     start_pulses_in_array(i)(0) <= start_pulses(i);
@@ -313,7 +314,8 @@ begin
       port map (
         clock     => CLK_200_IN,
         en_clk    => '1',
-        signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))),
+   --     signal_in => hit_cntr(conv_integer(rw_register_i(25)(5 downto 0))),
+        signal_in => hit_cntr(8),
         pulse     => beam_inhibit_pulse);    
 
   BEAM_INHIBIT_SET_WIDTH: cts_fpga1_test_set_width

diff --git a/cts_fpga2_compile.pl b/cts_fpga2_compile.pl
index 34b82a42220c750652def44c132ae4d30df42f8a..986a987d52a3edeec4c0fa6b6dafc99e156b0cb3 100755 (executable)
--- a/cts_fpga2_compile.pl
+++ b/cts_fpga2_compile.pl
@@ -35,9 +35,9 @@ my $SPEEDGRADE="5";
 
 
 #create full lpf file
-system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
-system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
-
+#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+#system("cp .$TOPNAME.lpf workdir/$TOPNAME.lpf");
 #set -e
 #set -o errexit
 
@@ -107,7 +107,7 @@ execute($c);
 
 my $tpmap = $TOPNAME . "_map" ;
 
-$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/map  -hier -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
 execute($c);
 
 

diff --git a/cts_fpga2_reg_interface.vhd b/cts_fpga2_reg_interface.vhd
index 9e16bd2ba2d28515dd71bcf7b8528c430bc0618b..31c9c79bde376a67129c39881dff50bd93f3b747 100644 (file)
--- a/cts_fpga2_reg_interface.vhd
+++ b/cts_fpga2_reg_interface.vhd
@@ -82,8 +82,8 @@ architecture cts_fpga2_reg_interface of cts_fpga2_reg_interface is
   
   component cts_fpga2_reg_mem
     port (
-      WrAddress : in  std_logic_vector(12 downto 0);
-      RdAddress : in  std_logic_vector(12 downto 0);
+      WrAddress : in  std_logic_vector(13 downto 0);
+      RdAddress : in  std_logic_vector(13 downto 0);
       Data      : in  std_logic_vector(31 downto 0);
       WE        : in  std_logic;
       RdClock   : in  std_logic;
@@ -96,7 +96,7 @@ architecture cts_fpga2_reg_interface of cts_fpga2_reg_interface is
 
   signal unknown_addr,unknown_addr_pulse  : std_logic;
   signal saved_mode : std_logic;
-  signal saved_address : std_logic_vector(15 downto 0);
+  signal saved_address, mem_saved_address : std_logic_vector(15 downto 0);
   signal saved_data : std_logic_vector(31 downto 0);
   signal data_out : std_logic_vector(31 downto 0);
   signal data_out_select_int : integer range 0 to 255:=0;
@@ -106,16 +106,17 @@ architecture cts_fpga2_reg_interface of cts_fpga2_reg_interface is
   signal ack_out_synch_c : std_logic;
   signal ack_out_synch_d : std_logic;
   signal ack_out_synch_e : std_logic;
+  signal ack_out_synch_f : std_logic;
 
   signal rw_register_i : std_logic_vector(RW_REGISTERS_NUMBER*32 -1 downto 0);
 
   --registers from fpga1
   signal reg_mem_data : std_logic_vector(31 downto 0);
   signal down_data_all_cntr_up, down_data_all_rst, down_data_all_rst_a, down_data_all_rst_b, down_data_empty, down_data_full: std_logic;
-  signal down_data_all_cntr, down_data_all_cntr_sync : std_logic_vector(12 downto 0);
+  signal down_data_all_cntr, down_data_all_cntr_sync : std_logic_vector(13 downto 0);
   signal down_data_out_i : std_logic_vector(31 downto 0);
   signal cts_fpga2_reg_mem_wr_en, cts_fpga2_reg_mem_wr_en_sync : std_logic;
-  signal cts_fpga2_reg_mem_addr : std_logic_vector(12 downto 0);
+  signal cts_fpga2_reg_mem_addr : std_logic_vector(13 downto 0);
   signal reg_fifo_rst : std_logic;
   signal reg_fifo_rst_pulse : std_logic;
   
@@ -183,7 +184,7 @@ begin
 --      signal_in => unknown_addr,
 --      pulse     => unknown_addr_pulse);
   
-  REGIO_UNKNOWN_ADDR_OUT <= unknown_addr and ack_out_synch_d;  --'0'
+  REGIO_UNKNOWN_ADDR_OUT <= unknown_addr and ack_out_synch_e;  --'0'
 
   CHANGE_ADDR_TO_INT : process (CLK, RESET)
   begin
@@ -219,7 +220,7 @@ begin
       if RESET = '1' then
         rw_register_i <= (others => '0');
 --      elsif  saved_mode = '0' and ack_out_synch_d = '1' then
-      elsif saved_address(15 downto 4) = x"A0f" and saved_mode = '0' and ack_out_synch_d = '1' then
+      elsif saved_address(15 downto 4) = x"A0f" and saved_mode = '0' and ack_out_synch_e = '1' then
         rw_register_i((data_out_select_int+1)*32-1 downto data_out_select_int*32) <= saved_data;
       end if;
     end if;
@@ -236,7 +237,9 @@ begin
         ack_out_synch_c <= '0';
         ack_out_synch_d <= '0';
         ack_out_synch_e <= '0';
+        ack_out_synch_f <= '0';
       else
+        ack_out_synch_f <= ack_out_synch_e;
         ack_out_synch_e <= ack_out_synch_d;
         ack_out_synch_d <= ack_out_synch_c;
         ack_out_synch_c <= ack_out_synch_b;
@@ -246,9 +249,9 @@ begin
     end if;
   end process SET_ACK_OUT;
 
-  REGIO_NO_MORE_DATA_OUT <= ack_out_synch_e and (not unknown_addr);
-  REGIO_DATAREADY_OUT <= ack_out_synch_d and saved_mode and (not unknown_addr);
-  REGIO_WRITE_ACK_OUT <= ack_out_synch_d and (not (saved_mode)) and (not unknown_addr);
+  REGIO_NO_MORE_DATA_OUT <= ack_out_synch_f and (not unknown_addr);
+  REGIO_DATAREADY_OUT <= ack_out_synch_e and saved_mode and (not unknown_addr);
+  REGIO_WRITE_ACK_OUT <= ack_out_synch_e and (not (saved_mode)) and (not unknown_addr);
 
   -----------------------------------------------------------------------------
   -- registers from fpga1
@@ -309,7 +312,7 @@ begin
 
   DATA_DOWN_COUNTER: up_down_counter
     generic map (
-        NUMBER_OF_BITS => 13)
+        NUMBER_OF_BITS => 14)
     port map (
         CLK       => CLK,
         RESET     => down_data_all_rst_b,
@@ -328,15 +331,38 @@ begin
       else
        cts_fpga2_reg_mem_wr_en <= down_data_all_cntr_up;
        cts_fpga2_reg_mem_wr_en_sync <= cts_fpga2_reg_mem_wr_en;
-       cts_fpga2_reg_mem_addr <= down_data_all_cntr(12 downto 0);
+       cts_fpga2_reg_mem_addr <= down_data_all_cntr(13 downto 0);
       end if;
     end if;
   end process WRITE_REG_MEM_SYNC;
+
+
+  OFFSET_CHANGE_FOR_ADDRESSING : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        mem_saved_address <= (others => '0');
+      else
+        case saved_address(15 downto 12) is
+          when x"A" =>
+            mem_saved_address(15 downto 12) <= x"0";
+            mem_saved_address(11 downto 0) <= saved_address(11 downto 0);
+          when x"B" =>
+            mem_saved_address(15 downto 12) <= x"1";
+            mem_saved_address(11 downto 0) <= saved_address(11 downto 0);
+          when others =>
+            mem_saved_address(15 downto 12) <= x"0";
+            mem_saved_address(11 downto 0) <= saved_address(11 downto 0);
+        end case;
+      end if;
+    end if;
+  end process OFFSET_CHANGE_FOR_ADDRESSING;
+
   
    THE_CTS_FPGA2_REG_MEM: cts_fpga2_reg_mem
     port map (
-      WrAddress => down_data_all_cntr_sync(12 downto 0),--cts_fpga2_reg_mem_addr,
-      RdAddress => saved_address(12 downto 0),
+      WrAddress => down_data_all_cntr_sync(13 downto 0),--cts_fpga2_reg_mem_addr,
+      RdAddress => mem_saved_address(13 downto 0),
       Data      => down_data_out_i,
       WE        => cts_fpga2_reg_mem_wr_en,
       RdClock   => CLK,
@@ -437,7 +463,7 @@ begin
       
       when IDLE      =>
         rw_data_send_debug_fsm <= x"1";
-        if ack_out_synch_e = '1' and saved_address(15 downto 8) = x"A0" and saved_address(7 downto 0) < 240 and saved_address(7 downto 0) > 191 and  saved_mode = '0' then
+        if ack_out_synch_f = '1' and saved_address(15 downto 8) = x"A0" and saved_address(7 downto 0) < 240 and saved_address(7 downto 0) > 191 and  saved_mode = '0' then
           RW_DATA_SEND_NEXT <= RW_REG_PREPARE_A;
         else
           RW_DATA_SEND_NEXT <= IDLE;

diff --git a/cts_fpga2_reg_mem.vhd b/cts_fpga2_reg_mem.vhd
index 4e1c376d5056bfd9484ccae793a530a0b3beae98..fd51461c4f246d90dade2ce6a42ff44c8ec785c8 100644 (file)
--- a/cts_fpga2_reg_mem.vhd
+++ b/cts_fpga2_reg_mem.vhd
@@ -2,7 +2,7 @@
 -- Module  Version: 6.1
 --/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 16384 -outdata REGISTERED -resetmode SYNC -cascade -1 -e 
 
--- Mon Jan  2 14:17:10 2012
+-- Wed Jan  4 13:41:21 2012
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -11,7 +11,7 @@ library ecp2m;
 use ecp2m.components.all;
 -- synopsys translate_on
 
-entity cts_fpga2_reg_mem_a is
+entity cts_fpga2_reg_mem is
     port (
         WrAddress: in  std_logic_vector(13 downto 0); 
         RdAddress: in  std_logic_vector(13 downto 0); 
@@ -23,9 +23,9 @@ entity cts_fpga2_reg_mem_a is
         WrClock: in  std_logic; 
         WrClockEn: in  std_logic; 
         Q: out  std_logic_vector(31 downto 0));
-end cts_fpga2_reg_mem_a;
+end cts_fpga2_reg_mem;
 
-architecture Structure of cts_fpga2_reg_mem_a is
+architecture Structure of cts_fpga2_reg_mem is
 
     -- internal signal declarations
     signal scuba_vhi: std_logic;
@@ -116,397 +116,397 @@ architecture Structure of cts_fpga2_reg_mem_a is
     attribute REGMODE_A : string; 
     attribute DATA_WIDTH_B : string; 
     attribute DATA_WIDTH_A : string; 
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_0_31 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_0_31 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_0_31 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_0_31 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_0_31 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_0_31 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_1_30 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_1_30 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_1_30 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_1_30 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_1_30 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_1_30 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_2_29 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_2_29 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_2_29 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_2_29 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_2_29 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_2_29 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_3_28 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_3_28 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_3_28 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_3_28 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_3_28 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_3_28 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_4_27 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_4_27 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_4_27 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_4_27 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_4_27 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_4_27 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_5_26 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_5_26 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_5_26 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_5_26 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_5_26 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_5_26 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_6_25 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_6_25 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_6_25 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_6_25 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_6_25 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_6_25 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_7_24 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_7_24 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_7_24 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_7_24 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_7_24 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_7_24 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_8_23 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_8_23 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_8_23 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_8_23 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_8_23 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_8_23 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_9_22 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_9_22 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_9_22 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_9_22 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_9_22 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_9_22 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_10_21 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_10_21 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_10_21 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_10_21 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_10_21 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_10_21 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_11_20 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_11_20 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_11_20 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_11_20 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_11_20 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_11_20 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_12_19 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_12_19 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_12_19 : label is "DISABLED";
-    attribute RESETMODE of cts_fpga2_reg_mem_a_0_12_19 : label is "SYNC";
-    attribute REGMODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "OUTREG";
-    attribute REGMODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "OUTREG";
-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_12_19 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_12_19 : label is "1";
-    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_13_18 : label is "cts_fpga2_reg_mem_a.lpc";
-    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_13_18 : label is "";
-    attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_13_18 : label is "0b000";
-    attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_13_18 : label is "0b000";
-    attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_13_18 : label is "NORMAL";
-    attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_13_18 : label is "NORMAL";
-    attribute GSR of cts_fpga2_reg_mem_a_0_13_18 : label is "DISABLED";
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-    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_31_0 : label is "1";
-    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_31_0 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_0_31 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_0_31 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_0_31 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_0_31 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_0_31 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_0_31 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_0_31 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_0_31 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_0_31 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_0_31 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_0_31 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_0_31 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_1_30 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_1_30 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_1_30 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_1_30 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_1_30 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_1_30 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_1_30 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_1_30 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_1_30 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_1_30 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_1_30 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_1_30 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_2_29 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_2_29 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_2_29 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_2_29 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_2_29 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_2_29 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_2_29 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_2_29 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_2_29 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_2_29 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_2_29 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_2_29 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_3_28 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_3_28 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_3_28 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_3_28 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_3_28 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_3_28 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_3_28 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_3_28 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_3_28 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_3_28 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_3_28 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_3_28 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_4_27 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_4_27 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_4_27 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_4_27 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_4_27 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_4_27 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_4_27 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_4_27 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_4_27 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_4_27 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_4_27 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_4_27 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_5_26 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_5_26 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_5_26 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_5_26 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_5_26 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_5_26 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_5_26 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_5_26 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_5_26 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_5_26 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_5_26 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_5_26 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_6_25 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_6_25 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_6_25 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_6_25 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_6_25 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_6_25 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_6_25 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_6_25 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_6_25 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_6_25 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_6_25 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_6_25 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_7_24 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_7_24 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_7_24 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_7_24 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_7_24 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_7_24 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_7_24 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_7_24 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_7_24 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_7_24 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_7_24 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_7_24 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_8_23 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_8_23 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_8_23 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_8_23 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_8_23 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_8_23 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_8_23 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_8_23 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_8_23 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_8_23 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_8_23 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_8_23 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_9_22 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_9_22 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_9_22 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_9_22 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_9_22 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_9_22 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_9_22 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_9_22 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_9_22 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_9_22 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_9_22 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_9_22 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_10_21 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_10_21 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_10_21 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_10_21 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_10_21 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_10_21 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_10_21 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_10_21 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_10_21 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_10_21 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_10_21 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_10_21 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_11_20 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_11_20 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_11_20 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_11_20 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_11_20 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_11_20 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_11_20 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_11_20 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_11_20 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_11_20 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_11_20 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_11_20 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_12_19 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_12_19 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_12_19 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_12_19 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_12_19 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_12_19 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_12_19 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_12_19 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_12_19 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_12_19 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_12_19 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_12_19 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_13_18 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_13_18 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_13_18 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_13_18 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_13_18 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_13_18 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_13_18 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_13_18 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_13_18 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_13_18 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_13_18 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_13_18 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_14_17 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_14_17 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_14_17 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_14_17 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_14_17 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_14_17 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_14_17 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_14_17 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_14_17 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_14_17 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_14_17 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_14_17 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_15_16 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_15_16 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_15_16 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_15_16 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_15_16 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_15_16 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_15_16 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_15_16 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_15_16 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_15_16 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_15_16 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_15_16 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_16_15 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_16_15 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_16_15 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_16_15 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_16_15 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_16_15 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_16_15 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_16_15 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_16_15 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_16_15 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_16_15 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_16_15 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_17_14 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_17_14 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_17_14 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_17_14 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_17_14 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_17_14 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_17_14 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_17_14 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_17_14 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_17_14 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_17_14 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_17_14 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_18_13 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_18_13 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_18_13 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_18_13 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_18_13 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_18_13 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_18_13 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_18_13 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_18_13 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_18_13 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_18_13 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_18_13 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_19_12 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_19_12 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_19_12 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_19_12 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_19_12 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_19_12 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_19_12 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_19_12 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_19_12 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_19_12 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_19_12 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_19_12 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_20_11 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_20_11 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_20_11 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_20_11 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_20_11 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_20_11 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_20_11 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_20_11 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_20_11 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_20_11 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_20_11 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_20_11 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_21_10 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_21_10 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_21_10 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_21_10 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_21_10 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_21_10 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_21_10 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_21_10 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_21_10 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_21_10 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_21_10 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_21_10 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_22_9 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_22_9 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_22_9 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_22_9 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_22_9 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_22_9 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_22_9 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_22_9 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_22_9 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_22_9 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_22_9 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_22_9 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_23_8 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_23_8 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_23_8 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_23_8 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_23_8 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_23_8 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_23_8 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_23_8 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_23_8 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_23_8 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_23_8 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_23_8 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_24_7 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_24_7 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_24_7 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_24_7 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_24_7 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_24_7 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_24_7 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_24_7 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_24_7 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_24_7 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_24_7 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_24_7 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_25_6 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_25_6 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_25_6 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_25_6 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_25_6 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_25_6 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_25_6 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_25_6 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_25_6 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_25_6 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_25_6 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_25_6 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_26_5 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_26_5 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_26_5 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_26_5 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_26_5 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_26_5 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_26_5 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_26_5 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_26_5 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_26_5 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_26_5 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_26_5 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_27_4 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_27_4 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_27_4 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_27_4 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_27_4 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_27_4 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_27_4 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_27_4 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_27_4 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_27_4 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_27_4 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_27_4 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_28_3 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_28_3 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_28_3 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_28_3 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_28_3 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_28_3 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_28_3 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_28_3 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_28_3 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_28_3 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_28_3 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_28_3 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_29_2 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_29_2 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_29_2 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_29_2 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_29_2 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_29_2 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_29_2 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_29_2 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_29_2 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_29_2 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_29_2 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_29_2 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_30_1 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_30_1 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_30_1 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_30_1 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_30_1 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_30_1 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_30_1 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_30_1 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_30_1 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_30_1 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_30_1 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_30_1 : label is "1";
+    attribute MEM_LPC_FILE of cts_fpga2_reg_mem_0_31_0 : label is "cts_fpga2_reg_mem.lpc";
+    attribute MEM_INIT_FILE of cts_fpga2_reg_mem_0_31_0 : label is "";
+    attribute CSDECODE_B of cts_fpga2_reg_mem_0_31_0 : label is "0b000";
+    attribute CSDECODE_A of cts_fpga2_reg_mem_0_31_0 : label is "0b000";
+    attribute WRITEMODE_B of cts_fpga2_reg_mem_0_31_0 : label is "NORMAL";
+    attribute WRITEMODE_A of cts_fpga2_reg_mem_0_31_0 : label is "NORMAL";
+    attribute GSR of cts_fpga2_reg_mem_0_31_0 : label is "DISABLED";
+    attribute RESETMODE of cts_fpga2_reg_mem_0_31_0 : label is "SYNC";
+    attribute REGMODE_B of cts_fpga2_reg_mem_0_31_0 : label is "OUTREG";
+    attribute REGMODE_A of cts_fpga2_reg_mem_0_31_0 : label is "OUTREG";
+    attribute DATA_WIDTH_B of cts_fpga2_reg_mem_0_31_0 : label is "1";
+    attribute DATA_WIDTH_A of cts_fpga2_reg_mem_0_31_0 : label is "1";
 
 begin
     -- component instantiation statements
     scuba_vhi_inst: VHI
         port map (Z=>scuba_vhi);
 
-    cts_fpga2_reg_mem_a_0_0_31: DP16KB
+    cts_fpga2_reg_mem_0_0_31: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -549,7 +549,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_1_30: DP16KB
+    cts_fpga2_reg_mem_0_1_30: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -592,7 +592,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_2_29: DP16KB
+    cts_fpga2_reg_mem_0_2_29: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -635,7 +635,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_3_28: DP16KB
+    cts_fpga2_reg_mem_0_3_28: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -678,7 +678,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_4_27: DP16KB
+    cts_fpga2_reg_mem_0_4_27: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -721,7 +721,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_5_26: DP16KB
+    cts_fpga2_reg_mem_0_5_26: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -764,7 +764,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_6_25: DP16KB
+    cts_fpga2_reg_mem_0_6_25: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -807,7 +807,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_7_24: DP16KB
+    cts_fpga2_reg_mem_0_7_24: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -850,7 +850,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_8_23: DP16KB
+    cts_fpga2_reg_mem_0_8_23: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -893,7 +893,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_9_22: DP16KB
+    cts_fpga2_reg_mem_0_9_22: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -936,7 +936,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_10_21: DP16KB
+    cts_fpga2_reg_mem_0_10_21: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -979,7 +979,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_11_20: DP16KB
+    cts_fpga2_reg_mem_0_11_20: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1022,7 +1022,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_12_19: DP16KB
+    cts_fpga2_reg_mem_0_12_19: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1065,7 +1065,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_13_18: DP16KB
+    cts_fpga2_reg_mem_0_13_18: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1108,7 +1108,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_14_17: DP16KB
+    cts_fpga2_reg_mem_0_14_17: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1151,7 +1151,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_15_16: DP16KB
+    cts_fpga2_reg_mem_0_15_16: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1194,7 +1194,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_16_15: DP16KB
+    cts_fpga2_reg_mem_0_16_15: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1237,7 +1237,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_17_14: DP16KB
+    cts_fpga2_reg_mem_0_17_14: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1280,7 +1280,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_18_13: DP16KB
+    cts_fpga2_reg_mem_0_18_13: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1323,7 +1323,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_19_12: DP16KB
+    cts_fpga2_reg_mem_0_19_12: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1366,7 +1366,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_20_11: DP16KB
+    cts_fpga2_reg_mem_0_20_11: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1409,7 +1409,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_21_10: DP16KB
+    cts_fpga2_reg_mem_0_21_10: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1452,7 +1452,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_22_9: DP16KB
+    cts_fpga2_reg_mem_0_22_9: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1495,7 +1495,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_23_8: DP16KB
+    cts_fpga2_reg_mem_0_23_8: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1538,7 +1538,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_24_7: DP16KB
+    cts_fpga2_reg_mem_0_24_7: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1581,7 +1581,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_25_6: DP16KB
+    cts_fpga2_reg_mem_0_25_6: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1624,7 +1624,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_26_5: DP16KB
+    cts_fpga2_reg_mem_0_26_5: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1667,7 +1667,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_27_4: DP16KB
+    cts_fpga2_reg_mem_0_27_4: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1710,7 +1710,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_28_3: DP16KB
+    cts_fpga2_reg_mem_0_28_3: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1753,7 +1753,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_29_2: DP16KB
+    cts_fpga2_reg_mem_0_29_2: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1796,7 +1796,7 @@ begin
             DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, 
             DOB16=>open, DOB17=>open);
 
-    cts_fpga2_reg_mem_a_0_30_1: DP16KB
+    cts_fpga2_reg_mem_0_30_1: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1842,7 +1842,7 @@ begin
     scuba_vlo_inst: VLO
         port map (Z=>scuba_vlo);
 
-    cts_fpga2_reg_mem_a_0_31_0: DP16KB
+    cts_fpga2_reg_mem_0_31_0: DP16KB
         -- synopsys translate_off
         generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", 
         WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC", 
@@ -1889,7 +1889,7 @@ end Structure;
 
 -- synopsys translate_off
 library ecp2m;
-configuration Structure_CON of cts_fpga2_reg_mem_a is
+configuration Structure_CON of cts_fpga2_reg_mem is
     for Structure
         for all:VHI use entity ecp2m.VHI(V); end for;
         for all:VLO use entity ecp2m.VLO(V); end for;

diff --git a/cts_fpga2_trb_no_fpga.xcf b/cts_fpga2_trb_no_fpga.xcf
index 1291f2dc4c4f2420b697f2b29f19d6057e5ce2f4..33098913886b136bf3c43b6b8d2af4e635aaf7e5 100644 (file)
--- a/cts_fpga2_trb_no_fpga.xcf
+++ b/cts_fpga2_trb_no_fpga.xcf
@@ -48,7 +48,7 @@
                        </Bypass>
                        <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
                        <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
-                       <FileTime>8/13/2010 0:0:41</FileTime>
+                       <FileTime>1/4/2012 15:5:51</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>

diff --git a/cts_simulation_tb.mpf b/cts_simulation_tb.mpf
index 524f2026ba91cbdba7f71df6ec03d1d776cfd015..d40da45d65321e2f3181d275de8fcb3e161be78f 100644 (file)
--- a/cts_simulation_tb.mpf
+++ b/cts_simulation_tb.mpf
@@ -583,7 +583,7 @@ Resolution = ns
 UserTimeUnit = default
 
 ; Default run length
-RunLength = 450 us
+RunLength = 10 ns
 
 ; Maximum iterations that can be run without advancing simulation time
 IterationLimit = 5000
@@ -631,7 +631,7 @@ IterationLimit = 5000
 ; The severity of VHDL assertion or severity system task
 ; should be higher or equal.
 ; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
-BreakOnAssertion = 3
+BreakOnAssertion = 4
 
 ; VHDL assertion Message Format
 ; %S - Severity Level 
@@ -1462,6 +1462,7 @@ DumpportsCollapse = 1
 ; instead of the leftmost value.
 ; EnumBaseInit = 1
 
+DelayFileOpen = 1
 [lmc]
 ; The simulator's interface to Logic Modeling's SmartModel SWIFT software
 libsm = $MODEL_TECH/libsm.sl
@@ -1547,284 +1548,284 @@ Project_Version = 6
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 139
-Project_File_0 = /home/marek/trbv2/up_down_counter.vhd
-Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 117 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_0 = /home/marek/trbnet/basics/ram.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 59 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_1 = /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
-Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 75 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_2 = /home/marek/trbnet/basics/ram.vhd
-Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 59 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_3 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd
-Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 81 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_4 = /home/marek/trbnet/basics/ram_16x8_dp.vhd
-Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 60 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_5 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 40 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_6 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd
-Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_7 = /home/marek/trbnet/special/spi_master.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 113 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_2 = /home/marek/trbv2/up_down_counter.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_3 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_4 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 40 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_5 = /home/marek/trbnet/basics/ram_16x8_dp.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 60 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_6 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_7 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_8 = /home/marek/trbnet/trb_net_priority_arbiter.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 95 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_9 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_9 = /home/marek/trbnet/special/spi_master.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 113 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_10 = /home/marek/ctsaddon/simulation/ram_register.vhd
-Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_11 = /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd
-Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 74 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 74 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_12 = /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd
-Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 68 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_13 = /home/marek/trbnet/trb_net_sbuf6.vhd
-Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 98 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_14 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd
-Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 36 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325773805 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_15 = /home/marek/trbnet/special/handler_trigger_and_data.vhd
-Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 111 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 111 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_16 = /home/marek/trbnet/trb_net16_term.vhd
-Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 55 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 55 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_17 = /home/marek/trbnet/trb_net_dummy_fifo.vhd
-Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 93 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_18 = /home/marek/trbnet/trb_net_sbuf.vhd
-Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 97 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_19 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd
-Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 89 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_20 = /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd
-Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 67 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 67 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_21 = /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd
-Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 33 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_22 = /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd
-Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 101 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_23 = /home/marek/ctsaddon/simulation/pll_in200_out40.vhd
-Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_24 = /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd
-Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_25 = /home/marek/ctsaddon/simulation/cts_width_rom.vhd
-Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_26 = /home/marek/trbnet/special/handler_lvl1.vhd
-Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 110 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 110 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_27 = /home/marek/trbnet/trb_net16_sbuf.vhd
-Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 108 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 108 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_28 = /home/marek/trbv2/f_divider.vhd
-Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 116 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 116 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_29 = /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd
-Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 23 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_30 = /home/marek/trbnet/trb_net16_obuf_nodata.vhd
-Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 54 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_31 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd
-Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 37 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_32 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd
-Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 124 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_33 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd
-Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 32 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_34 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd
-Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 133 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_35 = /home/marek/trbnet/special/spi_databus_memory.vhd
-Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 112 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_36 = /home/marek/trbnet/special/spi_slim.vhd
-Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 131 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_37 = /home/marek/trbnet/trb_net16_term_buf.vhd
-Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 56 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_38 = /home/marek/trbnet/basics/pulse_stretch.vhd
-Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 129 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_39 = /home/marek/trbnet/trb_net16_iobuf.vhd
-Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 104 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_40 = /home/marek/trbnet/trb_net16_regIO.vhd
-Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 106 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_41 = /home/marek/trbnet/trb_net16_ibuf.vhd
-Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 102 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_42 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd
-Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 118 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 118 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_43 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd
-Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 79 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_44 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd
-Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321978606 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 138 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325766507 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_45 = /home/marek/trbnet/trb_net16_ipudata.vhd
-Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 53 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_46 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd
-Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 38 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_47 = /home/marek/trbnet/trb_net_CRC.vhd
-Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 92 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_48 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd
-Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 135 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 38 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_47 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd
+Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_48 = /home/marek/trbnet/trb_net_CRC.vhd
+Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 92 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_49 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd
-Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 103 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_50 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd
-Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 72 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_51 = /home/marek/ctsaddon/simulation/delay_fifo.vhd
-Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 103 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_50 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd
+Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_51 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd
+Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 39 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_52 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd
-Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_53 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd
-Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 39 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_54 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd
-Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_55 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd
-Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 78 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_53 = /home/marek/ctsaddon/simulation/delay_fifo.vhd
+Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_54 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd
+Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_55 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd
+Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_56 = /home/marek/trbnet/trb_net16_api_base.vhd
-Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 99 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_57 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd
-Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_57 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd
+Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 78 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_58 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd
-Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 41 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_59 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd
-Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 76 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_59 = /home/marek/ctsaddon/simulation/cts_readout.vhd
+Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_60 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd
-Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 132 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_61 = /home/marek/ctsaddon/simulation/cts_readout.vhd
-Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_62 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
-Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 124 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_63 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd
-Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 52 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_64 = /home/marek/trbnet/trb_net_onewire_listener.vhd
-Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 128 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_65 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd
-Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_66 = /home/marek/trbnet/trb_net_pattern_gen.vhd
-Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 94 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_67 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd
-Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 42 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_68 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd
-Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_69 = /home/marek/ctsaddon/simulation/cts_components.vhd
-Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_70 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd
-Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 84 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_71 = /home/marek/trbnet/special/trb_net_reset_handler.vhd
-Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 66 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 131 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_61 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd
+Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 76 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_62 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd
+Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_63 = /home/marek/trbnet/trb_net_onewire_listener.vhd
+Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 127 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_64 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd
+Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_65 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
+Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_66 = /home/marek/ctsaddon/simulation/cts_components.vhd
+Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_67 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd
+Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_68 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd
+Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 42 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_69 = /home/marek/trbnet/trb_net_pattern_gen.vhd
+Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_70 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd
+Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_71 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd
+Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_72 = /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd
-Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 43 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_73 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd
-Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 35 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_74 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd
-Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_75 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd
-Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 71 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_73 = /home/marek/trbnet/special/trb_net_reset_handler.vhd
+Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 66 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_74 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd
+Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 84 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_75 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd
+Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 44 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_76 = /home/marek/trbnet/trb_net_onewire.vhd
-Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 127 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_77 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd
-Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 44 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_78 = /home/marek/trbv2/etrax_write_read_tb.vhd
-Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 120 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_77 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd
+Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_78 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd
+Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_79 = /home/marek/trbnet/basics/ram_dp.vhd
-Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 62 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_80 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd
-Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_81 = /home/marek/ctsaddon/cts_fpga1_test.vhd
-Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321889254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 119 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_82 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd
-Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 107 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_80 = /home/marek/trbv2/etrax_write_read_tb.vhd
+Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 119 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_81 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd
+Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_82 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd
+Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_83 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd
-Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_84 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd
-Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 45 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_85 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd
-Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_84 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd
+Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 107 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_85 = /home/marek/ctsaddon/cts_fpga1_test.vhd
+Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325688824 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_86 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd
-Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 85 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_87 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd
-Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 123 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_88 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd
-Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 69 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_89 = /home/marek/trbnet/trb_net_sbuf5.vhd
-Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 49 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_90 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd
-Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 21 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_91 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
-Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 115 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_92 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd
-Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 88 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_87 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd
+Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_88 = /home/marek/trbnet/trb_net_sbuf5.vhd
+Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_89 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd
+Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 69 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_90 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd
+Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_91 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd
+Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_92 = /home/marek/ctsaddon/simulation/version.vhd
+Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_93 = /home/marek/trbnet/special/handler_ipu.vhd
-Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 109 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_94 = /home/marek/ctsaddon/simulation/version.vhd
-Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321458601 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_95 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd
-Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 109 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_94 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd
+Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 88 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_95 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
+Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 115 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_96 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd
-Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 46 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 46 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_97 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd
-Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 70 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_98 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd
-Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321871053 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 126 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_99 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd
-Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 87 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_100 = /home/marek/trbnet/trb_net_priority_encoder.vhd
-Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 96 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_101 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd
-Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 22 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_102 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd
-Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 48 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_103 = /home/marek/ctsaddon/simulation/cts_downscale.vhd
-Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 31 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_98 = /home/marek/ctsaddon/simulation/cts_downscale.vhd
+Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_99 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd
+Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_100 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd
+Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_101 = /home/marek/trbnet/trb_net_priority_encoder.vhd
+Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 96 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_102 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd
+Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 87 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_103 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd
+Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_104 = /home/marek/trbnet/trb_net16_obuf.vhd
-Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 105 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_105 = /home/marek/trbnet/trb_net16_term_ibuf.vhd
-Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 57 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_106 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd
-Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 30 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_107 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd
-Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 82 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_108 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd
-Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977291 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 136 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 105 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_105 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd
+Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_106 = /home/marek/trbnet/trb_net16_term_ibuf.vhd
+Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_107 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd
+Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_108 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd
+Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 82 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_109 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd
-Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 77 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_110 = /home/marek/trbnet/basics/ram_16x16_dp.vhd
-Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 61 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_110 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd
+Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_111 = /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd
-Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_112 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd
-Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 34 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_113 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd
-Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 90 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_112 = /home/marek/trbnet/basics/ram_16x16_dp.vhd
+Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 61 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_113 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd
+Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 135 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_114 = /home/marek/ctsaddon/simulation/dll_edge.vhd
-Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_115 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd
-Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321978014 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002
-Project_File_116 = /home/marek/trbnet/basics/signal_sync.vhd
-Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 65 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_117 = /home/marek/ctsaddon/simulation/multiplicity.vhd
-Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 29 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_118 = /home/marek/trbnet/basics/ram_dp_rw.vhd
-Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 63 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_115 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd
+Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_116 = /home/marek/ctsaddon/simulation/multiplicity.vhd
+Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_117 = /home/marek/trbnet/basics/signal_sync.vhd
+Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 65 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_118 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd
+Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_119 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd
-Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_120 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd
-Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_121 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd
-Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 73 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_120 = /home/marek/trbnet/basics/ram_dp_rw.vhd
+Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 63 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_121 = /home/marek/ctsaddon/simulation/trb_net_components.vhd
+Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_122 = /home/marek/trbnet/trb_net16_trigger.vhd
-Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 58 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_123 = /home/marek/ctsaddon/simulation/trb_net_components.vhd
-Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 91 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 58 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_123 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd
+Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 73 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_124 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd
-Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 122 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_125 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd
-Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 121 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_126 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd
-Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 100 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_127 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd
-Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 120 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_126 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd
+Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_127 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd
+Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 100 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_128 = /home/marek/ctsaddon/simulation/cts_delay.vhd
-Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 24 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_129 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd
-Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 114 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_130 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd
-Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 80 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_129 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd
+Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 80 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_130 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd
+Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 114 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_131 = /home/marek/trbnet/special/handler_data.vhd
-Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 130 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_132 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd
-Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 86 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 129 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_132 = /home/marek/trbnet/trb_net_std.vhd
+Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_133 = /home/marek/trbnet/basics/rom_16x8.vhd
-Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 64 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_134 = /home/marek/trbnet/trb_net_std.vhd
-Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 50 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd
+Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_135 = /home/marek/ctsaddon/simulation/cts_set_width.vhd
-Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 134 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325759970 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_136 = /home/marek/trbnet/trb_net16_addresses.vhd
-Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 51 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_137 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd
-Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 83 dont_compile 0 cover_nosub 0 vhdl_use93 2002
-Project_File_138 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd
-Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 47 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_137 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd
+Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 47 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_138 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd
+Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0

diff --git a/version.vhd b/version.vhd
index 695148d7fc081aa5d89799734cea1f2a27bff021..913b9c2d748718d9be73a89a938bfc6dd2fac787 100644 (file)
--- a/version.vhd
+++ b/version.vhd
@@ -8,6 +8,6 @@ use ieee.numeric_std.all;
 
 package version is
 
-    constant VERSION_NUMBER_TIME  : integer   := 1325593830;
+    constant VERSION_NUMBER_TIME  : integer   := 1325773800;
 
 end package version;