*** empty log message ***

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index ad8f0bb2651a3bdccae0b61a2711e49112cb35ab..c431f7c2e678f922b997344ae0527b82dab958bc 100644 (file)
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -190,7 +190,8 @@ signal flash_go      : std_logic;
 signal flash_busy    : std_logic;\r
 signal flash_err     : std_logic;\r
 \r
-signal inp_select    : integer range 0 to 15 := 0;\r
+signal inp_select    : integer range 0 to 31 := 0;\r
+signal inp_invert   : std_logic_vector(15 downto 0);\r
 signal input_enable : std_logic_vector(15 downto 0);\r
 signal inp_status   : std_logic_vector(15 downto 0);\r
 signal led_status   : std_logic_vector(4  downto 0);\r
@@ -391,7 +392,8 @@ THE_IO_REG_READ : process begin
       when x"0" => spi_reg20_i <= input_enable;\r
       when x"1" => spi_reg20_i <= inp_status;\r
       when x"2" => spi_reg20_i <= x"00" & "000" & led_status(4) & leds;\r
-      when x"3" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(inp_select,4));\r
+      when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
+      when x"4" => spi_reg20_i <= inp_invert;\r
       when others => null;\r
     end case;\r
   else\r
@@ -410,7 +412,8 @@ THE_IO_REG_WRITE : process begin
       when x"0" => input_enable <= spi_data_i;\r
       when x"1" => null;\r
       when x"2" => led_status <= spi_data_i(4 downto 0);\r
-      when x"3" => inp_select <= to_integer(unsigned(spi_data_i(3 downto 0)));\r
+      when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));\r
+      when x"4" => inp_invert <= spi_data_i;\r
       when others => null;\r
     end case;\r
   end if;\r
@@ -435,14 +438,22 @@ end process;
 ---------------------------------------------------------------------------\r
 -- Rest of the I/O\r
 ---------------------------------------------------------------------------\r
-CON <= INP and not input_enable;\r
+CON <= (INP xor inp_invert) and not input_enable;\r
 \r
 SPARE_LINE(0) <= '0'; --clk_26;\r
 SPARE_LINE(1) <= '0'; --clk_i;\r
 SPARE_LINE(2) <= '0'; --timer(18);\r
 SPARE_LINE(3) <= '0';\r
 \r
-SPARE_LVDS <= INP(inp_select+1);\r
+\r
+SPARE_OUTPUT : process(INP, inp_select, input_enable)\r
+  begin\r
+    if inp_select < 16 then\r
+      SPARE_LVDS <= INP(inp_select+1);\r
+    else\r
+      SPARE_LVDS <= or_all(INP and not input_enable);\r
+    end if;\r
+  end process;\r
 \r
 -- TEST_LINE(0) <= '0';\r
 -- TEST_LINE(15 downto 1) <= (others => '0');\r

diff --git a/wasa/sim/machxo.mpf b/wasa/sim/machxo.mpf
index ac15a64a0cbc740eb9ed9f270022aba06ed9dc21..7b8bc7d49b4c850a7049d6c8b33c14774018c1bb 100644 (file)
--- a/wasa/sim/machxo.mpf
+++ b/wasa/sim/machxo.mpf
@@ -1657,11 +1657,11 @@ Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
 Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd
 Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd
-Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921672 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921672 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
 Project_File_6 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd
 Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346765030 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_7 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd
-Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921711 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346921711 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_8 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd
 Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_9 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd

diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd
index 97faf8558ba21ca8acddeb514df43c75248b4445..6127fbbb536a6f67af9f851e5edc8100fa4787f7 100644 (file)
--- a/wasa/trb3_periph_padiwa.vhd
+++ b/wasa/trb3_periph_padiwa.vhd
@@ -28,9 +28,6 @@ entity trb3_periph_padiwa is
     CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 0, not used
     SERDES_TX        : out std_logic_vector(3 downto 2);
     SERDES_RX        : in  std_logic_vector(3 downto 2);
-    SFP_TXDIS        : out std_logic;
-    SFP_MOD          : inout std_logic_vector(2 downto 0);
-    SFP_LOS          : in  std_logic;
 
     FPGA5_COMM           : inout std_logic_vector(11 downto 0);
                                         --Bit 0/1 input, serial link RX active
@@ -39,7 +36,7 @@ entity trb3_periph_padiwa is
     
     --Connections
     SPARE_LINE : inout std_logic_vector( 3 downto 0);
-    INP        : in    std_logic_vector(64 downto 1);
+    INP        : in    std_logic_vector(63 downto 0);
 
     --Flash ROM & Reboot
     FLASH_CLK  : out   std_logic;
@@ -49,10 +46,10 @@ entity trb3_periph_padiwa is
     PROGRAMN   : out   std_logic;                     --reboot FPGA
 
     --DAC
-    OUT_SDO    : out   std_logic_vector(3 downto 0);
-    IN_SDI     : in    std_logic_vector(3 downto 0);
-    OUT_SCK    : out   std_logic_vector(3 downto 0);
-    OUT_CS     : out   std_logic_vector(3 downto 0);
+    OUT_SDO    : out   std_logic_vector(4 downto 1);
+    IN_SDI     : in    std_logic_vector(4 downto 1);
+    OUT_SCK    : out   std_logic_vector(4 downto 1);
+    OUT_CS     : out   std_logic_vector(4 downto 1);
     --Misc
     TEMPSENS      : inout std_logic;       --Temperature Sensor
     CODE_LINE     : in    std_logic_vector(1 downto 0);
@@ -208,11 +205,8 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
   signal padiwa_sdi    : std_logic;
   signal padiwa_sdo    : std_logic;
   
-  --FPGA Test
-  signal time_counter : unsigned(31 downto 0);
-
   --TDC
-  signal hit_in_i : std_logic_vector(64 downto 1);
+  signal hit_in_i : std_logic_vector(63 downto 0);
 
   --TDC component
   component TDC
@@ -412,7 +406,8 @@ begin
       REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
       REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
       REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-      REGIO_VAR_ENDPOINT_ID              => (others => '0'),
+      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
+      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
 
       BUS_ADDR_OUT         => regio_addr_out,
       BUS_READ_ENABLE_OUT  => regio_read_enable_out,
@@ -619,14 +614,7 @@ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
 --  TEST_LINE(15 downto 0) <= (others => '0');
 
 
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-  process
-  begin
-    wait until rising_edge(clk_100_i);
-    time_counter <= time_counter + 1;
-  end process;
+
 
 -------------------------------------------------------------------------------
 -- TDC
@@ -641,7 +629,7 @@ padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
       CLK_TDC               => CLK_PCLK_LEFT,  -- Clock used for the time measurement
       CLK_READOUT           => clk_100_i,   -- Clock for the readout
       REFERENCE_TIME        => timing_trg_received_i,   -- Reference time input
-      HIT_IN                => hit_in_i(16 downto 1),  -- Channel start signals
+      HIT_IN                => hit_in_i(15 downto 0),  -- Channel start signals
       TRG_WIN_PRE           => ctrl_reg(42 downto 32),  -- Pre-Trigger window width
       TRG_WIN_POST          => ctrl_reg(58 downto 48),  -- Post-Trigger window width
       --