additional buffers for synchronizing hitbus and szintilator signals

diff --git a/mupix/sources/MuPix3_boardinterface.vhd b/mupix/sources/MuPix3_boardinterface.vhd
index 07ec5103a57431f4e78241f6b3f9ab06d8c35db9..e2c51f880ac7be51c7490d81b92e1bb2bf815eec 100644 (file)
--- a/mupix/sources/MuPix3_boardinterface.vhd
+++ b/mupix/sources/MuPix3_boardinterface.vhd
@@ -50,6 +50,8 @@ end entity board_interface;
 architecture rtl of board_interface is
 
   signal invert_signals_int : std_logic := '0';
+  signal szintilator_sync_buf : std_logic := '0';
+  signal hitbus_buf : std_logic := '0';
   
 begin
 
@@ -57,11 +59,13 @@ begin
    fast_sync: process (fast_clk_in) is
    begin  -- process fast_sync
      if rising_edge(fast_clk_in) then
-       szintilator_sync <= fpga_aux_from_board(0);
+       hitbus_buf <= hbus_from_mupix;
+       szintilator_sync_buf <= fpga_aux_from_board(0);
+       szintilator_sync <= szintilator_sync_buf;
        if invert_signals_int = '1' then
-         hbus_from_mupix_sync <=  hbus_from_mupix;
+         hbus_from_mupix_sync <=  hitbus_buf;
        else
-         hbus_from_mupix_sync <=  not hbus_from_mupix;
+         hbus_from_mupix_sync <=  not hitbus_buf;
        end if;
      end if;
    end process fast_sync;

diff --git a/mupix/sources/graycounter.vhd b/mupix/sources/graycounter.vhd
index aaddd0722c66e9990680783a0cfe9380d3678a06..894501430019df21b2d5c3582eb4746e1c984750 100644 (file)
--- a/mupix/sources/graycounter.vhd
+++ b/mupix/sources/graycounter.vhd
@@ -55,10 +55,6 @@ begin
 
   process(clk, reset)
   begin
-    --if(reset = '1') then
-    --  counter_reg    <= (others => '0');
-    --  counter_reg(0) <= '1';
-    --  no_ones_below(0) <= '1';
     if (clk'event and clk = '1') then
       if (sync_reset = '1') then
         no_ones_below(0) <= '1';