--TDC settings
constant BOARD : string := "dirich"; -- Options: dirich, trb3
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
# synplify_command => "/d/jspc29/lattice/diamond/3.7_x64/bin/lin64/synpwrap -fg -options",
# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
-nodelist_file => 'nodelist_frankfurt.txt',
+nodelist_file => '../nodelist_frankfurt.txt',
pinout_file => 'dirich2',
par_options => '../par.p2t',
#Include only necessary lpf files
#pinout_file => '', #name of pin-out file, if not equal TOPNAME
-include_TDC => 0,
+include_TDC => 1,
include_GBE => 0,
#Report settings
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
- <Property name="PROP_PAR_PARModArgs" value="" time="0"/>
+ <Property name="PROP_PAR_PARModArgs" value="-exp parHold=ON:parHoldLimit=10000" time="0"/>
<Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/>
<Property name="PROP_PAR_ParMatchFact" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
-REGION "MEDIA" "R81C45D" 12 28;
+REGION "MEDIA" "R81C45D" 12 40;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
set_option -part_companion ""
# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
set_option -top_module "dirich"
+set_option -resource_sharing false
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
# set result format/file last
project -result_format "edif"
project -result_file "workdir/dirich.edf"
+set_option log_file "workdir/dirich_project.srf"
+#implementation attributes
-
-#compilation/mapping options
-set_option -symbolic_fsm_compiler true
-set_option -resource_sharing true
-
-#use verilog 2001 standard option
set_option -vlog_std v2001
-
-#map options
-set_option -frequency auto
-set_option -maxfan 1000
-set_option -auto_constrain_io 0
-set_option -disable_io_insertion false
-set_option -retiming false;
-set_option -pipe true
-set_option -force_gsr false
-set_option -compiler_compatible 0
-set_option -dup false
-
-set_option -default_enum_encoding default
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#synplifyPro options
-set_option -fix_gated_and_generated_clocks 1
-set_option -update_models_cp 0
-set_option -resolve_multiple_driver 0
-
-
set_option -project_relative_includes 1
impl -active "workdir"
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout.vhd"
add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd"
add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC.vhd"
add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd"
--TEST_LINE(8 downto 1) <= med_stat_debug(7 downto 0);
--TEST_LINE(8 downto 1) <= clk_sys & med_stat_debug(9) & med_stat_debug(10) & med_stat_debug(11) & clear_i & reset_i & link_stat_out & link_stat_in_reg;
- TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6);
+-- TEST_LINE(8 downto 3) <= clear_i & reset_i & link_stat_out & link_stat_in_reg & debug_clock_reset(0) & med_stat_debug(4);-- & med_stat_debug(5) & med_stat_debug(6);
---------------------------------------------------------------------------
-- LCD Data to display
---------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
--- THE_TDC : entity work.TDC_record
--- generic map (
--- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
--- STATUS_REG_NR => 21, -- Number of status regs
--- DEBUG => c_YES,
--- SIMULATION => c_NO)
--- port map (
--- RESET => reset_i,
--- CLK_TDC => CLOCK_IN,
--- CLK_READOUT => clk_sys, -- Clock for the readout
--- REFERENCE_TIME => TRIG_IN, -- Reference time input
--- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
--- HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC
--- -- Trigger signals from handler
--- BUSRDO_RX => readout_rx,
--- BUSRDO_TX => readout_tx(0),
--- -- Slow control bus
--- BUS_RX => bustdc_rx,
--- BUS_TX => bustdc_tx,
--- -- Dubug signals
--- INFO_IN => timer,
--- LOGIC_ANALYSER_OUT => logic_analyser_i
--- );
---
--- -- For single edge measurements
--- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
--- hit_in_i <= INPUT;
--- end generate;
+ THE_TDC : entity work.TDC_record
+ generic map (
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
+ DEBUG => c_YES,
+ SIMULATION => c_NO)
+ port map (
+ RESET => reset_i,
+ CLK_TDC => CLOCK_IN,
+ CLK_READOUT => clk_sys, -- Clock for the readout
+ REFERENCE_TIME => TRIG_IN, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => CLOCK_CAL, -- Hits for calibrating the TDC
+ -- Trigger signals from handler
+ BUSRDO_RX => readout_rx,
+ BUSRDO_TX => readout_tx(0),
+ -- Slow control bus
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx,
+ -- Dubug signals
+ INFO_IN => timer,
+ LOGIC_ANALYSER_OUT => logic_analyser_i
+ );
+
+-- For single edge measurements
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
+ hit_in_i <= INPUT;
+ end generate;
--
-- -- For ToT Measurements
-- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
-- end generate;
-readout_tx(0).data_finished <= '1';
-readout_tx(0).data_write <= '0';
-readout_tx(0).busy_release <= '1';
+-- readout_tx(0).data_finished <= '1';
+-- readout_tx(0).data_write <= '0';
+-- readout_tx(0).busy_release <= '1';
end architecture;
[jspc29]
SYSTEM = linux
CORENUM = 3
-ENV = /d/jspc29/lattice/37_settings.sh
+ENV = /d/jspc29/lattice/39_settings.sh
WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir
[jspc57]
SYSTEM = linux
CORENUM = 7
-ENV = /d/jspc29/lattice/37_settings.sh
+ENV = /d/jspc29/lattice/39_settings.sh
WORKDIR = /d/jspc22/trb/git/dirich/dirich/workdir
-l 5
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 1 # Controlled by the compile.pl script.
--s 1
--t 1
+-s 10
+-t 3
-c 0
-e 0
-i 6
--exp parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1
-
#-exp parPlcInLimit=0
#-exp parPlcInNeighborSize=1
-#-exp parHold=ON
-#-exp parHoldLimit=10000
#General PAR Command Line Options
# -w With this option, any files generated will overwrite existing files
# (e.g., any .par, .pad files).
# parHold.
# parPlcInLimit Cannot find in the online help
# parPlcInNeighborSize Cannot find in the online help
-
+-exp parHold=ON:parHoldLimit=10000:parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1:parHold=2
jspc29 / dirich.git / commitdiff