fixed bugs in RX_LSM

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index e51533de9fea4cb38ebf448e25924247576f864e..9c1f2c2a7d0f498b5270b1a86a7b6c394497dbf8 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -1058,10 +1058,10 @@ end generate;
 -- LED
 ---------------------------------------------------------------------------
   --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
-  LED_GREEN            <= debug_i(11); -- LFD  --debug_clock_reset(0);   
-  LED_ORANGE           <= debug_i(10); -- LHD  --debug_clock_reset(1);
-  LED_RED              <= debug_i(8);  -- LRR  --not sed_error_i;
-  LED_YELLOW           <= debug_i(7);  -- LTR  --debug_clock_reset(2);
+  LED_GREEN            <= not debug_i(11); -- LFD  --debug_clock_reset(0);   
+  LED_ORANGE           <= not debug_i(10); -- LHD  --debug_clock_reset(1);
+  LED_RED              <= not debug_i(8);  -- LRR  --not sed_error_i;
+  LED_YELLOW           <= not debug_i(7);  -- LTR  --debug_clock_reset(2);
 
 
   gen_leds_addon : if USE_ADDON = c_YES generate

diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd
index ce283939475e6432e1453c77401a1ac28a5e5146..bc6eef784ce67807d7836a36baecbdb9a6204e18 100644 (file)
--- a/tdctemplate/trb3sc_tdctemplate.vhd
+++ b/tdctemplate/trb3sc_tdctemplate.vhd
@@ -14,9 +14,6 @@ use work.version.all;
 use work.trb_net_gbe_components.all;
 use work.med_sync_define_RS.all;
 
---library ecp3;
---use ecp3.components.all;
-
 entity trb3sc_tdctemplate is
   port(
     CLK_SUPPL_PCLK       : in    std_logic; -- 125 MHz for GbE
@@ -35,7 +32,6 @@ entity trb3sc_tdctemplate is
     FEETEMP              : inout std_logic_vector(3 downto 0);
     --Additional IO
 --    HDR_IO               : inout std_logic_vector(10 downto 1);
---    HDR_IO               : inout std_logic_vector(10 downto 9);
     RJ_IO                : inout std_logic_vector(3 downto 0);
 --     SPARE_IN : in    std_logic_vector(1 downto 0);
     --LED
@@ -158,12 +154,8 @@ architecture trb3sc_arch of trb3sc_tdctemplate is
   signal tx_pcs_rst_i      : std_logic;
   signal debug_i           : std_logic_vector(31 downto 0);
   signal rx_dlm_i          : std_logic;
---  signal rx_dlm_iq         : std_logic; -- ADDED
   signal word_sync_i       : std_logic;
---  signal word_sync_iq      : std_logic; -- ADDED
   signal master_clk_i      : std_logic;
---  signal test_clk          : std_logic; -- ADDED
---  signal stat_debug_i      : std_logic_vector(63 downto 0);
   
   signal tx_reset_state    : std_logic_vector(3 downto 0);
   signal master_reset_i    : std_logic;
@@ -293,32 +285,6 @@ end generate;
       DEBUG_OUT          => debug_i
     );
 
---    THE_CLOCK_A: ODDRXD1
---    port map(
---      SCLK          => clk_full_osc,
---      DA            => '1',
---      DB            => '0',
---      Q             => HDR_IO(10)
---    );
-
---    THE_CLOCK_B: ODDRXD1
---    port map(
---      SCLK          => clk_full,
---      DA            => '1',
---      DB            => '0',
---      Q             => HDR_IO(10)
---    );
-    
---  test_clk <= stat_debug_i(7);
---    
---  THE_TRANSFER_PROC: process(test_clk)
---  begin
---    if( rising_edge(test_clk) ) then
---      word_sync_iq <= word_sync_i;
---      rx_dlm_iq    <= rx_dlm_i;
---    end if;
---  end process THE_TRANSFER_PROC;
-    
   THE_MAIN_TX_RST: main_tx_reset_RS
   generic map(
     SIM_MODE    => 0
@@ -352,8 +318,9 @@ end generate;
 --  HDR_IO(2)  <= rx_dlm_i;
 --  HDR_IO(1)  <= '0';
 
-  TEST_LINE(11 downto 0)  <= debug_i(11 downto 0);
-  TEST_LINE(15 downto 12) <= tx_reset_state;
+  TEST_LINE(15 downto 0) <= (others => '0');
+--  TEST_LINE(11 downto 0)  <= debug_i(11 downto 0);
+--  TEST_LINE(15 downto 12) <= tx_reset_state;
   
 ---------------------------------------------------------------------------
 -- Endpoint
@@ -403,7 +370,6 @@ end generate;
       TIMERS_OUT                => timer
       );
 
-
 ---------------------------------------------------------------------------
 -- Bus Handler
 ---------------------------------------------------------------------------
@@ -435,8 +401,6 @@ end generate;
       STAT_DEBUG => open
       );
 
-       
-      
 ---------------------------------------------------------------------------
 -- Control Tools
 ---------------------------------------------------------------------------
@@ -498,8 +462,6 @@ end generate;
 
 --  RJ_IO(1 downto 0) <= trig_gen_out_i(3 downto 2);
   RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0);
-  RJ_IO(0) <= clk_full_osc;
-  RJ_IO(1) <= clk_sys;
 
   BACK_GPIO(1 downto 0)  <= (others => 'Z');
   BACK_GPIO(3 downto 2)  <= trig_gen_out_i(3 downto 2);
@@ -546,8 +508,7 @@ gen_ada : if PINOUT = 3 or PINOUT = 4 generate
   DAC_OUT_SCK(2 downto 1) <= spi_clk(1 downto 0);
   DAC_OUT_CS(2 downto 1)  <= spi_cs(1 downto 0);
   DAC_OUT_SDO(2 downto 1) <= spi_mosi(1 downto 0);
-  
-  
+    
   spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
   DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
   DAC_OUT_CS(6 downto 5)  <= spi_cs(5 downto 4);
@@ -596,10 +557,10 @@ end generate;
 -- LED
 ---------------------------------------------------------------------------
   --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2)
-  LED_GREEN     <= debug_i(11); -- LFD  --debug_clock_reset(0);   
-  LED_ORANGE    <= debug_i(10); -- LHD  --debug_clock_reset(1);
-  LED_RED       <= debug_i(8);  -- LRR  --not sed_error_i;
-  LED_YELLOW    <= debug_i(7);  -- LTR  --debug_clock_reset(2);
+  LED_GREEN     <= not debug_i(11); -- LFD  --debug_clock_reset(0);   
+  LED_ORANGE    <= not debug_i(10); -- LHD  --debug_clock_reset(1);
+  LED_RED       <= not debug_i(8);  -- LRR  --not sed_error_i;
+  LED_YELLOW    <= not debug_i(7);  -- LTR  --debug_clock_reset(2);
   LED_WHITE(0)  <= time_counter(26) and time_counter(19);
   LED_WHITE(1)  <= time_counter(20);
   LED_SFP_GREEN <= not med2int(0).stat_op(9) & '1';  --SFP Link Status