update to CTS project file for TDCs

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 1faeba05bea47711d2b4ea383387c451d67fe841..235b16362d3db418002e6387e8b95e605301f2cc 100644 (file)
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -57,6 +57,7 @@ impl -active "workdir"
 #add_file options
 
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib "work" "tdc_release/tdc_version.vhd"
 add_file -vhdl -lib work "version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"

diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj
index c0e68cf354e1e6851dae18eacb0392616698b211..0fa01102cf963509a11afb1c9d2d9588a8397927 100644 (file)
--- a/wasa/trb3_periph_padiwa.prj
+++ b/wasa/trb3_periph_padiwa.prj
@@ -52,7 +52,7 @@ impl -active "workdir"
 #add_file options
 
 add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "currectRelease/tdc_version.vhd"
+add_file -vhdl -lib work "currentRelease/tdc_version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
@@ -96,6 +96,7 @@ add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
 
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
@@ -166,7 +167,9 @@ add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
 add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
 add_file -vhdl -lib "work" "currentRelease/hit_mux.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd"
 add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
 add_file -vhdl -lib "work" "../base/code/input_statistics.vhd"
 add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"