Use raw clock rather than 200 MHz output from PLL

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 1c4f4cdb53f69cc27bd9fb5856d5860fab10fe83..82c87d778036353bc0964ed2eef126449890c7aa 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -61,9 +61,9 @@ THE_PLL : entity work.pll_240_100 --PLL with 200 MHz input!
     );  
 
 gen_slow_clock : if USE_120_MHZ = 0 generate
-  RAW_CLK_OUT <= clock_200;
+  RAW_CLK_OUT <= clock_200_raw;
   sys_clk_i   <= clock_100;
-  REF_CLK_OUT <= clock_200;
+  REF_CLK_OUT <= clock_200_raw;
 end generate;
 gen_fast_clock : if USE_120_MHZ = 1 generate
   RAW_CLK_OUT <= clock_240;
@@ -72,7 +72,7 @@ gen_fast_clock : if USE_120_MHZ = 1 generate
 end generate;
 
 
-clear_n_i <= timer(24) when rising_edge(CLOCK_IN);
+clear_n_i <= timer(24) when rising_edge(clock_200_raw);
 
 process begin
   wait until rising_edge(sys_clk_i);
@@ -109,7 +109,7 @@ THE_RESET_HANDLER : trb_net_reset_handler
 
 RESET_OUT <= reset_i;
   
-last_reset_i <= reset_i when rising_edge(CLOCK_IN);
+last_reset_i <= reset_i when rising_edge(clock_200_raw);
 reset_rising <= reset_i and not last_reset_i;
   
 ---------------------------------------------------------------------------

diff --git a/combiner/par.p2t b/combiner/par.p2t
index a89b69b37e3fd0757083f70293287da98d0a36cf..7f2e7bfd981bb6a9c25ae97876b396e82433f4cb 100644 (file)
--- a/combiner/par.p2t
+++ b/combiner/par.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 31
+-t 33
 -c 1
 -e 2
 #-g guidefile.ncd