--- /dev/null
+\r
+\r
+--synopsys translate_off\r
+\r
+library pcsc_work;\r
+use pcsc_work.all;\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity PCSC is\r
+GENERIC(\r
+ CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt"\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+\r
+end PCSC;\r
+\r
+architecture PCSC_arch of PCSC is\r
+\r
+component PCSC_sim\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+\r
+begin\r
+\r
+PCSC_sim_inst : PCSC_sim\r
+generic map (\r
+ CONFIG_FILE => CONFIG_FILE)\r
+port map (\r
+ HDINN0 => HDINN0,\r
+ HDINN1 => HDINN1,\r
+ HDINN2 => HDINN2,\r
+ HDINN3 => HDINN3,\r
+ HDINP0 => HDINP0,\r
+ HDINP1 => HDINP1,\r
+ HDINP2 => HDINP2,\r
+ HDINP3 => HDINP3,\r
+ REFCLKN => REFCLKN,\r
+ REFCLKP => REFCLKP,\r
+ CIN11 => CIN11,\r
+ CIN10 => CIN10,\r
+ CIN9 => CIN9,\r
+ CIN8 => CIN8,\r
+ CIN7 => CIN7,\r
+ CIN6 => CIN6,\r
+ CIN5 => CIN5,\r
+ CIN4 => CIN4,\r
+ CIN3 => CIN3,\r
+ CIN2 => CIN2,\r
+ CIN1 => CIN1,\r
+ CIN0 => CIN0,\r
+ CYAWSTN => CYAWSTN,\r
+ FF_EBRD_CLK_3 => FF_EBRD_CLK_3,\r
+ FF_EBRD_CLK_2 => FF_EBRD_CLK_2,\r
+ FF_EBRD_CLK_1 => FF_EBRD_CLK_1,\r
+ FF_EBRD_CLK_0 => FF_EBRD_CLK_0,\r
+ FF_RXI_CLK_3 => FF_RXI_CLK_3,\r
+ FF_RXI_CLK_2 => FF_RXI_CLK_2,\r
+ FF_RXI_CLK_1 => FF_RXI_CLK_1,\r
+ FF_RXI_CLK_0 => FF_RXI_CLK_0,\r
+\r
+ FF_TX_D_0_0 => FF_TX_D_0_0,\r
+ FF_TX_D_0_1 => FF_TX_D_0_1,\r
+ FF_TX_D_0_2 => FF_TX_D_0_2,\r
+ FF_TX_D_0_3 => FF_TX_D_0_3,\r
+ FF_TX_D_0_4 => FF_TX_D_0_4,\r
+ FF_TX_D_0_5 => FF_TX_D_0_5,\r
+ FF_TX_D_0_6 => FF_TX_D_0_6,\r
+ FF_TX_D_0_7 => FF_TX_D_0_7,\r
+ FF_TX_D_0_8 => FF_TX_D_0_8,\r
+ FF_TX_D_0_9 => FF_TX_D_0_9,\r
+ FF_TX_D_0_10 => FF_TX_D_0_10,\r
+ FF_TX_D_0_11 => FF_TX_D_0_11,\r
+ FF_TX_D_0_12 => FF_TX_D_0_12,\r
+ FF_TX_D_0_13 => FF_TX_D_0_13,\r
+ FF_TX_D_0_14 => FF_TX_D_0_14,\r
+ FF_TX_D_0_15 => FF_TX_D_0_15,\r
+ FF_TX_D_0_16 => FF_TX_D_0_16,\r
+ FF_TX_D_0_17 => FF_TX_D_0_17,\r
+ FF_TX_D_0_18 => FF_TX_D_0_18,\r
+ FF_TX_D_0_19 => FF_TX_D_0_19,\r
+ FF_TX_D_0_20 => FF_TX_D_0_20,\r
+ FF_TX_D_0_21 => FF_TX_D_0_21,\r
+ FF_TX_D_0_22 => FF_TX_D_0_22,\r
+ FF_TX_D_0_23 => FF_TX_D_0_23,\r
+ FF_TX_D_1_0 => FF_TX_D_1_0,\r
+ FF_TX_D_1_1 => FF_TX_D_1_1,\r
+ FF_TX_D_1_2 => FF_TX_D_1_2,\r
+ FF_TX_D_1_3 => FF_TX_D_1_3,\r
+ FF_TX_D_1_4 => FF_TX_D_1_4,\r
+ FF_TX_D_1_5 => FF_TX_D_1_5,\r
+ FF_TX_D_1_6 => FF_TX_D_1_6,\r
+ FF_TX_D_1_7 => FF_TX_D_1_7,\r
+ FF_TX_D_1_8 => FF_TX_D_1_8,\r
+ FF_TX_D_1_9 => FF_TX_D_1_9,\r
+ FF_TX_D_1_10 => FF_TX_D_1_10,\r
+ FF_TX_D_1_11 => FF_TX_D_1_11,\r
+ FF_TX_D_1_12 => FF_TX_D_1_12,\r
+ FF_TX_D_1_13 => FF_TX_D_1_13,\r
+ FF_TX_D_1_14 => FF_TX_D_1_14,\r
+ FF_TX_D_1_15 => FF_TX_D_1_15,\r
+ FF_TX_D_1_16 => FF_TX_D_1_16,\r
+ FF_TX_D_1_17 => FF_TX_D_1_17,\r
+ FF_TX_D_1_18 => FF_TX_D_1_18,\r
+ FF_TX_D_1_19 => FF_TX_D_1_19,\r
+ FF_TX_D_1_20 => FF_TX_D_1_20,\r
+ FF_TX_D_1_21 => FF_TX_D_1_21,\r
+ FF_TX_D_1_22 => FF_TX_D_1_22,\r
+ FF_TX_D_1_23 => FF_TX_D_1_23,\r
+ FF_TX_D_2_0 => FF_TX_D_2_0,\r
+ FF_TX_D_2_1 => FF_TX_D_2_1,\r
+ FF_TX_D_2_2 => FF_TX_D_2_2,\r
+ FF_TX_D_2_3 => FF_TX_D_2_3,\r
+ FF_TX_D_2_4 => FF_TX_D_2_4,\r
+ FF_TX_D_2_5 => FF_TX_D_2_5,\r
+ FF_TX_D_2_6 => FF_TX_D_2_6,\r
+ FF_TX_D_2_7 => FF_TX_D_2_7,\r
+ FF_TX_D_2_8 => FF_TX_D_2_8,\r
+ FF_TX_D_2_9 => FF_TX_D_2_9,\r
+ FF_TX_D_2_10 => FF_TX_D_2_10,\r
+ FF_TX_D_2_11 => FF_TX_D_2_11,\r
+ FF_TX_D_2_12 => FF_TX_D_2_12,\r
+ FF_TX_D_2_13 => FF_TX_D_2_13,\r
+ FF_TX_D_2_14 => FF_TX_D_2_14,\r
+ FF_TX_D_2_15 => FF_TX_D_2_15,\r
+ FF_TX_D_2_16 => FF_TX_D_2_16,\r
+ FF_TX_D_2_17 => FF_TX_D_2_17,\r
+ FF_TX_D_2_18 => FF_TX_D_2_18,\r
+ FF_TX_D_2_19 => FF_TX_D_2_19,\r
+ FF_TX_D_2_20 => FF_TX_D_2_20,\r
+ FF_TX_D_2_21 => FF_TX_D_2_21,\r
+ FF_TX_D_2_22 => FF_TX_D_2_22,\r
+ FF_TX_D_2_23 => FF_TX_D_2_23,\r
+ FF_TX_D_3_0 => FF_TX_D_3_0,\r
+ FF_TX_D_3_1 => FF_TX_D_3_1,\r
+ FF_TX_D_3_2 => FF_TX_D_3_2,\r
+ FF_TX_D_3_3 => FF_TX_D_3_3,\r
+ FF_TX_D_3_4 => FF_TX_D_3_4,\r
+ FF_TX_D_3_5 => FF_TX_D_3_5,\r
+ FF_TX_D_3_6 => FF_TX_D_3_6,\r
+ FF_TX_D_3_7 => FF_TX_D_3_7,\r
+ FF_TX_D_3_8 => FF_TX_D_3_8,\r
+ FF_TX_D_3_9 => FF_TX_D_3_9,\r
+ FF_TX_D_3_10 => FF_TX_D_3_10,\r
+ FF_TX_D_3_11 => FF_TX_D_3_11,\r
+ FF_TX_D_3_12 => FF_TX_D_3_12,\r
+ FF_TX_D_3_13 => FF_TX_D_3_13,\r
+ FF_TX_D_3_14 => FF_TX_D_3_14,\r
+ FF_TX_D_3_15 => FF_TX_D_3_15,\r
+ FF_TX_D_3_16 => FF_TX_D_3_16,\r
+ FF_TX_D_3_17 => FF_TX_D_3_17,\r
+ FF_TX_D_3_18 => FF_TX_D_3_18,\r
+ FF_TX_D_3_19 => FF_TX_D_3_19,\r
+ FF_TX_D_3_20 => FF_TX_D_3_20,\r
+ FF_TX_D_3_21 => FF_TX_D_3_21,\r
+ FF_TX_D_3_22 => FF_TX_D_3_22,\r
+ FF_TX_D_3_23 => FF_TX_D_3_23,\r
+ FF_TXI_CLK_0 => FF_TXI_CLK_0,\r
+ FF_TXI_CLK_1 => FF_TXI_CLK_1,\r
+ FF_TXI_CLK_2 => FF_TXI_CLK_2,\r
+ FF_TXI_CLK_3 => FF_TXI_CLK_3,\r
+ FFC_CK_CORE_RX => FFC_CK_CORE_RX,\r
+ FFC_CK_CORE_TX => FFC_CK_CORE_TX,\r
+ FFC_EI_EN_0 => FFC_EI_EN_0,\r
+ FFC_EI_EN_1 => FFC_EI_EN_1,\r
+ FFC_EI_EN_2 => FFC_EI_EN_2,\r
+ FFC_EI_EN_3 => FFC_EI_EN_3,\r
+ FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,\r
+ FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,\r
+ FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,\r
+ FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,\r
+ FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,\r
+ FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,\r
+ FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,\r
+ FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,\r
+ FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,\r
+ FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,\r
+ FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,\r
+ FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,\r
+ FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,\r
+ FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,\r
+ FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,\r
+ FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,\r
+ FFC_MACRO_RST => FFC_MACRO_RST,\r
+ FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,\r
+ FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,\r
+ FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,\r
+ FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,\r
+ FFC_PCIE_CT_0 => FFC_PCIE_CT_0,\r
+ FFC_PCIE_CT_1 => FFC_PCIE_CT_1,\r
+ FFC_PCIE_CT_2 => FFC_PCIE_CT_2,\r
+ FFC_PCIE_CT_3 => FFC_PCIE_CT_3,\r
+ FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,\r
+ FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,\r
+ FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,\r
+ FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,\r
+ FFC_QUAD_RST => FFC_QUAD_RST,\r
+ FFC_RRST_0 => FFC_RRST_0,\r
+ FFC_RRST_1 => FFC_RRST_1,\r
+ FFC_RRST_2 => FFC_RRST_2,\r
+ FFC_RRST_3 => FFC_RRST_3,\r
+ FFC_RXPWDNB_0 => FFC_RXPWDNB_0,\r
+ FFC_RXPWDNB_1 => FFC_RXPWDNB_1,\r
+ FFC_RXPWDNB_2 => FFC_RXPWDNB_2,\r
+ FFC_RXPWDNB_3 => FFC_RXPWDNB_3,\r
+ FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,\r
+ FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,\r
+ FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,\r
+ FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,\r
+ FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,\r
+ FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,\r
+ FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,\r
+ FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,\r
+ FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,\r
+ FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,\r
+ FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,\r
+ FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,\r
+ FFC_TRST => FFC_TRST,\r
+ FFC_TXPWDNB_0 => FFC_TXPWDNB_0,\r
+ FFC_TXPWDNB_1 => FFC_TXPWDNB_1,\r
+ FFC_TXPWDNB_2 => FFC_TXPWDNB_2,\r
+ FFC_TXPWDNB_3 => FFC_TXPWDNB_3,\r
+ SCIADDR0 => SCIADDR0,\r
+ SCIADDR1 => SCIADDR1,\r
+ SCIADDR2 => SCIADDR2,\r
+ SCIADDR3 => SCIADDR3,\r
+ SCIADDR4 => SCIADDR4,\r
+ SCIADDR5 => SCIADDR5,\r
+ SCIENAUX => SCIENAUX,\r
+ SCIENCH0 => SCIENCH0,\r
+ SCIENCH1 => SCIENCH1,\r
+ SCIENCH2 => SCIENCH2,\r
+ SCIENCH3 => SCIENCH3,\r
+ SCIRD => SCIRD,\r
+ SCISELAUX => SCISELAUX,\r
+ SCISELCH0 => SCISELCH0,\r
+ SCISELCH1 => SCISELCH1,\r
+ SCISELCH2 => SCISELCH2,\r
+ SCISELCH3 => SCISELCH3,\r
+ SCIWDATA0 => SCIWDATA0,\r
+ SCIWDATA1 => SCIWDATA1,\r
+ SCIWDATA2 => SCIWDATA2,\r
+ SCIWDATA3 => SCIWDATA3,\r
+ SCIWDATA4 => SCIWDATA4,\r
+ SCIWDATA5 => SCIWDATA5,\r
+ SCIWDATA6 => SCIWDATA6,\r
+ SCIWDATA7 => SCIWDATA7,\r
+ SCIWSTN => SCIWSTN,\r
+ HDOUTN0 => HDOUTN0,\r
+ HDOUTN1 => HDOUTN1,\r
+ HDOUTN2 => HDOUTN2,\r
+ HDOUTN3 => HDOUTN3,\r
+ HDOUTP0 => HDOUTP0,\r
+ HDOUTP1 => HDOUTP1,\r
+ HDOUTP2 => HDOUTP2,\r
+ HDOUTP3 => HDOUTP3,\r
+ COUT19 => COUT19,\r
+ COUT18 => COUT18,\r
+ COUT17 => COUT17,\r
+ COUT16 => COUT16,\r
+ COUT15 => COUT15,\r
+ COUT14 => COUT14,\r
+ COUT13 => COUT13,\r
+ COUT12 => COUT12,\r
+ COUT11 => COUT11,\r
+ COUT10 => COUT10,\r
+ COUT9 => COUT9,\r
+ COUT8 => COUT8,\r
+ COUT7 => COUT7,\r
+ COUT6 => COUT6,\r
+ COUT5 => COUT5,\r
+ COUT4 => COUT4,\r
+ COUT3 => COUT3,\r
+ COUT2 => COUT2,\r
+ COUT1 => COUT1,\r
+ COUT0 => COUT0,\r
+ FF_RX_D_0_0 => FF_RX_D_0_0,\r
+ FF_RX_D_0_1 => FF_RX_D_0_1,\r
+ FF_RX_D_0_2 => FF_RX_D_0_2,\r
+ FF_RX_D_0_3 => FF_RX_D_0_3,\r
+ FF_RX_D_0_4 => FF_RX_D_0_4,\r
+ FF_RX_D_0_5 => FF_RX_D_0_5,\r
+ FF_RX_D_0_6 => FF_RX_D_0_6,\r
+ FF_RX_D_0_7 => FF_RX_D_0_7,\r
+ FF_RX_D_0_8 => FF_RX_D_0_8,\r
+ FF_RX_D_0_9 => FF_RX_D_0_9,\r
+ FF_RX_D_0_10 => FF_RX_D_0_10,\r
+ FF_RX_D_0_11 => FF_RX_D_0_11,\r
+ FF_RX_D_0_12 => FF_RX_D_0_12,\r
+ FF_RX_D_0_13 => FF_RX_D_0_13,\r
+ FF_RX_D_0_14 => FF_RX_D_0_14,\r
+ FF_RX_D_0_15 => FF_RX_D_0_15,\r
+ FF_RX_D_0_16 => FF_RX_D_0_16,\r
+ FF_RX_D_0_17 => FF_RX_D_0_17,\r
+ FF_RX_D_0_18 => FF_RX_D_0_18,\r
+ FF_RX_D_0_19 => FF_RX_D_0_19,\r
+ FF_RX_D_0_20 => FF_RX_D_0_20,\r
+ FF_RX_D_0_21 => FF_RX_D_0_21,\r
+ FF_RX_D_0_22 => FF_RX_D_0_22,\r
+ FF_RX_D_0_23 => FF_RX_D_0_23,\r
+ FF_RX_D_1_0 => FF_RX_D_1_0,\r
+ FF_RX_D_1_1 => FF_RX_D_1_1,\r
+ FF_RX_D_1_2 => FF_RX_D_1_2,\r
+ FF_RX_D_1_3 => FF_RX_D_1_3,\r
+ FF_RX_D_1_4 => FF_RX_D_1_4,\r
+ FF_RX_D_1_5 => FF_RX_D_1_5,\r
+ FF_RX_D_1_6 => FF_RX_D_1_6,\r
+ FF_RX_D_1_7 => FF_RX_D_1_7,\r
+ FF_RX_D_1_8 => FF_RX_D_1_8,\r
+ FF_RX_D_1_9 => FF_RX_D_1_9,\r
+ FF_RX_D_1_10 => FF_RX_D_1_10,\r
+ FF_RX_D_1_11 => FF_RX_D_1_11,\r
+ FF_RX_D_1_12 => FF_RX_D_1_12,\r
+ FF_RX_D_1_13 => FF_RX_D_1_13,\r
+ FF_RX_D_1_14 => FF_RX_D_1_14,\r
+ FF_RX_D_1_15 => FF_RX_D_1_15,\r
+ FF_RX_D_1_16 => FF_RX_D_1_16,\r
+ FF_RX_D_1_17 => FF_RX_D_1_17,\r
+ FF_RX_D_1_18 => FF_RX_D_1_18,\r
+ FF_RX_D_1_19 => FF_RX_D_1_19,\r
+ FF_RX_D_1_20 => FF_RX_D_1_20,\r
+ FF_RX_D_1_21 => FF_RX_D_1_21,\r
+ FF_RX_D_1_22 => FF_RX_D_1_22,\r
+ FF_RX_D_1_23 => FF_RX_D_1_23,\r
+ FF_RX_D_2_0 => FF_RX_D_2_0,\r
+ FF_RX_D_2_1 => FF_RX_D_2_1,\r
+ FF_RX_D_2_2 => FF_RX_D_2_2,\r
+ FF_RX_D_2_3 => FF_RX_D_2_3,\r
+ FF_RX_D_2_4 => FF_RX_D_2_4,\r
+ FF_RX_D_2_5 => FF_RX_D_2_5,\r
+ FF_RX_D_2_6 => FF_RX_D_2_6,\r
+ FF_RX_D_2_7 => FF_RX_D_2_7,\r
+ FF_RX_D_2_8 => FF_RX_D_2_8,\r
+ FF_RX_D_2_9 => FF_RX_D_2_9,\r
+ FF_RX_D_2_10 => FF_RX_D_2_10,\r
+ FF_RX_D_2_11 => FF_RX_D_2_11,\r
+ FF_RX_D_2_12 => FF_RX_D_2_12,\r
+ FF_RX_D_2_13 => FF_RX_D_2_13,\r
+ FF_RX_D_2_14 => FF_RX_D_2_14,\r
+ FF_RX_D_2_15 => FF_RX_D_2_15,\r
+ FF_RX_D_2_16 => FF_RX_D_2_16,\r
+ FF_RX_D_2_17 => FF_RX_D_2_17,\r
+ FF_RX_D_2_18 => FF_RX_D_2_18,\r
+ FF_RX_D_2_19 => FF_RX_D_2_19,\r
+ FF_RX_D_2_20 => FF_RX_D_2_20,\r
+ FF_RX_D_2_21 => FF_RX_D_2_21,\r
+ FF_RX_D_2_22 => FF_RX_D_2_22,\r
+ FF_RX_D_2_23 => FF_RX_D_2_23,\r
+ FF_RX_D_3_0 => FF_RX_D_3_0,\r
+ FF_RX_D_3_1 => FF_RX_D_3_1,\r
+ FF_RX_D_3_2 => FF_RX_D_3_2,\r
+ FF_RX_D_3_3 => FF_RX_D_3_3,\r
+ FF_RX_D_3_4 => FF_RX_D_3_4,\r
+ FF_RX_D_3_5 => FF_RX_D_3_5,\r
+ FF_RX_D_3_6 => FF_RX_D_3_6,\r
+ FF_RX_D_3_7 => FF_RX_D_3_7,\r
+ FF_RX_D_3_8 => FF_RX_D_3_8,\r
+ FF_RX_D_3_9 => FF_RX_D_3_9,\r
+ FF_RX_D_3_10 => FF_RX_D_3_10,\r
+ FF_RX_D_3_11 => FF_RX_D_3_11,\r
+ FF_RX_D_3_12 => FF_RX_D_3_12,\r
+ FF_RX_D_3_13 => FF_RX_D_3_13,\r
+ FF_RX_D_3_14 => FF_RX_D_3_14,\r
+ FF_RX_D_3_15 => FF_RX_D_3_15,\r
+ FF_RX_D_3_16 => FF_RX_D_3_16,\r
+ FF_RX_D_3_17 => FF_RX_D_3_17,\r
+ FF_RX_D_3_18 => FF_RX_D_3_18,\r
+ FF_RX_D_3_19 => FF_RX_D_3_19,\r
+ FF_RX_D_3_20 => FF_RX_D_3_20,\r
+ FF_RX_D_3_21 => FF_RX_D_3_21,\r
+ FF_RX_D_3_22 => FF_RX_D_3_22,\r
+ FF_RX_D_3_23 => FF_RX_D_3_23,\r
+ FF_RX_F_CLK_0 => FF_RX_F_CLK_0,\r
+ FF_RX_F_CLK_1 => FF_RX_F_CLK_1,\r
+ FF_RX_F_CLK_2 => FF_RX_F_CLK_2,\r
+ FF_RX_F_CLK_3 => FF_RX_F_CLK_3,\r
+ FF_RX_H_CLK_0 => FF_RX_H_CLK_0,\r
+ FF_RX_H_CLK_1 => FF_RX_H_CLK_1,\r
+ FF_RX_H_CLK_2 => FF_RX_H_CLK_2,\r
+ FF_RX_H_CLK_3 => FF_RX_H_CLK_3,\r
+ FF_RX_Q_CLK_0 => FF_RX_Q_CLK_0,\r
+ FF_RX_Q_CLK_1 => FF_RX_Q_CLK_1,\r
+ FF_RX_Q_CLK_2 => FF_RX_Q_CLK_2,\r
+ FF_RX_Q_CLK_3 => FF_RX_Q_CLK_3,\r
+ FF_TX_F_CLK => FF_TX_F_CLK,\r
+ FF_TX_H_CLK => FF_TX_H_CLK,\r
+ FF_TX_Q_CLK => FF_TX_Q_CLK,\r
+ FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,\r
+ FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,\r
+ FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,\r
+ FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,\r
+ FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,\r
+ FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,\r
+ FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,\r
+ FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,\r
+ FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,\r
+ FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,\r
+ FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,\r
+ FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,\r
+ FFS_PCIE_CON_0 => FFS_PCIE_CON_0,\r
+ FFS_PCIE_CON_1 => FFS_PCIE_CON_1,\r
+ FFS_PCIE_CON_2 => FFS_PCIE_CON_2,\r
+ FFS_PCIE_CON_3 => FFS_PCIE_CON_3,\r
+ FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,\r
+ FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,\r
+ FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,\r
+ FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,\r
+ FFS_RLOS_LO_0 => FFS_RLOS_LO_0,\r
+ FFS_RLOS_LO_1 => FFS_RLOS_LO_1,\r
+ FFS_RLOS_LO_2 => FFS_RLOS_LO_2,\r
+ FFS_RLOS_LO_3 => FFS_RLOS_LO_3,\r
+ FFS_PLOL => FFS_PLOL,\r
+ FFS_RLOL_0 => FFS_RLOL_0,\r
+ FFS_RLOL_1 => FFS_RLOL_1,\r
+ FFS_RLOL_2 => FFS_RLOL_2,\r
+ FFS_RLOL_3 => FFS_RLOL_3,\r
+ FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,\r
+ FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,\r
+ FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,\r
+ FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,\r
+ FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,\r
+ FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,\r
+ FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,\r
+ FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,\r
+ OOB_OUT_0 => OOB_OUT_0,\r
+ OOB_OUT_1 => OOB_OUT_1,\r
+ OOB_OUT_2 => OOB_OUT_2,\r
+ OOB_OUT_3 => OOB_OUT_3,\r
+ REFCK2CORE => REFCK2CORE,\r
+ SCIINT => SCIINT,\r
+ SCIRDATA0 => SCIRDATA0,\r
+ SCIRDATA1 => SCIRDATA1,\r
+ SCIRDATA2 => SCIRDATA2,\r
+ SCIRDATA3 => SCIRDATA3,\r
+ SCIRDATA4 => SCIRDATA4,\r
+ SCIRDATA5 => SCIRDATA5,\r
+ SCIRDATA6 => SCIRDATA6,\r
+ SCIRDATA7 => SCIRDATA7\r
+ );\r
+\r
+end PCSC_arch;\r
+\r
+--synopsys translate_on\r
+\r
+--synopsys translate_off\r
+library ECP2;\r
+use ECP2.components.all;\r
+--synopsys translate_on\r
+\r
+library IEEE, STD;\r
+use IEEE.std_logic_1164.all;\r
+use STD.TEXTIO.all;\r
+\r
+entity serdes_gbe_0_extclock_8b is\r
+ GENERIC (USER_CONFIG_FILE : String := "serdes_gbe_0_extclock_8b.txt");\r
+ port (\r
+ refclkp, refclkn : in std_logic;\r
+ hdinp0, hdinn0 : in std_logic;\r
+ hdoutp0, hdoutn0 : out std_logic;\r
+ ff_rxiclk_ch0, ff_txiclk_ch0, ff_ebrd_clk_0 : in std_logic;\r
+ ff_txdata_ch0 : in std_logic_vector (7 downto 0);\r
+ ff_rxdata_ch0 : out std_logic_vector (7 downto 0);\r
+ ff_tx_k_cntrl_ch0 : in std_logic;\r
+ ff_rx_k_cntrl_ch0 : out std_logic;\r
+ ff_rxfullclk_ch0 : out std_logic;\r
+ ff_xmit_ch0 : in std_logic;\r
+ ff_correct_disp_ch0 : in std_logic;\r
+ ff_disp_err_ch0, ff_cv_ch0 : out std_logic;\r
+ ff_rx_even_ch0 : out std_logic;\r
+ ffc_rrst_ch0 : in std_logic;\r
+ ffc_lane_tx_rst_ch0 : in std_logic;\r
+ ffc_lane_rx_rst_ch0 : in std_logic;\r
+ ffc_txpwdnb_ch0 : in std_logic;\r
+ ffc_rxpwdnb_ch0 : in std_logic;\r
+ ffs_rlos_lo_ch0 : out std_logic;\r
+ ffs_ls_sync_status_ch0 : out std_logic;\r
+ ffs_rlol_ch0 : out std_logic;\r
+ oob_out_ch0 : out std_logic;\r
+ ffc_macro_rst : in std_logic;\r
+ ffc_quad_rst : in std_logic;\r
+ ffc_trst : in std_logic;\r
+ ff_txfullclk : out std_logic;\r
+ ff_txhalfclk : out std_logic;\r
+ refck2core : out std_logic;\r
+ ffs_plol : out std_logic);\r
+\r
+end serdes_gbe_0_extclock_8b;\r
+\r
+architecture serdes_gbe_0_extclock_8b_arch of serdes_gbe_0_extclock_8b is\r
+\r
+component VLO\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+\r
+component VHI\r
+port (\r
+ Z : out std_logic);\r
+end component;\r
+component PCSC\r
+--synopsys translate_off\r
+GENERIC(\r
+ CONFIG_FILE : String\r
+ );\r
+--synopsys translate_on\r
+port (\r
+ HDINN0 : in std_logic;\r
+ HDINN1 : in std_logic;\r
+ HDINN2 : in std_logic;\r
+ HDINN3 : in std_logic;\r
+ HDINP0 : in std_logic;\r
+ HDINP1 : in std_logic;\r
+ HDINP2 : in std_logic;\r
+ HDINP3 : in std_logic;\r
+ REFCLKN : in std_logic;\r
+ REFCLKP : in std_logic;\r
+ CIN0 : in std_logic;\r
+ CIN1 : in std_logic;\r
+ CIN2 : in std_logic;\r
+ CIN3 : in std_logic;\r
+ CIN4 : in std_logic;\r
+ CIN5 : in std_logic;\r
+ CIN6 : in std_logic;\r
+ CIN7 : in std_logic;\r
+ CIN8 : in std_logic;\r
+ CIN9 : in std_logic;\r
+ CIN10 : in std_logic;\r
+ CIN11 : in std_logic;\r
+ CYAWSTN : in std_logic;\r
+ FF_EBRD_CLK_0 : in std_logic;\r
+ FF_EBRD_CLK_1 : in std_logic;\r
+ FF_EBRD_CLK_2 : in std_logic;\r
+ FF_EBRD_CLK_3 : in std_logic;\r
+ FF_RXI_CLK_0 : in std_logic;\r
+ FF_RXI_CLK_1 : in std_logic;\r
+ FF_RXI_CLK_2 : in std_logic;\r
+ FF_RXI_CLK_3 : in std_logic;\r
+ FF_TX_D_0_0 : in std_logic;\r
+ FF_TX_D_0_1 : in std_logic;\r
+ FF_TX_D_0_2 : in std_logic;\r
+ FF_TX_D_0_3 : in std_logic;\r
+ FF_TX_D_0_4 : in std_logic;\r
+ FF_TX_D_0_5 : in std_logic;\r
+ FF_TX_D_0_6 : in std_logic;\r
+ FF_TX_D_0_7 : in std_logic;\r
+ FF_TX_D_0_8 : in std_logic;\r
+ FF_TX_D_0_9 : in std_logic;\r
+ FF_TX_D_0_10 : in std_logic;\r
+ FF_TX_D_0_11 : in std_logic;\r
+ FF_TX_D_0_12 : in std_logic;\r
+ FF_TX_D_0_13 : in std_logic;\r
+ FF_TX_D_0_14 : in std_logic;\r
+ FF_TX_D_0_15 : in std_logic;\r
+ FF_TX_D_0_16 : in std_logic;\r
+ FF_TX_D_0_17 : in std_logic;\r
+ FF_TX_D_0_18 : in std_logic;\r
+ FF_TX_D_0_19 : in std_logic;\r
+ FF_TX_D_0_20 : in std_logic;\r
+ FF_TX_D_0_21 : in std_logic;\r
+ FF_TX_D_0_22 : in std_logic;\r
+ FF_TX_D_0_23 : in std_logic;\r
+ FF_TX_D_1_0 : in std_logic;\r
+ FF_TX_D_1_1 : in std_logic;\r
+ FF_TX_D_1_2 : in std_logic;\r
+ FF_TX_D_1_3 : in std_logic;\r
+ FF_TX_D_1_4 : in std_logic;\r
+ FF_TX_D_1_5 : in std_logic;\r
+ FF_TX_D_1_6 : in std_logic;\r
+ FF_TX_D_1_7 : in std_logic;\r
+ FF_TX_D_1_8 : in std_logic;\r
+ FF_TX_D_1_9 : in std_logic;\r
+ FF_TX_D_1_10 : in std_logic;\r
+ FF_TX_D_1_11 : in std_logic;\r
+ FF_TX_D_1_12 : in std_logic;\r
+ FF_TX_D_1_13 : in std_logic;\r
+ FF_TX_D_1_14 : in std_logic;\r
+ FF_TX_D_1_15 : in std_logic;\r
+ FF_TX_D_1_16 : in std_logic;\r
+ FF_TX_D_1_17 : in std_logic;\r
+ FF_TX_D_1_18 : in std_logic;\r
+ FF_TX_D_1_19 : in std_logic;\r
+ FF_TX_D_1_20 : in std_logic;\r
+ FF_TX_D_1_21 : in std_logic;\r
+ FF_TX_D_1_22 : in std_logic;\r
+ FF_TX_D_1_23 : in std_logic;\r
+ FF_TX_D_2_0 : in std_logic;\r
+ FF_TX_D_2_1 : in std_logic;\r
+ FF_TX_D_2_2 : in std_logic;\r
+ FF_TX_D_2_3 : in std_logic;\r
+ FF_TX_D_2_4 : in std_logic;\r
+ FF_TX_D_2_5 : in std_logic;\r
+ FF_TX_D_2_6 : in std_logic;\r
+ FF_TX_D_2_7 : in std_logic;\r
+ FF_TX_D_2_8 : in std_logic;\r
+ FF_TX_D_2_9 : in std_logic;\r
+ FF_TX_D_2_10 : in std_logic;\r
+ FF_TX_D_2_11 : in std_logic;\r
+ FF_TX_D_2_12 : in std_logic;\r
+ FF_TX_D_2_13 : in std_logic;\r
+ FF_TX_D_2_14 : in std_logic;\r
+ FF_TX_D_2_15 : in std_logic;\r
+ FF_TX_D_2_16 : in std_logic;\r
+ FF_TX_D_2_17 : in std_logic;\r
+ FF_TX_D_2_18 : in std_logic;\r
+ FF_TX_D_2_19 : in std_logic;\r
+ FF_TX_D_2_20 : in std_logic;\r
+ FF_TX_D_2_21 : in std_logic;\r
+ FF_TX_D_2_22 : in std_logic;\r
+ FF_TX_D_2_23 : in std_logic;\r
+ FF_TX_D_3_0 : in std_logic;\r
+ FF_TX_D_3_1 : in std_logic;\r
+ FF_TX_D_3_2 : in std_logic;\r
+ FF_TX_D_3_3 : in std_logic;\r
+ FF_TX_D_3_4 : in std_logic;\r
+ FF_TX_D_3_5 : in std_logic;\r
+ FF_TX_D_3_6 : in std_logic;\r
+ FF_TX_D_3_7 : in std_logic;\r
+ FF_TX_D_3_8 : in std_logic;\r
+ FF_TX_D_3_9 : in std_logic;\r
+ FF_TX_D_3_10 : in std_logic;\r
+ FF_TX_D_3_11 : in std_logic;\r
+ FF_TX_D_3_12 : in std_logic;\r
+ FF_TX_D_3_13 : in std_logic;\r
+ FF_TX_D_3_14 : in std_logic;\r
+ FF_TX_D_3_15 : in std_logic;\r
+ FF_TX_D_3_16 : in std_logic;\r
+ FF_TX_D_3_17 : in std_logic;\r
+ FF_TX_D_3_18 : in std_logic;\r
+ FF_TX_D_3_19 : in std_logic;\r
+ FF_TX_D_3_20 : in std_logic;\r
+ FF_TX_D_3_21 : in std_logic;\r
+ FF_TX_D_3_22 : in std_logic;\r
+ FF_TX_D_3_23 : in std_logic;\r
+ FF_TXI_CLK_0 : in std_logic;\r
+ FF_TXI_CLK_1 : in std_logic;\r
+ FF_TXI_CLK_2 : in std_logic;\r
+ FF_TXI_CLK_3 : in std_logic;\r
+ FFC_CK_CORE_RX : in std_logic;\r
+ FFC_CK_CORE_TX : in std_logic;\r
+ FFC_EI_EN_0 : in std_logic;\r
+ FFC_EI_EN_1 : in std_logic;\r
+ FFC_EI_EN_2 : in std_logic;\r
+ FFC_EI_EN_3 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_0 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_1 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_2 : in std_logic;\r
+ FFC_ENABLE_CGALIGN_3 : in std_logic;\r
+ FFC_FB_LOOPBACK_0 : in std_logic;\r
+ FFC_FB_LOOPBACK_1 : in std_logic;\r
+ FFC_FB_LOOPBACK_2 : in std_logic;\r
+ FFC_FB_LOOPBACK_3 : in std_logic;\r
+ FFC_LANE_RX_RST_0 : in std_logic;\r
+ FFC_LANE_RX_RST_1 : in std_logic;\r
+ FFC_LANE_RX_RST_2 : in std_logic;\r
+ FFC_LANE_RX_RST_3 : in std_logic;\r
+ FFC_LANE_TX_RST_0 : in std_logic;\r
+ FFC_LANE_TX_RST_1 : in std_logic;\r
+ FFC_LANE_TX_RST_2 : in std_logic;\r
+ FFC_LANE_TX_RST_3 : in std_logic;\r
+ FFC_MACRO_RST : in std_logic;\r
+ FFC_PCI_DET_EN_0 : in std_logic;\r
+ FFC_PCI_DET_EN_1 : in std_logic;\r
+ FFC_PCI_DET_EN_2 : in std_logic;\r
+ FFC_PCI_DET_EN_3 : in std_logic;\r
+ FFC_PCIE_CT_0 : in std_logic;\r
+ FFC_PCIE_CT_1 : in std_logic;\r
+ FFC_PCIE_CT_2 : in std_logic;\r
+ FFC_PCIE_CT_3 : in std_logic;\r
+ FFC_PFIFO_CLR_0 : in std_logic;\r
+ FFC_PFIFO_CLR_1 : in std_logic;\r
+ FFC_PFIFO_CLR_2 : in std_logic;\r
+ FFC_PFIFO_CLR_3 : in std_logic;\r
+ FFC_QUAD_RST : in std_logic;\r
+ FFC_RRST_0 : in std_logic;\r
+ FFC_RRST_1 : in std_logic;\r
+ FFC_RRST_2 : in std_logic;\r
+ FFC_RRST_3 : in std_logic;\r
+ FFC_RXPWDNB_0 : in std_logic;\r
+ FFC_RXPWDNB_1 : in std_logic;\r
+ FFC_RXPWDNB_2 : in std_logic;\r
+ FFC_RXPWDNB_3 : in std_logic;\r
+ FFC_SB_INV_RX_0 : in std_logic;\r
+ FFC_SB_INV_RX_1 : in std_logic;\r
+ FFC_SB_INV_RX_2 : in std_logic;\r
+ FFC_SB_INV_RX_3 : in std_logic;\r
+ FFC_SB_PFIFO_LP_0 : in std_logic;\r
+ FFC_SB_PFIFO_LP_1 : in std_logic;\r
+ FFC_SB_PFIFO_LP_2 : in std_logic;\r
+ FFC_SB_PFIFO_LP_3 : in std_logic;\r
+ FFC_SIGNAL_DETECT_0 : in std_logic;\r
+ FFC_SIGNAL_DETECT_1 : in std_logic;\r
+ FFC_SIGNAL_DETECT_2 : in std_logic;\r
+ FFC_SIGNAL_DETECT_3 : in std_logic;\r
+ FFC_TRST : in std_logic;\r
+ FFC_TXPWDNB_0 : in std_logic;\r
+ FFC_TXPWDNB_1 : in std_logic;\r
+ FFC_TXPWDNB_2 : in std_logic;\r
+ FFC_TXPWDNB_3 : in std_logic;\r
+ SCIADDR0 : in std_logic;\r
+ SCIADDR1 : in std_logic;\r
+ SCIADDR2 : in std_logic;\r
+ SCIADDR3 : in std_logic;\r
+ SCIADDR4 : in std_logic;\r
+ SCIADDR5 : in std_logic;\r
+ SCIENAUX : in std_logic;\r
+ SCIENCH0 : in std_logic;\r
+ SCIENCH1 : in std_logic;\r
+ SCIENCH2 : in std_logic;\r
+ SCIENCH3 : in std_logic;\r
+ SCIRD : in std_logic;\r
+ SCISELAUX : in std_logic;\r
+ SCISELCH0 : in std_logic;\r
+ SCISELCH1 : in std_logic;\r
+ SCISELCH2 : in std_logic;\r
+ SCISELCH3 : in std_logic;\r
+ SCIWDATA0 : in std_logic;\r
+ SCIWDATA1 : in std_logic;\r
+ SCIWDATA2 : in std_logic;\r
+ SCIWDATA3 : in std_logic;\r
+ SCIWDATA4 : in std_logic;\r
+ SCIWDATA5 : in std_logic;\r
+ SCIWDATA6 : in std_logic;\r
+ SCIWDATA7 : in std_logic;\r
+ SCIWSTN : in std_logic;\r
+ HDOUTN0 : out std_logic;\r
+ HDOUTN1 : out std_logic;\r
+ HDOUTN2 : out std_logic;\r
+ HDOUTN3 : out std_logic;\r
+ HDOUTP0 : out std_logic;\r
+ HDOUTP1 : out std_logic;\r
+ HDOUTP2 : out std_logic;\r
+ HDOUTP3 : out std_logic;\r
+ COUT0 : out std_logic;\r
+ COUT1 : out std_logic;\r
+ COUT2 : out std_logic;\r
+ COUT3 : out std_logic;\r
+ COUT4 : out std_logic;\r
+ COUT5 : out std_logic;\r
+ COUT6 : out std_logic;\r
+ COUT7 : out std_logic;\r
+ COUT8 : out std_logic;\r
+ COUT9 : out std_logic;\r
+ COUT10 : out std_logic;\r
+ COUT11 : out std_logic;\r
+ COUT12 : out std_logic;\r
+ COUT13 : out std_logic;\r
+ COUT14 : out std_logic;\r
+ COUT15 : out std_logic;\r
+ COUT16 : out std_logic;\r
+ COUT17 : out std_logic;\r
+ COUT18 : out std_logic;\r
+ COUT19 : out std_logic;\r
+ FF_RX_D_0_0 : out std_logic;\r
+ FF_RX_D_0_1 : out std_logic;\r
+ FF_RX_D_0_2 : out std_logic;\r
+ FF_RX_D_0_3 : out std_logic;\r
+ FF_RX_D_0_4 : out std_logic;\r
+ FF_RX_D_0_5 : out std_logic;\r
+ FF_RX_D_0_6 : out std_logic;\r
+ FF_RX_D_0_7 : out std_logic;\r
+ FF_RX_D_0_8 : out std_logic;\r
+ FF_RX_D_0_9 : out std_logic;\r
+ FF_RX_D_0_10 : out std_logic;\r
+ FF_RX_D_0_11 : out std_logic;\r
+ FF_RX_D_0_12 : out std_logic;\r
+ FF_RX_D_0_13 : out std_logic;\r
+ FF_RX_D_0_14 : out std_logic;\r
+ FF_RX_D_0_15 : out std_logic;\r
+ FF_RX_D_0_16 : out std_logic;\r
+ FF_RX_D_0_17 : out std_logic;\r
+ FF_RX_D_0_18 : out std_logic;\r
+ FF_RX_D_0_19 : out std_logic;\r
+ FF_RX_D_0_20 : out std_logic;\r
+ FF_RX_D_0_21 : out std_logic;\r
+ FF_RX_D_0_22 : out std_logic;\r
+ FF_RX_D_0_23 : out std_logic;\r
+ FF_RX_D_1_0 : out std_logic;\r
+ FF_RX_D_1_1 : out std_logic;\r
+ FF_RX_D_1_2 : out std_logic;\r
+ FF_RX_D_1_3 : out std_logic;\r
+ FF_RX_D_1_4 : out std_logic;\r
+ FF_RX_D_1_5 : out std_logic;\r
+ FF_RX_D_1_6 : out std_logic;\r
+ FF_RX_D_1_7 : out std_logic;\r
+ FF_RX_D_1_8 : out std_logic;\r
+ FF_RX_D_1_9 : out std_logic;\r
+ FF_RX_D_1_10 : out std_logic;\r
+ FF_RX_D_1_11 : out std_logic;\r
+ FF_RX_D_1_12 : out std_logic;\r
+ FF_RX_D_1_13 : out std_logic;\r
+ FF_RX_D_1_14 : out std_logic;\r
+ FF_RX_D_1_15 : out std_logic;\r
+ FF_RX_D_1_16 : out std_logic;\r
+ FF_RX_D_1_17 : out std_logic;\r
+ FF_RX_D_1_18 : out std_logic;\r
+ FF_RX_D_1_19 : out std_logic;\r
+ FF_RX_D_1_20 : out std_logic;\r
+ FF_RX_D_1_21 : out std_logic;\r
+ FF_RX_D_1_22 : out std_logic;\r
+ FF_RX_D_1_23 : out std_logic;\r
+ FF_RX_D_2_0 : out std_logic;\r
+ FF_RX_D_2_1 : out std_logic;\r
+ FF_RX_D_2_2 : out std_logic;\r
+ FF_RX_D_2_3 : out std_logic;\r
+ FF_RX_D_2_4 : out std_logic;\r
+ FF_RX_D_2_5 : out std_logic;\r
+ FF_RX_D_2_6 : out std_logic;\r
+ FF_RX_D_2_7 : out std_logic;\r
+ FF_RX_D_2_8 : out std_logic;\r
+ FF_RX_D_2_9 : out std_logic;\r
+ FF_RX_D_2_10 : out std_logic;\r
+ FF_RX_D_2_11 : out std_logic;\r
+ FF_RX_D_2_12 : out std_logic;\r
+ FF_RX_D_2_13 : out std_logic;\r
+ FF_RX_D_2_14 : out std_logic;\r
+ FF_RX_D_2_15 : out std_logic;\r
+ FF_RX_D_2_16 : out std_logic;\r
+ FF_RX_D_2_17 : out std_logic;\r
+ FF_RX_D_2_18 : out std_logic;\r
+ FF_RX_D_2_19 : out std_logic;\r
+ FF_RX_D_2_20 : out std_logic;\r
+ FF_RX_D_2_21 : out std_logic;\r
+ FF_RX_D_2_22 : out std_logic;\r
+ FF_RX_D_2_23 : out std_logic;\r
+ FF_RX_D_3_0 : out std_logic;\r
+ FF_RX_D_3_1 : out std_logic;\r
+ FF_RX_D_3_2 : out std_logic;\r
+ FF_RX_D_3_3 : out std_logic;\r
+ FF_RX_D_3_4 : out std_logic;\r
+ FF_RX_D_3_5 : out std_logic;\r
+ FF_RX_D_3_6 : out std_logic;\r
+ FF_RX_D_3_7 : out std_logic;\r
+ FF_RX_D_3_8 : out std_logic;\r
+ FF_RX_D_3_9 : out std_logic;\r
+ FF_RX_D_3_10 : out std_logic;\r
+ FF_RX_D_3_11 : out std_logic;\r
+ FF_RX_D_3_12 : out std_logic;\r
+ FF_RX_D_3_13 : out std_logic;\r
+ FF_RX_D_3_14 : out std_logic;\r
+ FF_RX_D_3_15 : out std_logic;\r
+ FF_RX_D_3_16 : out std_logic;\r
+ FF_RX_D_3_17 : out std_logic;\r
+ FF_RX_D_3_18 : out std_logic;\r
+ FF_RX_D_3_19 : out std_logic;\r
+ FF_RX_D_3_20 : out std_logic;\r
+ FF_RX_D_3_21 : out std_logic;\r
+ FF_RX_D_3_22 : out std_logic;\r
+ FF_RX_D_3_23 : out std_logic;\r
+ FF_RX_F_CLK_0 : out std_logic;\r
+ FF_RX_F_CLK_1 : out std_logic;\r
+ FF_RX_F_CLK_2 : out std_logic;\r
+ FF_RX_F_CLK_3 : out std_logic;\r
+ FF_RX_H_CLK_0 : out std_logic;\r
+ FF_RX_H_CLK_1 : out std_logic;\r
+ FF_RX_H_CLK_2 : out std_logic;\r
+ FF_RX_H_CLK_3 : out std_logic;\r
+ FF_RX_Q_CLK_0 : out std_logic;\r
+ FF_RX_Q_CLK_1 : out std_logic;\r
+ FF_RX_Q_CLK_2 : out std_logic;\r
+ FF_RX_Q_CLK_3 : out std_logic;\r
+ FF_TX_F_CLK : out std_logic;\r
+ FF_TX_H_CLK : out std_logic;\r
+ FF_TX_Q_CLK : out std_logic;\r
+ FFS_CC_OVERRUN_0 : out std_logic;\r
+ FFS_CC_OVERRUN_1 : out std_logic;\r
+ FFS_CC_OVERRUN_2 : out std_logic;\r
+ FFS_CC_OVERRUN_3 : out std_logic;\r
+ FFS_CC_UNDERRUN_0 : out std_logic;\r
+ FFS_CC_UNDERRUN_1 : out std_logic;\r
+ FFS_CC_UNDERRUN_2 : out std_logic;\r
+ FFS_CC_UNDERRUN_3 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_0 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_1 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_2 : out std_logic;\r
+ FFS_LS_SYNC_STATUS_3 : out std_logic;\r
+ FFS_PCIE_CON_0 : out std_logic;\r
+ FFS_PCIE_CON_1 : out std_logic;\r
+ FFS_PCIE_CON_2 : out std_logic;\r
+ FFS_PCIE_CON_3 : out std_logic;\r
+ FFS_PCIE_DONE_0 : out std_logic;\r
+ FFS_PCIE_DONE_1 : out std_logic;\r
+ FFS_PCIE_DONE_2 : out std_logic;\r
+ FFS_PCIE_DONE_3 : out std_logic;\r
+ FFS_RLOS_LO_0 : out std_logic;\r
+ FFS_RLOS_LO_1 : out std_logic;\r
+ FFS_RLOS_LO_2 : out std_logic;\r
+ FFS_RLOS_LO_3 : out std_logic;\r
+ OOB_OUT_0 : out std_logic;\r
+ OOB_OUT_1 : out std_logic;\r
+ OOB_OUT_2 : out std_logic;\r
+ OOB_OUT_3 : out std_logic;\r
+ REFCK2CORE : out std_logic;\r
+ SCIINT : out std_logic;\r
+ SCIRDATA0 : out std_logic;\r
+ SCIRDATA1 : out std_logic;\r
+ SCIRDATA2 : out std_logic;\r
+ SCIRDATA3 : out std_logic;\r
+ SCIRDATA4 : out std_logic;\r
+ SCIRDATA5 : out std_logic;\r
+ SCIRDATA6 : out std_logic;\r
+ SCIRDATA7 : out std_logic;\r
+ FFS_PLOL : out std_logic;\r
+ FFS_RLOL_0 : out std_logic;\r
+ FFS_RLOL_1 : out std_logic;\r
+ FFS_RLOL_2 : out std_logic;\r
+ FFS_RLOL_3 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_RXFBFIFO_ERROR_3 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_0 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_1 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_2 : out std_logic;\r
+ FFS_TXFBFIFO_ERROR_3 : out std_logic\r
+);\r
+end component;\r
+ attribute IS_ASB: string;\r
+ attribute IS_ASB of PCSC_INST : label is "ep5m00/data/ep5m00.acd";\r
+ attribute CONFIG_FILE: string;\r
+ attribute CONFIG_FILE of PCSC_INST : label is USER_CONFIG_FILE;\r
+ attribute black_box_pad_pin: string;\r
+ attribute black_box_pad_pin of PCSC : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";\r
+\r
+signal fpsc_vlo : std_logic := '0';\r
+signal cin : std_logic_vector (11 downto 0) := "000000000000";\r
+signal cout : std_logic_vector (19 downto 0);\r
+\r
+begin\r
+\r
+vlo_inst : VLO port map(Z => fpsc_vlo);\r
+\r
+-- pcs_quad instance\r
+PCSC_INST : PCSC\r
+--synopsys translate_off\r
+ generic map (CONFIG_FILE => USER_CONFIG_FILE)\r
+--synopsys translate_on\r
+port map (\r
+ FFC_CK_CORE_TX => fpsc_vlo,\r
+ FFC_CK_CORE_RX => fpsc_vlo,\r
+ REFCLKP => refclkp,\r
+ REFCLKN => refclkn,\r
+ HDINP0 => hdinp0,\r
+ HDINN0 => hdinn0,\r
+ HDOUTP0 => hdoutp0,\r
+ HDOUTN0 => hdoutn0,\r
+ SCISELCH0 => fpsc_vlo,\r
+ SCIENCH0 => fpsc_vlo,\r
+ FF_RXI_CLK_0 => ff_rxiclk_ch0,\r
+ FF_TXI_CLK_0 => ff_txiclk_ch0,\r
+ FF_EBRD_CLK_0 => ff_ebrd_clk_0,\r
+ FF_RX_F_CLK_0 => ff_rxfullclk_ch0,\r
+ FF_RX_H_CLK_0 => open,\r
+ FF_RX_Q_CLK_0 => open,\r
+ FF_TX_D_0_0 => ff_txdata_ch0(0),\r
+ FF_TX_D_0_1 => ff_txdata_ch0(1),\r
+ FF_TX_D_0_2 => ff_txdata_ch0(2),\r
+ FF_TX_D_0_3 => ff_txdata_ch0(3),\r
+ FF_TX_D_0_4 => ff_txdata_ch0(4),\r
+ FF_TX_D_0_5 => ff_txdata_ch0(5),\r
+ FF_TX_D_0_6 => ff_txdata_ch0(6),\r
+ FF_TX_D_0_7 => ff_txdata_ch0(7),\r
+ FF_TX_D_0_8 => ff_tx_k_cntrl_ch0,\r
+ FF_TX_D_0_9 => fpsc_vlo,\r
+ FF_TX_D_0_10 => ff_xmit_ch0,\r
+ FF_TX_D_0_11 => ff_correct_disp_ch0,\r
+ FF_TX_D_0_12 => fpsc_vlo,\r
+ FF_TX_D_0_13 => fpsc_vlo,\r
+ FF_TX_D_0_14 => fpsc_vlo,\r
+ FF_TX_D_0_15 => fpsc_vlo,\r
+ FF_TX_D_0_16 => fpsc_vlo,\r
+ FF_TX_D_0_17 => fpsc_vlo,\r
+ FF_TX_D_0_18 => fpsc_vlo,\r
+ FF_TX_D_0_19 => fpsc_vlo,\r
+ FF_TX_D_0_20 => fpsc_vlo,\r
+ FF_TX_D_0_21 => fpsc_vlo,\r
+ FF_TX_D_0_22 => fpsc_vlo,\r
+ FF_TX_D_0_23 => fpsc_vlo,\r
+ FF_RX_D_0_0 => ff_rxdata_ch0(0),\r
+ FF_RX_D_0_1 => ff_rxdata_ch0(1),\r
+ FF_RX_D_0_2 => ff_rxdata_ch0(2),\r
+ FF_RX_D_0_3 => ff_rxdata_ch0(3),\r
+ FF_RX_D_0_4 => ff_rxdata_ch0(4),\r
+ FF_RX_D_0_5 => ff_rxdata_ch0(5),\r
+ FF_RX_D_0_6 => ff_rxdata_ch0(6),\r
+ FF_RX_D_0_7 => ff_rxdata_ch0(7),\r
+ FF_RX_D_0_8 => ff_rx_k_cntrl_ch0,\r
+ FF_RX_D_0_9 => ff_disp_err_ch0,\r
+ FF_RX_D_0_10 => ff_cv_ch0,\r
+ FF_RX_D_0_11 => ff_rx_even_ch0,\r
+ FF_RX_D_0_12 => open,\r
+ FF_RX_D_0_13 => open,\r
+ FF_RX_D_0_14 => open,\r
+ FF_RX_D_0_15 => open,\r
+ FF_RX_D_0_16 => open,\r
+ FF_RX_D_0_17 => open,\r
+ FF_RX_D_0_18 => open,\r
+ FF_RX_D_0_19 => open,\r
+ FF_RX_D_0_20 => open,\r
+ FF_RX_D_0_21 => open,\r
+ FF_RX_D_0_22 => open,\r
+ FF_RX_D_0_23 => open,\r
+ FFC_RRST_0 => ffc_rrst_ch0,\r
+ FFC_SIGNAL_DETECT_0 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_0 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_0 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_0 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_0 => fpsc_vlo,\r
+ FFC_SB_INV_RX_0 => fpsc_vlo,\r
+ FFC_PCIE_CT_0 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_0 => fpsc_vlo,\r
+ FFS_PCIE_DONE_0 => open,\r
+ FFS_PCIE_CON_0 => open,\r
+ FFC_EI_EN_0 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_0 => ffc_lane_tx_rst_ch0,\r
+ FFC_LANE_RX_RST_0 => ffc_lane_rx_rst_ch0,\r
+ FFC_TXPWDNB_0 => ffc_txpwdnb_ch0,\r
+ FFC_RXPWDNB_0 => ffc_rxpwdnb_ch0,\r
+ FFS_RLOS_LO_0 => ffs_rlos_lo_ch0,\r
+ FFS_LS_SYNC_STATUS_0 => ffs_ls_sync_status_ch0,\r
+ FFS_CC_UNDERRUN_0 => open,\r
+ FFS_CC_OVERRUN_0 => open,\r
+ FFS_RXFBFIFO_ERROR_0 => open,\r
+ FFS_TXFBFIFO_ERROR_0 => open,\r
+ FFS_RLOL_0 => ffs_rlol_ch0,\r
+ OOB_OUT_0 => oob_out_ch0,\r
+ HDINP1 => fpsc_vlo,\r
+ HDINN1 => fpsc_vlo,\r
+ HDOUTP1 => open,\r
+ HDOUTN1 => open,\r
+ SCISELCH1 => fpsc_vlo,\r
+ SCIENCH1 => fpsc_vlo,\r
+ FF_RXI_CLK_1 => fpsc_vlo,\r
+ FF_TXI_CLK_1 => fpsc_vlo,\r
+ FF_EBRD_CLK_1 => fpsc_vlo,\r
+ FF_RX_F_CLK_1 => open,\r
+ FF_RX_H_CLK_1 => open,\r
+ FF_RX_Q_CLK_1 => open,\r
+ FF_TX_D_1_0 => fpsc_vlo,\r
+ FF_TX_D_1_1 => fpsc_vlo,\r
+ FF_TX_D_1_2 => fpsc_vlo,\r
+ FF_TX_D_1_3 => fpsc_vlo,\r
+ FF_TX_D_1_4 => fpsc_vlo,\r
+ FF_TX_D_1_5 => fpsc_vlo,\r
+ FF_TX_D_1_6 => fpsc_vlo,\r
+ FF_TX_D_1_7 => fpsc_vlo,\r
+ FF_TX_D_1_8 => fpsc_vlo,\r
+ FF_TX_D_1_9 => fpsc_vlo,\r
+ FF_TX_D_1_10 => fpsc_vlo,\r
+ FF_TX_D_1_11 => fpsc_vlo,\r
+ FF_TX_D_1_12 => fpsc_vlo,\r
+ FF_TX_D_1_13 => fpsc_vlo,\r
+ FF_TX_D_1_14 => fpsc_vlo,\r
+ FF_TX_D_1_15 => fpsc_vlo,\r
+ FF_TX_D_1_16 => fpsc_vlo,\r
+ FF_TX_D_1_17 => fpsc_vlo,\r
+ FF_TX_D_1_18 => fpsc_vlo,\r
+ FF_TX_D_1_19 => fpsc_vlo,\r
+ FF_TX_D_1_20 => fpsc_vlo,\r
+ FF_TX_D_1_21 => fpsc_vlo,\r
+ FF_TX_D_1_22 => fpsc_vlo,\r
+ FF_TX_D_1_23 => fpsc_vlo,\r
+ FF_RX_D_1_0 => open,\r
+ FF_RX_D_1_1 => open,\r
+ FF_RX_D_1_2 => open,\r
+ FF_RX_D_1_3 => open,\r
+ FF_RX_D_1_4 => open,\r
+ FF_RX_D_1_5 => open,\r
+ FF_RX_D_1_6 => open,\r
+ FF_RX_D_1_7 => open,\r
+ FF_RX_D_1_8 => open,\r
+ FF_RX_D_1_9 => open,\r
+ FF_RX_D_1_10 => open,\r
+ FF_RX_D_1_11 => open,\r
+ FF_RX_D_1_12 => open,\r
+ FF_RX_D_1_13 => open,\r
+ FF_RX_D_1_14 => open,\r
+ FF_RX_D_1_15 => open,\r
+ FF_RX_D_1_16 => open,\r
+ FF_RX_D_1_17 => open,\r
+ FF_RX_D_1_18 => open,\r
+ FF_RX_D_1_19 => open,\r
+ FF_RX_D_1_20 => open,\r
+ FF_RX_D_1_21 => open,\r
+ FF_RX_D_1_22 => open,\r
+ FF_RX_D_1_23 => open,\r
+ FFC_RRST_1 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_1 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_1 => fpsc_vlo,\r
+ FFC_SB_INV_RX_1 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_1 => fpsc_vlo,\r
+ FFC_PCIE_CT_1 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_1 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_1 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_1 => fpsc_vlo,\r
+ FFC_EI_EN_1 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_1 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_1 => fpsc_vlo,\r
+ FFC_TXPWDNB_1 => fpsc_vlo,\r
+ FFC_RXPWDNB_1 => fpsc_vlo,\r
+ FFS_RLOS_LO_1 => open,\r
+ FFS_PCIE_DONE_1 => open,\r
+ FFS_PCIE_CON_1 => open,\r
+ FFS_LS_SYNC_STATUS_1 => open,\r
+ FFS_CC_UNDERRUN_1 => open,\r
+ FFS_CC_OVERRUN_1 => open,\r
+ FFS_RLOL_1 => open,\r
+ FFS_RXFBFIFO_ERROR_1 => open,\r
+ FFS_TXFBFIFO_ERROR_1 => open,\r
+ OOB_OUT_1 => open,\r
+ HDINP2 => fpsc_vlo,\r
+ HDINN2 => fpsc_vlo,\r
+ HDOUTP2 => open,\r
+ HDOUTN2 => open,\r
+ SCISELCH2 => fpsc_vlo,\r
+ SCIENCH2 => fpsc_vlo,\r
+ FF_RXI_CLK_2 => fpsc_vlo,\r
+ FF_TXI_CLK_2 => fpsc_vlo,\r
+ FF_EBRD_CLK_2 => fpsc_vlo,\r
+ FF_RX_F_CLK_2 => open,\r
+ FF_RX_H_CLK_2 => open,\r
+ FF_RX_Q_CLK_2 => open,\r
+ FF_TX_D_2_0 => fpsc_vlo,\r
+ FF_TX_D_2_1 => fpsc_vlo,\r
+ FF_TX_D_2_2 => fpsc_vlo,\r
+ FF_TX_D_2_3 => fpsc_vlo,\r
+ FF_TX_D_2_4 => fpsc_vlo,\r
+ FF_TX_D_2_5 => fpsc_vlo,\r
+ FF_TX_D_2_6 => fpsc_vlo,\r
+ FF_TX_D_2_7 => fpsc_vlo,\r
+ FF_TX_D_2_8 => fpsc_vlo,\r
+ FF_TX_D_2_9 => fpsc_vlo,\r
+ FF_TX_D_2_10 => fpsc_vlo,\r
+ FF_TX_D_2_11 => fpsc_vlo,\r
+ FF_TX_D_2_12 => fpsc_vlo,\r
+ FF_TX_D_2_13 => fpsc_vlo,\r
+ FF_TX_D_2_14 => fpsc_vlo,\r
+ FF_TX_D_2_15 => fpsc_vlo,\r
+ FF_TX_D_2_16 => fpsc_vlo,\r
+ FF_TX_D_2_17 => fpsc_vlo,\r
+ FF_TX_D_2_18 => fpsc_vlo,\r
+ FF_TX_D_2_19 => fpsc_vlo,\r
+ FF_TX_D_2_20 => fpsc_vlo,\r
+ FF_TX_D_2_21 => fpsc_vlo,\r
+ FF_TX_D_2_22 => fpsc_vlo,\r
+ FF_TX_D_2_23 => fpsc_vlo,\r
+ FF_RX_D_2_0 => open,\r
+ FF_RX_D_2_1 => open,\r
+ FF_RX_D_2_2 => open,\r
+ FF_RX_D_2_3 => open,\r
+ FF_RX_D_2_4 => open,\r
+ FF_RX_D_2_5 => open,\r
+ FF_RX_D_2_6 => open,\r
+ FF_RX_D_2_7 => open,\r
+ FF_RX_D_2_8 => open,\r
+ FF_RX_D_2_9 => open,\r
+ FF_RX_D_2_10 => open,\r
+ FF_RX_D_2_11 => open,\r
+ FF_RX_D_2_12 => open,\r
+ FF_RX_D_2_13 => open,\r
+ FF_RX_D_2_14 => open,\r
+ FF_RX_D_2_15 => open,\r
+ FF_RX_D_2_16 => open,\r
+ FF_RX_D_2_17 => open,\r
+ FF_RX_D_2_18 => open,\r
+ FF_RX_D_2_19 => open,\r
+ FF_RX_D_2_20 => open,\r
+ FF_RX_D_2_21 => open,\r
+ FF_RX_D_2_22 => open,\r
+ FF_RX_D_2_23 => open,\r
+ FFC_RRST_2 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_2 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_2 => fpsc_vlo,\r
+ FFC_SB_INV_RX_2 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_2 => fpsc_vlo,\r
+ FFC_PCIE_CT_2 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_2 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_2 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_2 => fpsc_vlo,\r
+ FFC_EI_EN_2 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_2 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_2 => fpsc_vlo,\r
+ FFC_TXPWDNB_2 => fpsc_vlo,\r
+ FFC_RXPWDNB_2 => fpsc_vlo,\r
+ FFS_RLOS_LO_2 => open,\r
+ FFS_PCIE_DONE_2 => open,\r
+ FFS_PCIE_CON_2 => open,\r
+ FFS_LS_SYNC_STATUS_2 => open,\r
+ FFS_CC_UNDERRUN_2 => open,\r
+ FFS_CC_OVERRUN_2 => open,\r
+ FFS_RLOL_2 => open,\r
+ FFS_RXFBFIFO_ERROR_2 => open,\r
+ FFS_TXFBFIFO_ERROR_2 => open,\r
+ OOB_OUT_2 => open,\r
+ HDINP3 => fpsc_vlo,\r
+ HDINN3 => fpsc_vlo,\r
+ HDOUTP3 => open,\r
+ HDOUTN3 => open,\r
+ SCISELCH3 => fpsc_vlo,\r
+ SCIENCH3 => fpsc_vlo,\r
+ FF_RXI_CLK_3 => fpsc_vlo,\r
+ FF_TXI_CLK_3 => fpsc_vlo,\r
+ FF_EBRD_CLK_3 => fpsc_vlo,\r
+ FF_RX_F_CLK_3 => open,\r
+ FF_RX_H_CLK_3 => open,\r
+ FF_RX_Q_CLK_3 => open,\r
+ FF_TX_D_3_0 => fpsc_vlo,\r
+ FF_TX_D_3_1 => fpsc_vlo,\r
+ FF_TX_D_3_2 => fpsc_vlo,\r
+ FF_TX_D_3_3 => fpsc_vlo,\r
+ FF_TX_D_3_4 => fpsc_vlo,\r
+ FF_TX_D_3_5 => fpsc_vlo,\r
+ FF_TX_D_3_6 => fpsc_vlo,\r
+ FF_TX_D_3_7 => fpsc_vlo,\r
+ FF_TX_D_3_8 => fpsc_vlo,\r
+ FF_TX_D_3_9 => fpsc_vlo,\r
+ FF_TX_D_3_10 => fpsc_vlo,\r
+ FF_TX_D_3_11 => fpsc_vlo,\r
+ FF_TX_D_3_12 => fpsc_vlo,\r
+ FF_TX_D_3_13 => fpsc_vlo,\r
+ FF_TX_D_3_14 => fpsc_vlo,\r
+ FF_TX_D_3_15 => fpsc_vlo,\r
+ FF_TX_D_3_16 => fpsc_vlo,\r
+ FF_TX_D_3_17 => fpsc_vlo,\r
+ FF_TX_D_3_18 => fpsc_vlo,\r
+ FF_TX_D_3_19 => fpsc_vlo,\r
+ FF_TX_D_3_20 => fpsc_vlo,\r
+ FF_TX_D_3_21 => fpsc_vlo,\r
+ FF_TX_D_3_22 => fpsc_vlo,\r
+ FF_TX_D_3_23 => fpsc_vlo,\r
+ FF_RX_D_3_0 => open,\r
+ FF_RX_D_3_1 => open,\r
+ FF_RX_D_3_2 => open,\r
+ FF_RX_D_3_3 => open,\r
+ FF_RX_D_3_4 => open,\r
+ FF_RX_D_3_5 => open,\r
+ FF_RX_D_3_6 => open,\r
+ FF_RX_D_3_7 => open,\r
+ FF_RX_D_3_8 => open,\r
+ FF_RX_D_3_9 => open,\r
+ FF_RX_D_3_10 => open,\r
+ FF_RX_D_3_11 => open,\r
+ FF_RX_D_3_12 => open,\r
+ FF_RX_D_3_13 => open,\r
+ FF_RX_D_3_14 => open,\r
+ FF_RX_D_3_15 => open,\r
+ FF_RX_D_3_16 => open,\r
+ FF_RX_D_3_17 => open,\r
+ FF_RX_D_3_18 => open,\r
+ FF_RX_D_3_19 => open,\r
+ FF_RX_D_3_20 => open,\r
+ FF_RX_D_3_21 => open,\r
+ FF_RX_D_3_22 => open,\r
+ FF_RX_D_3_23 => open,\r
+ FFC_RRST_3 => fpsc_vlo,\r
+ FFC_SIGNAL_DETECT_3 => fpsc_vlo,\r
+ FFC_SB_PFIFO_LP_3 => fpsc_vlo,\r
+ FFC_SB_INV_RX_3 => fpsc_vlo,\r
+ FFC_PFIFO_CLR_3 => fpsc_vlo,\r
+ FFC_PCIE_CT_3 => fpsc_vlo,\r
+ FFC_PCI_DET_EN_3 => fpsc_vlo,\r
+ FFC_FB_LOOPBACK_3 => fpsc_vlo,\r
+ FFC_ENABLE_CGALIGN_3 => fpsc_vlo,\r
+ FFC_EI_EN_3 => fpsc_vlo,\r
+ FFC_LANE_TX_RST_3 => fpsc_vlo,\r
+ FFC_LANE_RX_RST_3 => fpsc_vlo,\r
+ FFC_TXPWDNB_3 => fpsc_vlo,\r
+ FFC_RXPWDNB_3 => fpsc_vlo,\r
+ FFS_RLOS_LO_3 => open,\r
+ FFS_PCIE_DONE_3 => open,\r
+ FFS_PCIE_CON_3 => open,\r
+ FFS_LS_SYNC_STATUS_3 => open,\r
+ FFS_CC_UNDERRUN_3 => open,\r
+ FFS_CC_OVERRUN_3 => open,\r
+ FFS_RLOL_3 => open,\r
+ FFS_RXFBFIFO_ERROR_3 => open,\r
+ FFS_TXFBFIFO_ERROR_3 => open,\r
+ OOB_OUT_3 => open,\r
+ SCIWDATA0 => fpsc_vlo,\r
+ SCIWDATA1 => fpsc_vlo,\r
+ SCIWDATA2 => fpsc_vlo,\r
+ SCIWDATA3 => fpsc_vlo,\r
+ SCIWDATA4 => fpsc_vlo,\r
+ SCIWDATA5 => fpsc_vlo,\r
+ SCIWDATA6 => fpsc_vlo,\r
+ SCIWDATA7 => fpsc_vlo,\r
+ SCIADDR0 => fpsc_vlo,\r
+ SCIADDR1 => fpsc_vlo,\r
+ SCIADDR2 => fpsc_vlo,\r
+ SCIADDR3 => fpsc_vlo,\r
+ SCIADDR4 => fpsc_vlo,\r
+ SCIADDR5 => fpsc_vlo,\r
+ SCIRDATA0 => open,\r
+ SCIRDATA1 => open,\r
+ SCIRDATA2 => open,\r
+ SCIRDATA3 => open,\r
+ SCIRDATA4 => open,\r
+ SCIRDATA5 => open,\r
+ SCIRDATA6 => open,\r
+ SCIRDATA7 => open,\r
+ SCIENAUX => fpsc_vlo,\r
+ SCISELAUX => fpsc_vlo,\r
+ SCIRD => fpsc_vlo,\r
+ SCIWSTN => fpsc_vlo,\r
+ CYAWSTN => fpsc_vlo,\r
+ SCIINT => open,\r
+ FFC_MACRO_RST => ffc_macro_rst,\r
+ FFC_QUAD_RST => ffc_quad_rst,\r
+ FFC_TRST => ffc_trst,\r
+ FF_TX_F_CLK => ff_txfullclk,\r
+ FF_TX_H_CLK => ff_txhalfclk,\r
+ FF_TX_Q_CLK => open,\r
+ REFCK2CORE => refck2core,\r
+ CIN0 => cin(0),\r
+ CIN1 => cin(1),\r
+ CIN2 => cin(2),\r
+ CIN3 => cin(3),\r
+ CIN4 => cin(4),\r
+ CIN5 => cin(5),\r
+ CIN6 => cin(6),\r
+ CIN7 => cin(7),\r
+ CIN8 => cin(8),\r
+ CIN9 => cin(9),\r
+ CIN10 => cin(10),\r
+ CIN11 => cin(11),\r
+ COUT0 => cout(0),\r
+ COUT1 => cout(1),\r
+ COUT2 => cout(2),\r
+ COUT3 => cout(3),\r
+ COUT4 => cout(4),\r
+ COUT5 => cout(5),\r
+ COUT6 => cout(6),\r
+ COUT7 => cout(7),\r
+ COUT8 => cout(8),\r
+ COUT9 => cout(9),\r
+ COUT10 => cout(10),\r
+ COUT11 => cout(11),\r
+ COUT12 => cout(12),\r
+ COUT13 => cout(13),\r
+ COUT14 => cout(14),\r
+ COUT15 => cout(15),\r
+ COUT16 => cout(16),\r
+ COUT17 => cout(17),\r
+ COUT18 => cout(18),\r
+ COUT19 => cout(19),\r
+ FFS_PLOL => ffs_plol);\r
+\r
+--synopsys translate_off\r
+file_read : PROCESS\r
+VARIABLE open_status : file_open_status;\r
+FILE config : text;\r
+BEGIN\r
+ file_open (open_status, config, USER_CONFIG_FILE, read_mode);\r
+ IF (open_status = name_error) THEN\r
+ report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"\r
+ severity ERROR;\r
+ END IF;\r
+ wait;\r
+END PROCESS;\r
+--synopsys translate_on\r
+\r
+end serdes_gbe_0_extclock_8b_arch ;\r
jspc29 / trbnet.git / commitdiff