-w
-#-y
-l 5
-#-m nodelist.txt # Controlled by the compile.pl script.
-#-n 1 # Controlled by the compile.pl script.
-s 10
--t 11
+-t 11 # seed setting here!
-c 2
-e 2
-i 10
-#-exp parPlcInLimit=0
-#-exp parPlcInNeighborSize=1
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
#General PAR Command Line Options
-# -w With this option, any files generated will overwrite existing files
-# (e.g., any .par, .pad files).
-# -y Adds the Delay Summary Report in the .par file and creates the delay
-# file (in .dly format) at the end of the par run.
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
#
#PAR Placement Command Line Options
-# -l Specifies the effort level of the design from 1 (simplest designs)
-# to 5 (most complex designs).
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
# -m Multi-tasking option. Controlled by the compile.pl script.
-# -n Sets the number of iterations performed at the effort level
-# specified by the -l option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
# -s Save the number of best results for this run.
-# -t Start placement at the specified cost table. Default is 1.
+# -t Start placement at the specified cost table. Default is 1.
#
#PAR Routing Command Line Options
-# -c Run number of cost-based cleanup passes of the router.
-# -e Run number of delay-based cleanup passes of the router on
-# completely-routed designs only.
-# -i Run a maximum number of passes, stopping earlier only if the routing
-# goes to 100 percent completion and all constraints are met.
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
#
#PAR Explorer Command Line Options
-# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
-# compatible with all Lattice FPGA device families; however, most
-# benefit has been demonstrated with benchmarks targeted to ECP5,
-# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
-# parCDR Enable the congestion-driven router (CDR) algorithm.
-# Congestion-driven options like parCDR and parCDP can improve
-# performance given a design with multiple congestion “hotspots.” The
-# Layer > Congestion option of the Design Planner Floorplan View can
-# help visualize routing congestion. Large congested areas may prevent
-# the options from finding a successful solution.
-# CDR is compatible with all Lattice FPGA device families however most
-# benefit has been demonstrated with benchmarks targeted to ECP5,
-# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
-# paruseNBR NBR Router or Negotiation-based routing option. Supports all
-# FPGA device families except LatticeXP and MachXO.
-# When turned on, an alternate routing engine from the traditional
-# Rip-up-based routing selection (RBR) is used. This involves an
-# iterative routing algorithm that routes connections to achieve
-# minimum delay cost. It does so by computing the demand on each
-# routing resource and applying cost values per node. It will
-# complete when an optimal solution is arrived at or the number of
-# iterations is reached.
-# parPathBased Path-based placement option. Path-based timing driven
-# placement will yield better performance and more
-# predictable results in many cases.
-# parHold Additional hold time correction option. This option
-# forces the router to automatically insert extra wires to compensate for the
-# hold time violation.
-# parHoldLimit This option allows you to set a limit on the number of
-# hold time violations to be processed by the auto hold time correction option
-# parHold.
-# parPlcInLimit Cannot find in the online help
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
# parPlcInNeighborSize Cannot find in the online help
--exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
+
ADC_NCS : out std_logic;
ADC_MOSI : out std_logic;
ADC_MISO : in std_logic;
+
--Flash, Reload
FLASH_SCLK : out std_logic;
FLASH_NCS : out std_logic;
FLASH_HOLD : out std_logic;
FLASH_WP : out std_logic;
PROGRAMN : out std_logic;
+
--I2C
I2C_SDA : inout std_logic;
I2C_SCL : inout std_logic;
--Other Connectors
TEST : inout std_logic_vector(14 downto 1);
HDR_IO : inout std_logic_vector(15 downto 0)
- );
+ );
- attribute syn_useioff : boolean;
+ attribute syn_useioff : boolean;
attribute syn_useioff of FLASH_NCS : signal is true;
attribute syn_useioff of FLASH_SCLK : signal is true;
attribute syn_useioff of FLASH_MOSI : signal is true;
attribute syn_preserve : boolean;
signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic;
- signal GSR_N : std_logic;
- signal reset_i : std_logic;
- signal clear_i : std_logic;
- signal trigger_in_i : std_logic;
+ signal GSR_N : std_logic;
+ signal reset_i : std_logic;
+ signal clear_i : std_logic;
+ signal trigger_in_i : std_logic;
signal debug_clock_reset : std_logic_vector(31 downto 0);
signal debug_tools : std_logic_vector(31 downto 0);
signal flash_ncs_i : std_logic;
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
- signal header_io_i : std_logic_vector(10 downto 1);
- signal timer : TIMERS;
- signal led_off : std_logic;
+ signal header_io_i : std_logic_vector(10 downto 1);
+ signal timer : TIMERS;
+ signal led_off : std_logic;
--TDC
- signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1);
- signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
- signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
+ signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1);
+ signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
+ signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
attribute syn_keep of GSR_N : signal is true;
signal link_stat_in_reg : std_logic;
-
-
begin
trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);
-
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- Clock & Reset Handling
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
THE_CLOCK_RESET : entity work.clock_reset_handler
port map(
CLOCK_IN => CLK_200,
RESET_FROM_NET => med2int(0).stat_op(13),
SEND_RESET_IN => med2int(0).stat_op(15),
+ BUS_RX => bustc_rx,
+ BUS_TX => bustc_tx,
+ RESET_OUT => reset_i,
+ CLEAR_OUT => clear_i,
+ GSR_OUT => GSR_N,
+ REF_CLK_OUT => clk_full,
+ SYS_CLK_OUT => clk_sys,
+ RAW_CLK_OUT => clk_full_osc,
+ DEBUG_OUT => debug_clock_reset
+ );
- BUS_RX => bustc_rx,
- BUS_TX => bustc_tx,
-
- RESET_OUT => reset_i,
- CLEAR_OUT => clear_i,
- GSR_OUT => GSR_N,
-
- REF_CLK_OUT => clk_full,
- SYS_CLK_OUT => clk_sys,
- RAW_CLK_OUT => clk_full_osc,
-
- DEBUG_OUT => debug_clock_reset
- );
-
-
-
-THE_CAL_PLL : entity work.pll_in125_out50
- port map(
- CLKI => CLK_125,
- CLKOP => clk_cal
+ THE_CAL_PLL : entity work.pll_in125_out50
+ port map(
+ CLKI => CLK_125,
+ CLKOP => clk_cal
);
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- TrbNet Uplink
----------------------------------------------------------------------------
-
+-------------------------------------------------------------------------------
THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
generic map(
SERDES_NUM => 0,
IS_SYNC_SLAVE => c_YES
- )
+ )
port map(
- CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,
+ CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
--Internal Connection
MEDIA_MED2INT => med2int(0),
MEDIA_INT2MED => int2med(0),
-
--Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
-
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN => sfp_prsnt_i,
- SD_LOS_IN => sfp_los_i,
- SD_TXDIS_OUT => sfp_txdis_i,
+ SD_PRSNT_N_IN => sfp_prsnt_i,
+ SD_LOS_IN => sfp_los_i,
+ SD_TXDIS_OUT => sfp_txdis_i,
--Control Interface
- BUS_RX => bussci_rx,
- BUS_TX => bussci_tx,
+ BUS_RX => bussci_rx,
+ BUS_TX => bussci_tx,
-- Status and control port
STAT_DEBUG => med_stat_debug(63 downto 0),
CTRL_DEBUG => open
- );
+ );
gen_sfp_con : if SERDES_NUM = 1 generate
sfp_los_i <= SFP_LOS;
BACK_GPIO(0) <= sfp_txdis_i;
end generate;
-
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- Endpoint
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
generic map (
ADDRESS_MASK => x"FFFF",
TRG_RELEASE_AFTER_DATA => c_YES,
HEADER_BUFFER_DEPTH => 9,
HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
-
+ )
port map(
-- Misc
- CLK => clk_sys,
- RESET => reset_i,
- CLK_EN => '1',
-
+ CLK => clk_sys,
+ RESET => reset_i,
+ CLK_EN => '1',
-- Media direction port
- MEDIA_MED2INT => med2int(0),
- MEDIA_INT2MED => int2med(0),
-
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
--Timing trigger in
TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,
-
- READOUT_RX => readout_rx,
- READOUT_TX => readout_tx,
-
+ -- readout
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
--Slow Control Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- BUS_RX => ctrlbus_rx,
- BUS_TX => ctrlbus_tx,
- BUS_MASTER_IN => bus_master_in,
- BUS_MASTER_OUT => bus_master_out,
- BUS_MASTER_ACTIVE => bus_master_active,
-
- ONEWIRE_INOUT => open,
- I2C_SCL => I2C_SCL,
- I2C_SDA => I2C_SDA,
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg,
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ --UniqueID
+ ONEWIRE_INOUT => open,
+ I2C_SCL => I2C_SCL,
+ I2C_SDA => I2C_SDA,
--Timing registers
- TIMERS_OUT => timer
- );
+ TIMERS_OUT => timer
+ );
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- Bus Handler
----------------------------------------------------------------------------
-
-
+-------------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
PORT_NUMBER => 4,
PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"c000", others => x"0000"),
PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0),
PORT_MASK_ENABLE => 1
- )
+ )
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
- REGIO_RX => ctrlbus_rx,
- REGIO_TX => ctrlbus_tx,
-
- BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => bussci_rx, --SCI Serdes
- BUS_RX(2) => bustc_rx, --Clock switch
- BUS_RX(3) => bustdc_rx,
- BUS_TX(0) => bustools_tx,
- BUS_TX(1) => bussci_tx,
- BUS_TX(2) => bustc_tx,
- BUS_TX(3) => bustdc_tx,
-
+ CLK => clk_sys,
+ RESET => reset_i,
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bussci_rx, --SCI Serdes
+ BUS_RX(2) => bustc_rx, --Clock switch
+ BUS_RX(3) => bustdc_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bussci_tx,
+ BUS_TX(2) => bustc_tx,
+ BUS_TX(3) => bustdc_tx,
STAT_DEBUG => open
- );
+ );
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- Control Tools
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
THE_TOOLS : entity work.trb3sc_tools
port map(
- CLK => clk_sys,
- RESET => reset_i,
-
+ CLK => clk_sys,
+ RESET => reset_i,
--Flash & Reload
FLASH_CS => flash_ncs_i,
FLASH_CLK => FLASH_SCLK,
BUS_MASTER_OUT => bus_master_out,
BUS_MASTER_ACTIVE => bus_master_active,
DEBUG_OUT => debug_tools
- );
+ );
FLASH_HOLD <= '1';
FLASH_WP <= '1';
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- I/O
----------------------------------------------------------------------------
-
+-------------------------------------------------------------------------------
CS <= spi_cs(3 downto 0);
spi_miso(3 downto 0) <= MISO;
TEST(14) <= flash_ncs_i;
FLASH_NCS <= flash_ncs_i;
----------------------------------------------------------------------------
+-------------------------------------------------------------------------------
-- LED
----------------------------------------------------------------------------
-
+-------------------------------------------------------------------------------
LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
-
THE_TDC : entity work.TDC_record
generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
- STATUS_REG_NR => 21, -- Number of status regs
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS,
+ STATUS_REG_NR => 21,
DEBUG => c_NO,
- SIMULATION => c_NO)
+ SIMULATION => c_NO
+ )
port map (
RESET => reset_i,
CLK_TDC => clk_full,
- CLK_READOUT => clk_sys, -- Clock for the readout
- REFERENCE_TIME => trigger_in_i, -- Reference time input
- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+ CLK_READOUT => clk_sys,
+ REFERENCE_TIME => trigger_in_i,
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1),
+ HIT_CAL_IN => clk_cal,
-- Trigger signals from handler
BUSRDO_RX => readout_rx,
BUSRDO_TX => readout_tx(0),
-- Dubug signals
INFO_IN => timer,
LOGIC_ANALYSER_OUT => open
- );
+ );
-------------------------------------------------------------------------------
jspc29 / trb5sc.git / commitdiff