remove outdated ports from design

diff --git a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
index 0d2ba52c9372348a456e75b860d5db0433f244e8..087b8bcefd3e2f082402ac1ba7990056e72c3f32 100644 (file)
--- a/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
+++ b/releases/tdc_v2.3/trb3_periph_32PinAddOn.vhd
@@ -25,8 +25,8 @@ entity trb3_periph_32PinAddOn is
     --Serdes
     CLK_SERDES_INT_LEFT  : in    std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
     CLK_SERDES_INT_RIGHT : in    std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
-    SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
-    SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
+--     SERDES_INT_TX        : out   std_logic_vector(3 downto 0);
+--     SERDES_INT_RX        : in    std_logic_vector(3 downto 0);
     --Inter-FPGA Communication
     FPGA5_COMM           : inout std_logic_vector(11 downto 0);
                                         --Bit 0/1 input, serial link RX active
@@ -159,7 +159,7 @@ begin
 ---------------------------------------------------------------------------
 -- Clock Handling
 ---------------------------------------------------------------------------
-  THE_MAIN_PLL : pll_in200_out100
+  THE_MAIN_PLL : entity work.pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
       RESET => '0',
@@ -202,10 +202,10 @@ begin
       MED_READ_IN        => '1',
       REFCLK2CORE_OUT    => open,
       --SFP Connection
-      SD_RXD_P_IN        => SERDES_INT_RX(2),
-      SD_RXD_N_IN        => SERDES_INT_RX(3),
-      SD_TXD_P_OUT       => SERDES_INT_TX(2),
-      SD_TXD_N_OUT       => SERDES_INT_TX(3),
+--       SD_RXD_P_IN        => SERDES_INT_RX(2),
+--       SD_RXD_N_IN        => SERDES_INT_RX(3),
+--       SD_TXD_P_OUT       => SERDES_INT_TX(2),
+--       SD_TXD_N_OUT       => SERDES_INT_TX(3),
       SD_REFCLK_P_IN     => open,
       SD_REFCLK_N_IN     => open,
       SD_PRSNT_N_IN      => FPGA5_COMM(0),