added timer.vhd

diff --git a/source/timer.vhd b/source/timer.vhd
new file mode 100644 (file)
index 0000000..456e681
--- /dev/null
+++ b/source/timer.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity timer is
+  port (
+    clk    :in  std_logic; -- Input clock
+    reset  :out std_logic  -- Output of the counter
+    );
+end timer;
+
+architecture rtl of timer is
+ 
+  signal count :   std_logic_vector (26 downto 0);
+  signal temporal: STD_LOGIC;
+ 
+begin
+  process (clk) begin
+                  
+  if (rising_edge(clk)) then
+    count <= count + 1;
+    if (count(26)='1') then
+      temporal <= NOT(temporal);
+      count<=(others=>'0');
+    end if;
+  end if;
+                 
+  end process;
+  reset <= temporal;
+  
+end rtl;