tdc_v1.6.3 is made back compatible

diff --git a/tdc_releases/tdc_v1.6.3/Channel.vhd b/tdc_releases/tdc_v1.6.3/Channel.vhd
index e9d0494667fbb7e34fd56aa8723b07db5d3f4b88..06365df4bd62406b71f15ab4cac7ba957e194193 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Channel.vhd
+++ b/tdc_releases/tdc_v1.6.3/Channel.vhd
@@ -6,6 +6,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
+use work.tdc_components.all;
 use work.config.all;
 
 entity Channel is

diff --git a/tdc_releases/tdc_v1.6.3/Channel_200.vhd b/tdc_releases/tdc_v1.6.3/Channel_200.vhd
index b73e24a3a2b94e94906d3cd5a016101c95aa6946..e75e4a70097311d96adf1492c5bf13039821c229 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Channel_200.vhd
+++ b/tdc_releases/tdc_v1.6.3/Channel_200.vhd
@@ -5,7 +5,7 @@
 -- File       : Channel_200.vhd
 -- Author     : c.ugur@gsi.de
 -- Created    : 2012-08-28
--- Last update: 2014-07-16
+-- Last update: 2014-12-03
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -18,6 +18,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
+use work.tdc_components.all;
 use work.config.all;
 
 entity Channel_200 is

diff --git a/tdc_releases/tdc_v1.6.3/Encoder_304_Bit.vhd b/tdc_releases/tdc_v1.6.3/Encoder_304_Bit.vhd
index 49d46a809f11022546aa5ed8f355ca4da7c39482..c937e566006a4383b21270057739c1b135291ff7 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Encoder_304_Bit.vhd
+++ b/tdc_releases/tdc_v1.6.3/Encoder_304_Bit.vhd
@@ -21,6 +21,7 @@ use ieee.numeric_std.all;
 library work;
 use work.trb_net_std.all;
 use work.trb3_components.all;
+use work.tdc_components.all;
 
 -- synopsys translate_off
 library ecp3;

diff --git a/tdc_releases/tdc_v1.6.3/Readout.vhd b/tdc_releases/tdc_v1.6.3/Readout.vhd
index 452c8c631ab8dab27cab6e9d837138b1366fff06..18fa6752f7f139c83e7148b356cf755900dc8f14 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/Readout.vhd
+++ b/tdc_releases/tdc_v1.6.3/Readout.vhd
@@ -5,7 +5,7 @@
 -- File       : Readout.vhd
 -- Author     : cugur@gsi.de
 -- Created    : 2012-10-25
--- Last update: 2014-05-08
+-- Last update: 2014-12-03
 -------------------------------------------------------------------------------
 -- Description: 
 -------------------------------------------------------------------------------
@@ -20,6 +20,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
+use work.tdc_components.all;
 
 entity Readout is
   generic (

diff --git a/tdc_releases/tdc_v1.6.3/TDC.vhd b/tdc_releases/tdc_v1.6.3/TDC.vhd
index 77354252adcad9aaf980c4b9007a5d55e94ed3b4..427a31320bb320ac25babfc6a869556042441996 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/TDC.vhd
+++ b/tdc_releases/tdc_v1.6.3/TDC.vhd
@@ -7,6 +7,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb3_components.all;
+use work.tdc_components.all;
 use work.version.all;
 
 entity TDC is

diff --git a/tdc_releases/tdc_v1.6.3/tdc_components.vhd b/tdc_releases/tdc_v1.6.3/tdc_components.vhd
index 964cd7bda922af9d53450f725e4ffbc287d33450..f5d30b895bdfbcf0a55dd0cb0883d6a975f758ce 100644 (file)
--- a/tdc_releases/tdc_v1.6.3/tdc_components.vhd
+++ b/tdc_releases/tdc_v1.6.3/tdc_components.vhd
@@ -5,7 +5,9 @@ library work;
 use work.trb_net_std.all;
 
 package tdc_components is
-  
+
+  type unsigned_array_8 is array (integer range <>) of unsigned(7 downto 0);
+    
   component TDC is
     generic (
       CHANNEL_NUMBER : integer range 2 to 65;
@@ -70,6 +72,12 @@ package tdc_components is
       EFB_DATA_OUT          : out std_logic_vector(31 downto 0);
       EFB_DATAREADY_OUT     : out std_logic;
       EFB_UNKNOWN_ADDR_OUT  : out std_logic;
+      FWB_READ_EN_IN        : in  std_logic;  -- not used after version 1.3
+      FWB_WRITE_EN_IN       : in  std_logic;  -- not used after version 1.3
+      FWB_ADDR_IN           : in  std_logic_vector(6 downto 0);  -- not used after version 1.3
+      FWB_DATA_OUT          : out std_logic_vector(31 downto 0);  -- not used after version 1.3
+      FWB_DATAREADY_OUT     : out std_logic;  -- not used after version 1.3
+      FWB_UNKNOWN_ADDR_OUT  : out std_logic;  -- not used after version 1.3
       LHB_READ_EN_IN        : in  std_logic;
       LHB_WRITE_EN_IN       : in  std_logic;
       LHB_ADDR_IN           : in  std_logic_vector(6 downto 0);
@@ -80,6 +88,59 @@ package tdc_components is
       CONTROL_REG_IN        : in  std_logic_vector(32*CONTROL_REG_NR-1 downto 0));
   end component TDC;
 
+  component Reference_Channel
+    generic (
+      CHANNEL_ID : integer range 0 to 0);
+    port (
+      RESET_200              : in  std_logic;
+      RESET_100              : in  std_logic;
+      CLK_200                : in  std_logic;
+      CLK_100                : in  std_logic;
+      HIT_IN                 : in  std_logic;
+      READ_EN_IN             : in  std_logic;
+      VALID_TMG_TRG_IN       : in  std_logic;
+      SPIKE_DETECTED_IN      : in  std_logic;
+      MULTI_TMG_TRG_IN       : in  std_logic;
+      FIFO_DATA_OUT          : out std_logic_vector(35 downto 0);
+      FIFO_WCNT_OUT          : out unsigned(7 downto 0);
+      FIFO_EMPTY_OUT         : out std_logic;
+      FIFO_FULL_OUT          : out std_logic;
+      FIFO_ALMOST_FULL_OUT   : out std_logic;
+      COARSE_COUNTER_IN      : in  std_logic_vector(10 downto 0);
+      EPOCH_COUNTER_IN       : in  std_logic_vector(27 downto 0);
+      TRIGGER_WINDOW_END_IN  : in  std_logic;
+      DATA_FINISHED_IN       : in  std_logic;
+      RUN_MODE               : in  std_logic;
+      TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0);
+      REF_DEBUG_OUT          : out std_logic_vector(31 downto 0));
+  end component;
+
+  component Reference_Channel_200
+    generic (
+      CHANNEL_ID : integer range 0 to 0);
+    port (
+      CLK_200                : in  std_logic;
+      RESET_200              : in  std_logic;
+      CLK_100                : in  std_logic;
+      RESET_100              : in  std_logic;
+      VALID_TMG_TRG_IN       : in  std_logic;
+      SPIKE_DETECTED_IN      : in  std_logic;
+      MULTI_TMG_TRG_IN       : in  std_logic;
+      HIT_IN                 : in  std_logic;
+      READ_EN_IN             : in  std_logic;
+      FIFO_DATA_OUT          : out std_logic_vector(35 downto 0);
+      FIFO_WCNT_OUT          : out unsigned(7 downto 0);
+      FIFO_EMPTY_OUT         : out std_logic;
+      FIFO_FULL_OUT          : out std_logic;
+      FIFO_ALMOST_FULL_OUT   : out std_logic;
+      EPOCH_COUNTER_IN       : in  std_logic_vector(27 downto 0);
+      TRIGGER_WINDOW_END_IN  : in  std_logic;
+      TRIGGER_TIME_STAMP_OUT : out std_logic_vector(38 downto 0);
+      DATA_FINISHED_IN       : in  std_logic;
+      RUN_MODE               : in  std_logic;
+      COARSE_COUNTER_IN      : in  std_logic_vector(10 downto 0));
+  end component;
+
   component Channel
     generic (
       CHANNEL_ID : integer range 0 to 64;
@@ -93,7 +154,6 @@ package tdc_components is
       CLK_200                 : in  std_logic;
       CLK_100                 : in  std_logic;
       HIT_IN                  : in  std_logic;
-      HIT_EDGE_IN             : in  std_logic;
       TRIGGER_WIN_END_TDC     : in  std_logic;
       TRIGGER_WIN_END_RDO     : in  std_logic;
       READ_EN_IN              : in  std_logic;
@@ -102,6 +162,7 @@ package tdc_components is
       FIFO_EMPTY_OUT          : out std_logic;
       FIFO_FULL_OUT           : out std_logic;
       FIFO_ALMOST_EMPTY_OUT   : out std_logic;
+      FIFO_ALMOST_FULL_OUT    : out std_logic;
       COARSE_COUNTER_IN       : in  std_logic_vector(10 downto 0);
       EPOCH_COUNTER_IN        : in  std_logic_vector(27 downto 0);
       VALID_TIMING_TRG_IN     : in  std_logic;
@@ -110,7 +171,7 @@ package tdc_components is
       MULTI_TMG_TRG_IN        : in  std_logic;
       EPOCH_WRITE_EN_IN       : in  std_logic;
       LOST_HIT_NUMBER         : out std_logic_vector(23 downto 0);
-      HIT_DETECT_NUMBER       : out std_logic_vector(30 downto 0);
+      HIT_DETECT_NUMBER       : out std_logic_vector(23 downto 0);
       ENCODER_START_NUMBER    : out std_logic_vector(23 downto 0);
       ENCODER_FINISHED_NUMBER : out std_logic_vector(23 downto 0);
       FIFO_WRITE_NUMBER       : out std_logic_vector(23 downto 0);
@@ -118,7 +179,7 @@ package tdc_components is
       Channel_DEBUG           : out std_logic_vector(31 downto 0));
   end component;
 
-  component Channel_200 is
+  component Channel_200
     generic (
       CHANNEL_ID : integer range 0 to 64;
       DEBUG      : integer range 0 to 1;
@@ -129,8 +190,8 @@ package tdc_components is
       RESET_200             : in  std_logic;
       CLK_100               : in  std_logic;
       RESET_100             : in  std_logic;
+      RESET_COUNTERS        : in  std_logic;
       HIT_IN                : in  std_logic;
-      HIT_EDGE_IN           : in  std_logic;
       TRIGGER_WIN_END_TDC   : in  std_logic;
       TRIGGER_WIN_END_RDO   : in  std_logic;
       EPOCH_COUNTER_IN      : in  std_logic_vector(27 downto 0);
@@ -138,6 +199,9 @@ package tdc_components is
       READ_EN_IN            : in  std_logic;
       FIFO_DATA_OUT         : out std_logic_vector(35 downto 0);
       FIFO_DATA_VALID_OUT   : out std_logic;
+      FIFO_EMPTY_OUT        : out std_logic;
+      FIFO_FULL_OUT         : out std_logic;
+      FIFO_ALMOST_FULL_OUT  : out std_logic;
       VALID_TIMING_TRG_IN   : in  std_logic;
       VALID_NOTIMING_TRG_IN : in  std_logic;
       SPIKE_DETECTED_IN     : in  std_logic;
@@ -146,24 +210,8 @@ package tdc_components is
       ENCODER_START_OUT     : out std_logic;
       ENCODER_FINISHED_OUT  : out std_logic;
       FIFO_WRITE_OUT        : out std_logic;
-      CHANNEL_200_DEBUG     : out std_logic_vector(31 downto 0)); 
-  end component Channel_200;
-
-  component Readout_Header is
-    port (
-      RESET_100             : in  std_logic;
-      CLK_100               : in  std_logic;
-      VALID_TIMING_TRG_IN   : in  std_logic;
-      VALID_NOTIMING_TRG_IN : in  std_logic;
-      INVALID_TRG_IN        : in  std_logic;
-      TRG_CODE_IN           : in  std_logic_vector(7 downto 0);
-      TRG_TYPE_IN           : in  std_logic_vector(3 downto 0);
-      TRG_RELEASE_OUT       : out std_logic;
-      TRG_STATUSBIT_OUT     : out std_logic_vector(31 downto 0);
-      DATA_OUT              : out std_logic_vector(31 downto 0);
-      DATA_WRITE_OUT        : out std_logic;
-      DATA_FINISHED_OUT     : out std_logic);
-  end component Readout_Header;
+      Channel_200_DEBUG     : out std_logic_vector(31 downto 0));
+  end component;
 
   component Readout is
     generic (
@@ -176,11 +224,14 @@ package tdc_components is
       RESET_COUNTERS           : in  std_logic;
       CLK_100                  : in  std_logic;
       CLK_200                  : in  std_logic;
+      TRIGGER_RDO_IN           : in  std_logic;
+      TRIGGER_TDC_IN           : in  std_logic;
       CH_DATA_IN               : in  std_logic_vector_array_36(0 to CHANNEL_NUMBER);
       CH_DATA_VALID_IN         : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
       CH_EMPTY_IN              : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
       CH_FULL_IN               : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
       CH_ALMOST_EMPTY_IN       : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+      CH_ALMOST_FULL_IN        : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
       TRG_DATA_VALID_IN        : in  std_logic;
       VALID_TIMING_TRG_IN      : in  std_logic;
       VALID_NOTIMING_TRG_IN    : in  std_logic;
@@ -205,16 +256,20 @@ package tdc_components is
       TRIGGER_WIN_EN_IN        : in  std_logic;
       TRIG_WIN_END_TDC_IN      : in  std_logic;
       TRIG_WIN_END_RDO_IN      : in  std_logic;
-      TRIGGER_TDC_IN           : in  std_logic;
-      TRIG_TIME_IN             : in  std_logic_vector(38 downto 0);
       COARSE_COUNTER_IN        : in  std_logic_vector(10 downto 0);
       EPOCH_COUNTER_IN         : in  std_logic_vector(27 downto 0);
       DEBUG_MODE_EN_IN         : in  std_logic;
       STATUS_REGISTERS_BUS_OUT : out std_logic_vector_array_32(0 to STATUS_REG_NR-1);
       READOUT_DEBUG            : out std_logic_vector(31 downto 0);
-      REFERENCE_TIME           : in  std_logic); 
+-- ports not used after tdc_v1.5.2
+      TRIGGER_WIN_END_OUT      : out std_logic;
+      CH_WCNT_IN               : in  unsigned_array_8(0 to CHANNEL_NUMBER-1);
+      REFERENCE_TIME           : in  std_logic;
+      TRIGGER_TIME_IN          : in  std_logic_vector(38 downto 0)
+      );
   end component Readout;
 
+
   component TriggerHandler is
     generic (
       TRIGGER_NUM            : integer;
@@ -232,10 +287,7 @@ package tdc_components is
       TRIGGER_WIN_EN_IN       : in  std_logic;
       TRIGGER_WIN_POST_IN     : in  unsigned(10 downto 0);
       TRIGGER_WIN_END_RDO_OUT : out std_logic;
-      TRIGGER_WIN_END_TDC_OUT : out std_logic;
-      COARSE_COUNTER_IN       : in  std_logic_vector(10 downto 0);
-      EPOCH_COUNTER_IN        : in  std_logic_vector(27 downto 0);
-      TRIGGER_TIME_OUT        : out std_logic_vector(38 downto 0) := (others => '0'));
+      TRIGGER_WIN_END_TDC_OUT : out std_logic);
   end component TriggerHandler;
 
   component LogicAnalyser
@@ -273,33 +325,6 @@ package tdc_components is
       Q          : out std_logic_vector(3 downto 0));
   end component;
 
-  component Stretcher is
-    generic (
-      CHANNEL : integer range 1 to 64;
-      DEPTH   : integer range 1 to 10);
-    port (
-      PULSE_IN  : in  std_logic_vector(CHANNEL-1 downto 0);
-      PULSE_OUT : out std_logic_vector(CHANNEL-1 downto 0));
-  end component Stretcher;
-
-  component Stretcher_A is
-    generic (
-      CHANNEL : integer range 1 to 64;
-      DEPTH   : integer range 1 to 10);
-    port (
-      PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH downto 1);
-      PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 0));
-  end component Stretcher_A;
-
-  component Stretcher_B is
-    generic (
-      CHANNEL : integer range 1 to 64;
-      DEPTH   : integer range 1 to 10);
-    port (
-      PULSE_IN  : in  std_logic_vector(CHANNEL*DEPTH-1 downto 1);
-      PULSE_OUT : out std_logic_vector(CHANNEL*DEPTH-1 downto 1));
-  end component Stretcher_B;
-
   component up_counter
     generic (
       NUMBER_OF_BITS : positive); 
@@ -332,6 +357,17 @@ package tdc_components is
       ENCODER_DEBUG    : out std_logic_vector(31 downto 0));
   end component Encoder_304_Bit;
 
+  --component Encoder_304_Bit
+  --  port (
+  --    RESET           : in  std_logic;
+  --    CLK             : in  std_logic;
+  --    START_IN        : in  std_logic;
+  --    THERMOCODE_IN   : in  std_logic_vector(303 downto 0);
+  --    FINISHED_OUT    : out std_logic;
+  --    BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
+  --    ENCODER_DEBUG   : out std_logic_vector(31 downto 0));
+  --end component;
+
   component hit_mux is
     port (
       CH_EN_IN           : in  std_logic;
@@ -350,14 +386,60 @@ package tdc_components is
       Q          : out std_logic_vector(7 downto 0));
   end component;
 
-  component ROM4_Encoder is
+  component bit_sync
+    generic (
+      DEPTH : integer);
     port (
-      Address    : in  std_logic_vector(9 downto 0);
-      OutClock   : in  std_logic;
-      OutClockEn : in  std_logic;
-      Reset      : in  std_logic;
-      Q          : out std_logic_vector(7 downto 0));
-  end component ROM4_Encoder;
+      RESET : in  std_logic;
+      CLK0  : in  std_logic;
+      CLK1  : in  std_logic;
+      D_IN  : in  std_logic;
+      D_OUT : out std_logic);
+  end component;
+
+  component edge_to_pulse
+    port (
+      clock     : in  std_logic;
+      en_clk    : in  std_logic;
+      signal_in : in  std_logic;
+      pulse     : out std_logic);
+  end component;
+
+  component risingEdgeDetect is
+    port (
+      CLK       : in  std_logic;
+      SIGNAL_IN : in  std_logic;
+      PULSE_OUT : out std_logic);
+  end component risingEdgeDetect;
+
+  component fallingEdgeDetect is
+    port (
+      CLK       : in  std_logic;
+      SIGNAL_IN : in  std_logic;
+      PULSE_OUT : out std_logic);
+  end component fallingEdgeDetect;
+
+  component ShiftRegisterSISO
+    generic (
+      DEPTH : integer range 1 to 32;
+      WIDTH : integer range 1 to 32);
+    port (
+      CLK   : in  std_logic;
+      D_IN  : in  std_logic_vector(WIDTH-1 downto 0);
+      D_OUT : out std_logic_vector(WIDTH-1 downto 0));
+  end component;
+
+  component Stretcher
+    port (
+      PULSE_IN  : in  std_logic;
+      PULSE_OUT : out std_logic);
+  end component;
+
+  component WaveLauncher is
+    port (
+      HIT_IN  : in  std_logic;
+      HIT_OUT : out std_logic);
+  end component WaveLauncher;
 
 
 end package tdc_components;