signal a_aod_data_i : std_logic;
signal pulse_trdyo_i : std_logic;
signal debug_trigger_distributor_i : std_logic_vector(31 downto 0);
+ signal last_LVL1_TRG_RECEIVED_OUT : std_logic;
+ signal pseudo_timing_trigger : std_logic;
begin
---------------------------------------------------------------------
-- IPU Data channel handler
---------------------------------------------------------------------
- IPU_LENGTH_IN <= x"0005";
- IPU_ERROR_PATTERN_IN <= (others => '0');
-
- process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- IPU_READOUT_FINISHED_IN <= '0';
- ipu_counter <= ipu_counter;
- IPU_DATAREADY_IN <= '0';
- if IPU_START_READOUT_OUT = '1' then
- IPU_DATAREADY_IN <= IPU_DATAREADY_IN;
- if IPU_DATAREADY_IN = '0' and IPU_READOUT_FINISHED_IN = '0' then
- ipu_counter <= ipu_counter + 1;
- IPU_DATAREADY_IN <= '1';
- elsif IPU_DATAREADY_IN = '1' and IPU_READ_OUT = '1' then
- IPU_DATAREADY_IN <= '0';
- end if;
- if ipu_counter = x"5" or IPU_READOUT_FINISHED_IN = '1' then
- ipu_counter <= (others => '0');
- IPU_DATAREADY_IN <= '0';
- IPU_READOUT_FINISHED_IN <= '1';
- end if;
- else
- ipu_counter <= (others => '0');
- end if;
- end if;
- end process;
- IPU_DATA_IN(15 downto 0) <= std_logic_vector(ipu_counter);
- IPU_DATA_IN(31 downto 16) <= std_logic_vector(0 - unsigned(ipu_counter));
-
-
+-- IPU_LENGTH_IN <= x"0005";
+-- IPU_ERROR_PATTERN_IN <= (others => '0');
+
+-- process(CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- IPU_READOUT_FINISHED_IN <= '0';
+-- ipu_counter <= ipu_counter;
+-- IPU_DATAREADY_IN <= '0';
+-- if IPU_START_READOUT_OUT = '1' then
+-- IPU_DATAREADY_IN <= IPU_DATAREADY_IN;
+-- if IPU_DATAREADY_IN = '0' and IPU_READOUT_FINISHED_IN = '0' then
+-- ipu_counter <= ipu_counter + 1;
+-- IPU_DATAREADY_IN <= '1';
+-- elsif IPU_DATAREADY_IN = '1' and IPU_READ_OUT = '1' then
+-- IPU_DATAREADY_IN <= '0';
+-- end if;
+-- if ipu_counter = x"5" or IPU_READOUT_FINISHED_IN = '1' then
+-- ipu_counter <= (others => '0');
+-- IPU_DATAREADY_IN <= '0';
+-- IPU_READOUT_FINISHED_IN <= '1';
+-- end if;
+-- else
+-- ipu_counter <= (others => '0');
+-- end if;
+-- end if;
+-- end process;
+-- IPU_DATA_IN(15 downto 0) <= std_logic_vector(ipu_counter);
+-- IPU_DATA_IN(31 downto 16) <= std_logic_vector(0 - unsigned(ipu_counter));
---------------------------------------------------------------------
-- SlowControl Handler
---------------------------------------------------------------------
-- Transport trigger to FEE
---------------------------------------------------------------------
+
+ PROC_GEN_TIMING : process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ last_LVL1_TRG_RECEIVED_OUT <= REGIO_REGISTERS_OUT(0);
+ pseudo_timing_trigger <= REGIO_REGISTERS_OUT(0) and not last_LVL1_TRG_RECEIVED_OUT;
+ end if;
+ end process;
+
THE_TRIG_DISTR : trigger_distributor
port map (
CLK => CLK_100,
RESET => reset,
INTERNAL_RESET_IN => '0',
A_RDO_IN => token_to_mux_out_i,
- TRIGGER_IN => LVL1_TRG_RECEIVED_OUT,
- TRIGGER_TYPE_IN => '0',
+ TRIGGER_IN => pseudo_timing_trigger,
+ TRIGGER_TYPE_IN => LVL1_TRG_TYPE_OUT,
INIT_ALL_BUSES_OUT => init_all_buses_i,
ROC1_WRITTEN_IN => roc1_written_i,
- TOKEN_TO_TRB_OUT => open,
+ TOKEN_TO_TRB_OUT => open,--LVL1_TRG_RELEASE_IN,
CAL_TRIGGER_REGISTER_IN => (others => '0'),
DEBUG_REGISTER_OUT => debug_trigger_distributor_i,
- LED_CNT_1_OUT => open,--D(4),
- LED_CNT_2_OUT => open,--D(2),
- LED_ERROR_OUT => open,
- LED_GOOD_OUT => open
+ LED_CNT_1_OUT => D(4),
+ LED_CNT_2_OUT => D(3),
+ LED_ERROR_OUT => D(2),
+ LED_GOOD_OUT => D(1)
);
---------------------------------------------------------------------
--generic map (bus_number => bus_number)
port map (
CLK => CLK_100,
- --A_ADD => tad_data_i,--TAD,
RESET => reset,
A_ADS_0 => '0',
A_ADS_1 => '0',
A_ADS_2 => '0',
- --A_AOD => aod_i,--TAOD,
A_ACK => TACK,
A_CMS => CMS,
- --A_DST => dst_i,--TDST,
- A_RDM => RDYI, --out
+ A_RDM => RDYI,--out to MB
A_GDE => GDE,
A_RDO => TRDYO,--in
A_RESERV => TRSV,
LVL1_TRG_CODE_IN => LVL1_TRG_CODE_OUT,
LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_OUT,
LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_IN,
- LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_IN,
+ LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_IN,
--Data Port
- IPU_NUMBER_IN => IPU_NUMBER_OUT,
- IPU_INFORMATION_IN => IPU_INFORMATION_OUT,
+ IPU_NUMBER_IN => IPU_NUMBER_OUT,
+ IPU_INFORMATION_IN => IPU_INFORMATION_OUT,
--start strobe
- IPU_START_READOUT_IN => IPU_START_READOUT_OUT,
+ IPU_START_READOUT_IN => IPU_START_READOUT_OUT,
--detector data, equipped with DHDR
--- IPU_DATA_OUT => IPU_DATA_IN,
--- IPU_DATAREADY_OUT => IPU_DATAREADY_IN,
--- --no more data, end transfer, send TRM
--- IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN,
--- --will be low every second cycle due to 32bit -> 16bit conversion
--- IPU_LENGTH_OUT => IPU_LENGTH_IN,
--- IPU_ERROR_PATTERN_OUT=> IPU_ERROR_PATTERN_IN.
- IPU_READ_IN => IPU_READ_OUT
+ IPU_DATA_OUT => IPU_DATA_IN,
+ IPU_DATAREADY_OUT => IPU_DATAREADY_IN,
+ --no more data, end transfer, send TRM
+ IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN,
+ --will be low every second cycle due to 32bit -> 16bit conversion
+ IPU_LENGTH_OUT => IPU_LENGTH_IN,
+ IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_IN,
+ IPU_READ_IN => IPU_READ_OUT
);
-------------------------------------------------------------------------------
TAOD <= 'Z';
TDST <= 'Z';
TAD <= (others => 'Z');
- -- D(3) <= (a_add_data_i(0) and a_add_data_i(1) and
- -- a_add_data_i(2) and a_add_data_i(3) and
- -- a_add_data_i(4) and a_add_data_i(5) and
- -- a_add_data_i(6) and a_add_data_i(7) and
- -- a_add_data_i(8));
- -------------------------------------------------------------------------------
- -- -
- -------------------------------------------------------------------------------
+-- D(1) <= '0';
+-- D(2) <= '1';
elsif(debug_trigger_distributor_i(3 downto 0) = x"5" or
debug_trigger_distributor_i(3 downto 0) = x"6" or
debug_trigger_distributor_i(3 downto 0) = x"7") then
a_add_data_i <= (others => '0');
a_aod_data_i <= '0';
a_dst_data_i <= '0';
- -- D(3) <= '0';
- -------------------------------------------------------------------------------
- -- -
- -------------------------------------------------------------------------------
-
+-- D(1) <= '1';
+-- D(2) <= '1';
else
+
--DATA TACKING
a_add_data_i <= TAD;
a_aod_data_i <= TAOD;
TAOD <= 'Z';
TDST <= 'Z';
TAD <= (others => 'Z');
- -- D(3) <= (a_add_data_i(0) and a_add_data_i(1) and
- -- a_add_data_i(2) and a_add_data_i(3) and
- -- a_add_data_i(4) and a_add_data_i(5) and
- -- a_add_data_i(6) and a_add_data_i(7) and
- -- a_add_data_i(8));
+-- D(1) <= '0';
+-- D(2) <= '0';
end if;
end process;
-
-
---------------------------------------------------------------------
-- Outputs to Logic Analyzer
---------------------------------------------------------------------
---------------------------------------------------------------------
-- LED
---------------------------------------------------------------------
- D(1) <= not MED_STAT_DEBUG(1);
- D(2) <= not MED_STAT_OP(9);
- D(3) <= not MED_STAT_DEBUG(7);
- D(4) <= not MED_STAT_DEBUG(8);
+-- D(1) <= not MED_STAT_DEBUG(1);
+-- D(2) <= not MED_STAT_OP(9);
+-- D(3) <= not MED_STAT_DEBUG(7);
+-- D(4) <= not MED_STAT_DEBUG(8);
-- STAT_OP(14) <= reset_me; -- reset out
-- STAT_OP(15) <= buf_RESET_TRBNET_OUT;
--- STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
+-- STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32);
-- stat_debug(3 downto 0) <= state_bits;
-- stat_debug(4) <= align_me;
-- stat_debug(5) <= buf_swap_bytes;
jspc29 / mdcoep.git / commitdiff