+
+
+
+
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Memory Map}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{Trigger Control Registers}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+For all registers described in this subsection refer to the Fig.\ref{cts_logic}
\begin{description}
- \item[]
-\end{description}
+\item[RW registers] of the trigger logic
+ \begin{description}
+ \item [0xA0CC] Individual bits are enabling inputs
+ \item [0xA0D1 - 0xA0D4] Delay input signals, each nibble corresponds to one input e.g. 0xA0D1(3 to 0) corresponds to first input of the start part (Start 0). Delay value = 4 bit value * clock period (5ns)
+ \item [0xA0CD - 0xA0CE] Downscale input signals, each input signal is downscaled - $2^{value}$
+ \item [0xA0D6 - 0xA0D8] Set width = value*clock period
+ \item [0xA0D9] Bits 12 down to 0 - TS gating disable
+ \item [0xA0DA] Bits 14 down to 0 - trigger out enable
+ \item [0xA0DB] Bits 6 down to 0 is selecting multiplexer output for ADO TTL(1) line and 14 down to 8 for ADO TTL(2)
+ \begin{description}
+ \item [31 - 0] delayed signals
+ \item [46 - 32] pti $and$ gts out
+ \item [47] lvl1 trigger
+ \item [48] Start and Veto antycoincidence
+ \item [49] Veto set width out
+ \item [50] Start downscaled in
+ \item [51] LVL1 busy
+ \item [52] OR out
+ \item [53] Start downscaled out
+ \item [54] Veto downscaled out
+ \item [63 - 55] Multiplicity out
+ \end{description}
+ \item [0xA0DC 4 downto 0], if 0xA0DC(4)=0 then standard trigger selection else trigger code = 0xA0DC(3 downto 0)
+ \item [0xA0DC bit 5] MDC calibration trigger enable
+ \item [0xA0DC bit 6] Force update Shower pedestals trigger (write ..1..0)
+ \item [0xA0DC bit 7] Disable Shower pedestals update (generated once during each spill off)
+ \item [0xA0DC 11 down to 8] Select frequency for internally generated trigger - $781.25kHz/(2^value)$
+ \end{description}
+\item[R registers] of the trigger logic
+ \begin{description}
+ \item [0xA089] Trigger logic debug out
+ \item [0xA09B -0xA0BA] Scalers out
+ \end{description}
+\end{description}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsubsection{CTS Control and Status Registers}
\item[0xA093: IPU status] Status bits for event fifo, fill level and current IPU trigger number
\begin{description}
+ \item[Bit 0] CTS event random number fifo full
\item[Bit 1] CTS event random number fifo empty
\item[Bit 2] CTS event number / type fifo full
\item[Bit 3] CTS event number / type fifo empty
\item[Bit 11 -- 4] Difference between LVL1 and IPU event counters
\item[Bit 23 -- 12] IPU event number
\item[Bit 31 -- 24] CTS fifo data counter
- \item[Bit 28] CTS event random number fifo full
\end{description}
\item[0xA0C3: Etrax control] Etrax readout control register
\begin{description}
\item[Bit 4] Disable readout on Etrax
\end{description}
+
+% \item[0xA0C9] Select how many times should be sent data to the EB with current ID (which corresponds to the EB IP number), when 0 does not swith between IDs
+% \item[0xA0CA] Tables of 8 EB IDs (each ID has four bits), the IDs are switched form CA(3 down to 0) to CA(7 down to 4) ... CB(31 down to 28)
+% \item[0xA0CB] Tables of 8 EB IDs (each ID has four bits)
+
+% \end{description}
\end{description}
+
+\begin{figure}
+ \centering
+ \includegraphics[width=.9\textwidth]{cts_doc.pdf}
+ \caption{CTS trigger box logic}
+ \label{cts_logic}
+\end{figure}
+
+
\usepackage{upgreek}
\usepackage{listings}
\usepackage{scrtime}
+\usepackage{lscape}
+
+
\definecolor{darkblue}{rgb}{0,0,.5}
\usepackage[linkbordercolor={0 0 0},
\title{DaqNet - A Preliminary Handbook}
\date{\today ~-~\thistime}
-\author{Jan Michel, Michael B\"ohmer, Grzegorz Korcyl}
+\author{Jan Michel, Michael B\"ohmer, Grzegorz Korcyl, Marek Palka}
\newcommand{\filename}[1]{\textit{#1}}