adjustments to code

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 00657765b78305a7d6ade8c71a71e90df3f734eb..6dddfc7b01c15c557eaf76c359247d1420be6581 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -157,14 +157,6 @@ begin
   assert not (quad_mode = 8)                           report "Note: QUAD with one slave port detected" severity note;
   assert not ((quad_mode >= 9) and (quad_mode <= 11))  report "Note: mixed master/slave QUAD detected" severity note;
   
--------------------------------------------------      
--- only used SerDes are activated
--------------------------------------------------      
---  powerup_ch(3) <= '0' when IS_MODE(3) = c_IS_UNUSED else '1';
---  powerup_ch(2) <= '0' when IS_MODE(2) = c_IS_UNUSED else '1';
---  powerup_ch(1) <= '0' when IS_MODE(1) = c_IS_UNUSED else '1';
---  powerup_ch(0) <= '0' when IS_MODE(0) = c_IS_UNUSED else '1';
-
 -------------------------------------------------      
 -- SFPs are disabled on unused SerDes channels
 -------------------------------------------------      
@@ -465,6 +457,8 @@ end generate;
       SCI_WR      => sci_write_i,
       -- WAP
       WA_POS_OUT  => wa_position,
+      WA_READ_OUT => open,
+      LINK_RX_READY_IN => '0',
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 92b1299503669bea0fc17eb7dc6018d116312192..c7620287d33340f50a657edaf888d9842ffa6344 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -116,7 +116,6 @@ begin
   TX_RESET_OUT <= '0';
                   
 -- RX_RESET_FSM reset
---  clrn_rx_fsm_i <= not (CLEAR or RESET or sd_los_q);
   clr_rx_fsm_i     <= sd_los_q;
 
   MASTER_RESET_OUT <= sd_los_q;
@@ -130,23 +129,21 @@ begin
 -------------------------------------------------
   THE_RX_RST_FSM: rx_rsl
     port map(
-      CLEAR         => clr_rx_fsm_i,
-      REFCLK        => CLK_REF,
-      pll_lol       => PLL_LOL_IN,
-      cdr_lol       => RX_CDR_LOL_IN,
-      cv            => CV_IN,
-      lsm           => LSM_IN,
-      los           => RX_LOS_IN,
+      CLEAR             => clr_rx_fsm_i,
+      CLK_REF           => CLK_REF,
+      PLL_LOL_IN        => PLL_LOL_IN,
+      CDR_LOL_IN        => RX_CDR_LOL_IN,
+      CV_IN             => CV_IN,
+      LSM_IN            => LSM_IN,
+      LOS_IN            => RX_LOS_IN,
       -- outputs
-      rx_serdes_rst => rx_serdes_rst_i,
-      rx_pcs_rst    => rx_pcs_rst_i,
-      state_out     => rx_fsm_state
+      RX_SERDES_RST_OUT => rx_serdes_rst_i,
+      RX_PCS_RST_OUT    => rx_pcs_rst_i,
+      LINK_RX_READY_OUT => link_rx_ready_i,
+      STATE_OUT         => rx_fsm_state
     );
-
     
-  link_rx_ready_i <= '0'; -- BUG
-
--- reset signals for RX SerDes need to be sync'ed to real RX clock
+-- reset signals for RX SerDes need to be sync'ed to real RX clock for ECP5
   SYNC_RST_SIGS: entity work.signal_sync 
     generic map( WIDTH => 2 )
     port map(
@@ -297,11 +294,11 @@ begin
   DEBUG_OUT(2)            <= RX_CDR_LOL_IN;
   DEBUG_OUT(3)            <= rx_pcs_rst_i;
   DEBUG_OUT(4)            <= rx_serdes_rst_i;
-  DEBUG_OUT(5)            <= CV_IN;--link_rx_ready_i;
-  DEBUG_OUT(6)            <= LSM_IN;--link_half_done_i;
-  DEBUG_OUT(7)            <= PLL_LOL_IN;--link_full_done_i;
-  DEBUG_OUT(8)            <= RESET;--LINK_TX_READY_IN;
-  DEBUG_OUT(9)            <= CLEAR;--is_wap_zero_i;
+  DEBUG_OUT(5)            <= CV_IN;
+  DEBUG_OUT(6)            <= LSM_IN;
+  DEBUG_OUT(7)            <= PLL_LOL_IN;
+  DEBUG_OUT(8)            <= link_rx_ready_i;
+  DEBUG_OUT(9)            <= CLEAR;
   DEBUG_OUT(10)           <= clr_rx_fsm_i;
   DEBUG_OUT(11)           <= reset_i;
   DEBUG_OUT(15 downto 12) <= rx_fsm_state;

diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd
index 5b44a8526628b53a3f6fd87605702c65a28d71fe..e3a8aa89023baac150bd825426ece9106df6914c 100644 (file)
--- a/media_interfaces/sync/med_sync_define_RS.vhd
+++ b/media_interfaces/sync/med_sync_define_RS.vhd
@@ -27,17 +27,18 @@ constant D_IDLE1  : std_logic_vector(7 downto 0) := x"50"; -- D16.2
 \r
 component rx_rsl is\r
   port (\r
-    CLEAR         : in  std_logic;\r
-    refclk        : in  std_logic;\r
-    pll_lol       : in  std_logic;\r
-    cdr_lol       : in  std_logic;\r
-    cv            : in  std_logic;\r
-    lsm           : in  std_logic;\r
-    los           : in  std_logic;\r
+    CLEAR             : in  std_logic;\r
+    CLK_REF           : in  std_logic;\r
+    PLL_LOL_IN        : in  std_logic;\r
+    CDR_LOL_IN        : in  std_logic;\r
+    CV_IN             : in  std_logic;\r
+    LSM_IN            : in  std_logic;\r
+    LOS_IN            : in  std_logic;\r
     -- outputs\r
-    rx_serdes_rst : out  std_logic;\r
-    rx_pcs_rst    : out  std_logic;\r
-    state_out     : out  std_logic_vector(3 downto 0)\r
+    RX_SERDES_RST_OUT : out std_logic;\r
+    RX_PCS_RST_OUT    : out std_logic;\r
+    LINK_RX_READY_OUT : out std_logic;\r
+    STATE_OUT         : out std_logic_vector(3 downto 0)\r
   );\r
 end component;  \r
 \r

diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd
index 90af3c8874044e12ee264b639b7a77b3b8c297ac..0a2828d2965b48b8ac5d01b3d78c5f9413c0530a 100644 (file)
--- a/media_interfaces/sync/rx_rsl.vhd
+++ b/media_interfaces/sync/rx_rsl.vhd
@@ -1,195 +1,199 @@
 library ieee;\r
 use ieee.std_logic_1164.all;\r
-use IEEE.std_logic_unsigned.all;\r
-use IEEE.std_logic_arith.all;\r
+USE IEEE.numeric_std.all;\r
 \r
 entity rx_rsl is\r
   port (\r
-    CLEAR         : in  std_logic;\r
-    refclk        : in  std_logic;\r
-    pll_lol       : in  std_logic;\r
-    cdr_lol       : in  std_logic;\r
-    cv            : in  std_logic;\r
-    lsm           : in  std_logic;\r
-    los           : in  std_logic;\r
+    CLEAR             : in  std_logic;\r
+    CLK_REF           : in  std_logic;\r
+    PLL_LOL_IN        : in  std_logic;\r
+    CDR_LOL_IN        : in  std_logic;\r
+    CV_IN             : in  std_logic;\r
+    LSM_IN            : in  std_logic;\r
+    LOS_IN            : in  std_logic;\r
     -- outputs\r
-    rx_serdes_rst : out  std_logic;\r
-    rx_pcs_rst    : out  std_logic;\r
-    state_out     : out  std_logic_vector(3 downto 0)\r
+    RX_SERDES_RST_OUT : out std_logic;\r
+    RX_PCS_RST_OUT    : out std_logic;\r
+    LINK_RX_READY_OUT : out std_logic;\r
+    STATE_OUT         : out std_logic_vector(3 downto 0)\r
   );\r
 end rx_rsl;  \r
 \r
 architecture rx_rsl_arc of rx_rsl is\r
 \r
-attribute syn_keep : boolean;\r
+  attribute syn_keep : boolean;\r
 \r
-------------------------------------------------------------------\r
---                  Constants Declaration           --\r
-------------------------------------------------------------------\r
+-- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3.\r
+-- Without this piece of code, many things would have been a real pain.\r
 \r
+  constant Tshort     : unsigned(31 downto 0) := x"00000007";\r
 --@125MHz 100ms\r
+  constant Tplol      : unsigned(31 downto 0) := x"00BEBC20";\r
+  constant Tcdr       : unsigned(31 downto 0) := x"00BEBC20";\r
+  constant Tviol      : unsigned(31 downto 0) := x"00BEBC20";\r
 \r
-constant Tplol      : std_logic_vector (31 downto 0):=x"00BEBC20";\r
-constant Tcdr       : std_logic_vector (31 downto 0):=x"00BEBC20";\r
-constant Tviol      : std_logic_vector (31 downto 0):=x"00BEBC20";\r
+  signal pll_lol_s    : std_logic;\r
+  signal cdr_lol_s    : std_logic;\r
+  signal cv_s         : std_logic;\r
+  signal lsm_s        : std_logic;\r
+  signal los_s        : std_logic;\r
 \r
-------------------------------------------------------------------\r
---                  Internal Variables             --\r
-------------------------------------------------------------------\r
-signal pll_lol_s    : std_logic;\r
-signal cdr_lol_s    : std_logic;\r
-signal cv_s        : std_logic;\r
-signal lsm_s      : std_logic;\r
-signal los_s      : std_logic;\r
+  signal cnt          : unsigned(31 downto 0);\r
 \r
-signal cnt        : std_logic_vector (31 downto 0);\r
+  type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, \r
+                       APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, IDLE);\r
 \r
-type rx_sm_state is (powerup, apply_cdr_rst, wait_cdr_lock, test_cdr, apply_rxpcs_rst, wait_rxpcs_lock, test_rxpcs, idle);\r
-signal rx_sm        : rx_sm_state;\r
-attribute syn_keep of rx_sm : signal is true;\r
+  signal rx_sm : rx_sm_state;\r
+  \r
+  attribute syn_keep of rx_sm : signal is true;\r
 \r
 begin\r
-------------------------------------------------------------------\r
---                  Components Instantiation        --\r
-------------------------------------------------------------------\r
 \r
-------------------------------------------------------------------\r
---                  Begin Of The Design             --\r
-------------------------------------------------------------------\r
-\r
--- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL.\r
+-- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL. Deadlocks on POWERUP.\r
+-- Remark: RX_LOS is not necessary, as SFP_LOS keeps us safely in reset.\r
+-- Remark: syncing is done here by one FF only. Might be dangerous.\r
 \r
 ------------------------------------------------------------------\r
-rx_reset_proc    :  process (CLEAR, refclk)\r
+RX_RESET_PROC : process( CLEAR, CLK_REF )\r
 begin\r
   if( CLEAR = '1' ) then\r
-    pll_lol_s     <= '1';\r
-    cdr_lol_s     <= '1';\r
-    cv_s          <= '1';\r
-    lsm_s         <= '0';\r
-    los_s         <= '1';  \r
-    \r
-    rx_serdes_rst <= '1';\r
-    rx_pcs_rst    <= '1';\r
+    pll_lol_s         <= '1';\r
+    cdr_lol_s         <= '1';\r
+    cv_s              <= '1';\r
+    lsm_s             <= '0';\r
+    los_s             <= '1';  \r
+\r
+    RX_SERDES_RST_OUT <= '1';\r
+    RX_PCS_RST_OUT    <= '1';\r
+    LINK_RX_READY_OUT <= '0';\r
   \r
     rx_sm         <= powerup;\r
     cnt           <= (others => '0');  \r
-  elsif( rising_edge(refclk) ) then\r
-    pll_lol_s     <= pll_lol;\r
-    cdr_lol_s     <= cdr_lol;\r
-    cv_s          <= cv;    \r
-    lsm_s         <= lsm;    \r
-    los_s         <= los;  \r
+  elsif( rising_edge(CLK_REF) ) then\r
+    pll_lol_s     <= PLL_LOL_IN;\r
+    cdr_lol_s     <= CDR_LOL_IN;\r
+    cv_s          <= CV_IN;    \r
+    lsm_s         <= LSM_IN;    \r
+    los_s         <= LOS_IN;  \r
   \r
     case rx_sm is\r
-      when powerup =>\r
-        state_out <= x"0";\r
---        rx_serdes_rst  <= '1'; -- bad idea\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '1';\r
+      when POWERUP =>\r
+        STATE_OUT <= x"0";\r
+        RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
         if( (pll_lol_s = '1') or (los_s = '1') ) then\r
-          cnt        <= (others => '0');\r
+          cnt <= (others => '0');\r
         else\r
           if( cnt = Tplol ) then\r
-            cnt     <= (others => '0');\r
-            rx_sm  <= apply_cdr_rst;\r
+            cnt <= (others => '0');\r
+            rx_sm <= APPLY_CDR_RST;\r
           else\r
-          cnt     <= cnt + '1';\r
+          cnt <= cnt + 1;\r
           end if;\r
         end if;\r
 \r
-      when apply_cdr_rst =>\r
-        state_out <= x"1";\r
-        rx_serdes_rst  <= '1';\r
-        rx_pcs_rst     <= '1';\r
-        if( cnt = x"00000007" ) then\r
-          cnt      <= (others => '0');\r
-          rx_sm    <= wait_cdr_lock;\r
+      when APPLY_CDR_RST =>\r
+        STATE_OUT <= x"1";\r
+        RX_SERDES_RST_OUT <= '1';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tshort ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= WAIT_CDR_LOCK;\r
         else\r
-          cnt      <= cnt + '1';  \r
+          cnt <= cnt + 1;  \r
         end if;\r
       \r
-      when wait_cdr_lock =>\r
-        state_out <= x"2";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '1';\r
+      when WAIT_CDR_LOCK =>\r
+        STATE_OUT <= x"2";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
         if( cnt = Tcdr ) then\r
-          cnt      <= (others => '0');\r
-          rx_sm    <= test_cdr;\r
+          cnt <= (others => '0');\r
+          rx_sm <= TEST_CDR;\r
         else\r
-          cnt      <= cnt + '1';  \r
+          cnt <= cnt + 1;  \r
         end if;\r
 \r
-      when test_cdr =>\r
-        state_out <= x"3";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '1';\r
+      when TEST_CDR =>\r
+        STATE_OUT <= x"3";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
         if( cdr_lol_s = '1' ) then\r
-          cnt        <= (others => '0');\r
-          rx_sm    <= apply_cdr_rst;\r
+          cnt <= (others => '0');\r
+          rx_sm <= APPLY_CDR_RST;\r
         else\r
           if( cnt = Tcdr ) then\r
-            cnt     <= (others => '0');\r
-            rx_sm  <= apply_rxpcs_rst;\r
+            cnt <= (others => '0');\r
+            rx_sm <= APPLY_RXPCS_RST;\r
           else\r
-            cnt     <= cnt + '1';\r
+            cnt <= cnt + 1;\r
           end if;\r
         end if;\r
-      when apply_rxpcs_rst =>\r
-        state_out <= x"4";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '1';\r
-        if (cnt = x"00000007") then\r
-          cnt      <= (others => '0');\r
-          rx_sm    <= wait_rxpcs_lock;\r
+\r
+      when APPLY_RXPCS_RST =>\r
+        STATE_OUT <= x"4";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tshort ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= WAIT_RXPCS_LOCK;\r
         else\r
-          cnt      <= cnt + '1';  \r
+          cnt <= cnt + 1;  \r
         end if;\r
 \r
-      when wait_rxpcs_lock =>\r
-        state_out <= x"5";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '0';\r
-        if (cnt = Tviol) then\r
-          cnt      <= (others => '0');\r
-          rx_sm    <= test_rxpcs;\r
+      when WAIT_RXPCS_LOCK =>\r
+        STATE_OUT <= x"5";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( cnt = Tviol ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= TEST_RXPCS;\r
         else\r
-          cnt      <= cnt + '1';  \r
-        end if;    \r
-      when test_rxpcs =>\r
-        state_out <= x"6";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '0';\r
-        if (lsm_s = '0') or (cv_s = '1') then\r
-          cnt        <= (others => '0');\r
-          rx_sm    <= apply_rxpcs_rst;\r
+          cnt <= cnt + 1;  \r
+        end if;\r
+\r
+      when TEST_RXPCS =>\r
+        STATE_OUT <= x"6";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        if( (lsm_s = '0') or (cv_s = '1') ) then\r
+          cnt <= (others => '0');\r
+          rx_sm <= APPLY_RXPCS_RST;\r
         else\r
-          if (cnt = Tviol) then\r
-            cnt     <= (others => '0');\r
-            rx_sm  <= idle;\r
+          if( cnt = Tviol ) then\r
+            cnt <= (others => '0');\r
+            rx_sm <= IDLE;\r
           else\r
-            cnt     <= cnt + '1';\r
+            cnt <= cnt + 1;\r
           end if;\r
         end if;\r
      \r
       when idle =>\r
-        state_out <= x"7";\r
-        rx_serdes_rst  <= '0';\r
-        rx_pcs_rst     <= '0';\r
-        if (lsm_s = '0') or (cv_s = '1') then\r
-          rx_sm    <= apply_rxpcs_rst;      \r
-          cnt      <= (others => '0');\r
+        STATE_OUT <= x"7";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '1';\r
+        if( (lsm_s = '0') or (cv_s = '1') ) then\r
+          rx_sm <= APPLY_RXPCS_RST;      \r
+          cnt <= (others => '0');\r
         end if;\r
     end case;\r
   \r
 ------------------------------------------------\r
 --  if (pll_lol_s = '1') or (los_s = '1') then\r
-  if (pll_lol_s = '1') then\r
-    rx_sm      <= powerup;      \r
-    cnt        <= (others => '0');\r
-  end if;\r
+    if( pll_lol_s = '1' ) then\r
+      rx_sm <= POWERUP;      \r
+      cnt <= (others => '0');\r
+    end if;\r
 \r
-end if;\r
+  end if;\r
 end process rx_reset_proc;\r
 \r
 end rx_rsl_arc;\r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 20721d784d94adf0582220370d1c5782640361d2..0f99fcea9c303b08dbda5ab7287df1c478ebffca 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -11,26 +11,27 @@ library work;
 entity sci_reader_RS is
 
   port(
-    CLK         : in std_logic;
-    RESET       : in std_logic;
+    CLK              : in std_logic;
+    RESET            : in std_logic;
     
     --SCI
-    SCI_WRDATA  : out std_logic_vector(7 downto 0);
-    SCI_RDDATA  : in  std_logic_vector(7 downto 0);
-    SCI_ADDR    : out std_logic_vector(5 downto 0);
-    SCI_SEL     : out std_logic_vector(4 downto 0);
-    SCI_RD      : out std_logic;
-    SCI_WR      : out std_logic;
+    SCI_WRDATA       : out std_logic_vector(7 downto 0);
+    SCI_RDDATA       : in  std_logic_vector(7 downto 0);
+    SCI_ADDR         : out std_logic_vector(5 downto 0);
+    SCI_SEL          : out std_logic_vector(4 downto 0);
+    SCI_RD           : out std_logic;
+    SCI_WR           : out std_logic;
     
-    WA_POS_OUT  : out std_logic_vector(15 downto 0);
-    WA_READ_OUT : out std_logic;
+    WA_POS_OUT       : out std_logic_vector(15 downto 0);
+    WA_READ_OUT      : out std_logic;
+    LINK_RX_READY_IN : in  std_logic;
     
     --Slowcontrol
-    BUS_RX      : in  CTRLBUS_RX;
-    BUS_TX      : out CTRLBUS_TX;    
+    BUS_RX           : in  CTRLBUS_RX;
+    BUS_TX           : out CTRLBUS_TX;    
     
     MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0');
-    DEBUG_OUT   : out std_logic_vector(31 downto 0)
+    DEBUG_OUT        : out std_logic_vector(31 downto 0)
     );
 end entity;
 
@@ -87,7 +88,7 @@ begin
         SCI_RD        <= BUS_RX.read  and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
         next_sci_wr   <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and     BUS_RX.addr(8));
         sci_state     <= SCTRL;
-      elsif sci_timer(sci_timer'left) = '1' then
+      elsif (sci_timer(sci_timer'left) = '1') and (LINK_RX_READY_IN = '0') then
         sci_timer     <= (others => '0');
         sci_state     <= GET_WA;
         wa_read_i     <= '1';