--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
TOPNAME => "trb3_periph_32PinAddOn",
-project_path => "32PinAddOn",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.6_x64',
synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
+par_options => '../trb3_periph_32PinAddOn.p2t',
#Include only necessary lpf files
include_TDC => 1,
# file (in .dly format) at the end of the par run.
#
#PAR Placement Command Line Options
-# -l Specifies the effort level of the design from 1 (simplest designs)
+# -l Specifies the effort level of the design from 1 (simplest designs)
# to 5 (most complex designs).
-# -m Multi-tasking option. Controlled by the compile.pl script.
-# -n Sets the number of iterations performed at the effort level
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
# specified by the -l option. Controlled by the compile.pl script.
# -s Save the number of best results for this run.
# -t Start placement at the specified cost table. Default is 1.
# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
# parCDR Enable the congestion-driven router (CDR) algorithm.
# Congestion-driven options like parCDR and parCDP can improve
-# performance given a design with multiple congestion “hotspots.” The
+# performance given a design with multiple congestion “hotspots.” The
# Layer > Congestion option of the Design Planner Floorplan View can
# help visualize routing congestion. Large congested areas may prevent
# the options from finding a successful solution.
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
- --ring buffer size: 32,64,96,128,dyn
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - single fine time and the chain for the 0x3ff hits
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
-TOPNAME => "trb3_periph_ADA_Addon",
-project_path => "ADA_Addon",
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
+TOPNAME => "trb3_periph_ADA",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.6_x64',
synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
+par_options => '../trb3_periph_ADA.p2t',
#Include only necessary lpf files
include_TDC => 1,
#General PAR Command Line Options
-# -w With this option, any files generated will overwrite existing files
-# (e.g., any .par, .pad files).
-# -y Adds the Delay Summary Report in the .par file and creates the delay
-# file (in .dly format) at the end of the par run.
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
#
#PAR Placement Command Line Options
-# -l Specifies the effort level of the design from 1 (simplest designs) to 5
-# (most complex designs).
-# -m Multi-tasking option. Controlled by the compile.pl script.
-# -n Sets the number of iterations performed at the effort level specified by
-# the -l option. Controlled by the compile.pl script.
-# -s Save the number of best results for this run.
-# -t Start placement at the specified cost table. Default is 1.
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
#
#PAR Routing Command Line Options
-# -c Run number of cost-based cleanup passes of the router.
-# -e Run number of delay-based cleanup passes of the router on
-# completely-routed designs only.
-# -i Run a maximum number of passes, stopping earlier only if the routing
-# goes to 100 percent completion and all constraints are met.
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
#
#PAR Explorer Command Line Options
-# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
-# compatible with all Lattice FPGA device families; however, most
-# benefit has been demonstrated with benchmarks targeted to ECP5,
-# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
-# parCDR Enable the congestion-driven router (CDR) algorithm.
-# Congestion-driven options like parCDR and parCDP can improve
-# performance given a design with multiple congestion “hotspots.”
-# The Layer > Congestion option of the Design Planner Floorplan
-# View can help visualize routing congestion. Large congested
-# areas may prevent the options from finding a successful
-# solution. CDR is compatible with all Lattice FPGA device
-# families however most benefit has been demonstrated with
-# benchmarks targeted to ECP5, LatticeECP2/M,LatticeECP3, and
-# LatticeXP2 device families.
-# paruseNBR NBR Router or Negotiation-based routing option. Supports all
-# FPGA device families except LatticeXP and MachXO. When turned
-# on, an alternate routing engine from the traditional
-# Rip-up-based routing selection (RBR) is used. This involves an
-# iterative routing algorithm that routes connections to achieve
-# minimum delay cost. It does so by computing the demand on each
-# routing resource and applying cost values per node. It will
-# complete when an optimal solution is arrived at or the number
-# of iterations is reached.
-# parPathBased Path-based placement option. Path-based timing driven placement
-# will yield better performance and more predictable results in
-# many cases.
-# parHold Additional hold time correction option. This option forces the
-# router to automatically insert extra wires to compensate for
-# the hold time violation.
-# parHoldLimit This option allows you to set a limit on the number of hold time
-# violations to be processed by the auto hold time correction
-# option parHold.
-# parPlcInLimit Cannot find in the online help
-# parPlcInNeighborSize Cannot find in the online help
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+# load configuration derived from config.vhd by compile_constraints.pl
+source workdir/trb3_periph_ADA_prjconfig.tcl
# implementation: "workdir"
impl -add workdir -type fpga
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC.vhd"
add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+}
+if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+}
add_file -vhdl -lib work "trb3_periph_ADA.vhd"
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
+# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
--- /dev/null
+-w
+-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 12
+-t 1
+-c 1
+-e 2
+-i 15
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+
+
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+# load configuration derived from config.vhd by compile_constraints.pl
+source workdir/cbmtof_prjconfig.tcl
# implementation: "workdir"
impl -add workdir -type fpga
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
-
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../base/code/sedcheck.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
-###############
-#Change path to tdc release also in compile script!
-###############
-
-#add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC.vhd"
add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
-add_file -vhdl -lib work "../base/code/input_statistics.vhd"
-add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+}
+if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+}
+
+# ###############
+# #Change path to tdc release also in compile script!
+# ###############
+
+# #add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
+# add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+# add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+# #add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+# add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+# add_file -vhdl -lib work "tdc_release/Channel.vhd"
+# add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+# #add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
+# add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+# add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+# #add_file -vhdl -lib work "tdc_release/Readout.vhd"
+# add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+# add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
+# add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+# add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+# add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+# add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+# #add_file -vhdl -lib work "tdc_release/TDC.vhd"
+# add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+# add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+# add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+# add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+# add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+# add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+# add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+# add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+# add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+# add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
add_file -vhdl -lib work "cbmtof.vhd"
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
- --ring buffer size: 32,64,96,128,dyn
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - single fine time and the chain for the 0x3ff hits
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
- constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
- constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11; --13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 1024; --4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
--Include SPI on AddOn connector
constant INCLUDE_SPI : integer := c_YES;
--Add logic to generate configurable trigger signal from input signals.
constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --not compatible with cbmtof!
- constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs
+ constant INCLUDE_STATISTICS : integer := c_NO; --Do histos of all inputs
constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected
constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
TOPNAME => "cbmtof",
-project_path => "cbmtof",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.6_x64',
synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
+par_options => '../cbmtof.p2t',
#Include only necessary lpf files
include_TDC => 1,
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
+# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_EXT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_osc 2x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_osc TO CLKNET clk_100_osc 5x;
-MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_EXT_c 2x;
+# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_osc TO CLKNET clk_100_osc 5x;
+# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_EXT_c 2x;
--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 25; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
- --ring buffer size: 32,64,96,128,dyn
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - single fine time and the chain for the 0x3ff hits
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 4096; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
constant INCLUDE_SPI : integer := c_NO; --there is no spi connector on the addon
--Add logic to generate configurable trigger signal from input signals.
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs
constant PHYSICAL_INPUTS : integer := 24; --number of inputs connected
constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
TOPNAME => "trb3_periph_gpin",
-project_path => "gpin",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.6_x64',
synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
+par_options => '../trb3_periph_gpin.p2t',
#Include only necessary lpf files
include_TDC => 1,
-w
--i 15
--l 5
--n 1
-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
-s 12
--t 10
+-t 1
-c 1
-e 2
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
+-i 15
-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+
+
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
+# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
package config is
-
------------------------------------------------------------------------------
--Begin of design configuration
------------------------------------------------------------------------------
--TDC settings
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5;
- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
- constant USE_DOUBLE_EDGE : integer := c_YES;
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size: 0, 1, 2, 3
- --ring buffer size: 32,64,96,128
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 2; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - single fine time and the chain for the 0x3ff hits
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
--use only every fourth input as in HPTDC high precision mode
constant USE_HPTDC_FASTMODE_PINOUT : integer := c_YES;
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2
t(7 downto 0) := std_logic_vector(to_unsigned(USE_HPTDC_FASTMODE_PINOUT*3,8));
- t(11 downto 8) := std_logic_vector(to_unsigned(USE_DOUBLE_EDGE*2,4));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
t(15) := '1'; --TDC
+ t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
TOPNAME => "trb3_periph_hadesstart",
-project_path => "hadesstart",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
lattice_path => '/opt/lattice/diamond/3.6_x64',
synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
+par_options => '../trb3_periph_hadesstart.p2t',
#Include only necessary lpf files
include_TDC => 1,
--- /dev/null
+-w
+-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 12
+-t 1
+-c 1
+-e 2
+-i 15
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+
+
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+# load configuration derived from config.vhd by compile_constraints.pl
+source workdir/trb3_periph_hadesstart_prjconfig.tcl
# implementation: "workdir"
impl -add workdir -type fpga
#add_file options
add_file -vhdl -lib work "workdir/version.vhd"
-add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
add_file -vhdl -lib work "config.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
add_file -vhdl -lib "work" "../base/trb3_components.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-
-
-
-###############
-#Change path to tdc release also in compile script!
-###############
-#add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
-add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
-add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
-add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
-add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
-add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd"
-add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
-#add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd"
-add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
-add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
-add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"
-add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x64_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x16_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x16_OutReg.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd"
-#add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd"
-
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
add_file -vhdl -lib "work" "../base/code/input_statistics.vhd"
add_file -vhdl -lib "work" "../base/code/sedcheck.vhd"
+
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+}
+if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+}
+
+
+# ###############
+# #Change path to tdc release also in compile script!
+# ###############
+# #add_file -vhdl -lib "work" "tdc_release/Adder_304.vhd"
+# add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd"
+# add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd"
+# add_file -vhdl -lib "work" "tdc_release/Channel.vhd"
+# add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd"
+# add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd"
+# #add_file -vhdl -lib "work" "tdc_release/FIFO_36x128_OutReg_Counter.vhd"
+# add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd"
+# add_file -vhdl -lib "work" "tdc_release/Readout.vhd"
+# #add_file -vhdl -lib "work" "tdc_release/ROM4_Encoder.vhd"
+# add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd"
+# add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd"
+# add_file -vhdl -lib "work" "tdc_release/TDC.vhd"
+# add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd"
+# add_file -vhdl -lib "work" "tdc_release/up_counter.vhd"
+# add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd"
+# add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd"
+# add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_36x64_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_36x32_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_36x16_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x64_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x32_OutReg.vhd"
+# add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x16_OutReg.vhd"
+# #add_file -vhdl -lib "work" "tdc_release/Reference_Channel_200.vhd"
+# #add_file -vhdl -lib "work" "tdc_release/Reference_Channel.vhd"
+
+
add_file -vhdl -lib "work" "trb3_periph_hadesstart.vhd"
use work.trb_net_std.all;
use work.trb_net_components.all;
use work.trb3_components.all;
+use work.tdc_components.all;
use work.config.all;
use work.tdc_version.all;
use work.version.all;
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal clk_125_i : std_logic; -- 125 MHz, via Clock Manager and bypassed PLL
- signal clk_20_i : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL
signal osc_int : std_logic; -- clock for calibrating the tdc, 20 MHz, via Clock Manager and internal PLL
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal clear_i : std_logic;
--LVL1 channel
signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i : std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic;
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
- signal fee_data_i : std_logic_vector(31 downto 0);
- signal fee_data_write_i : std_logic;
- signal fee_data_finished_i : std_logic;
- signal fee_almost_full_i : std_logic;
+
+ --READOUT
+ signal readout_rx : READOUT_RX;
+ signal readout_tx : readout_tx_array_t(0 to 0);
--Slow Control channel
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+ signal timer : TIMERS;
--RegIO
signal regio_addr_out : std_logic_vector (15 downto 0);
signal spi_sdo : std_logic;
signal spi_sck : std_logic;
- signal hitreg_read_en : std_logic;
- signal hitreg_write_en : std_logic;
- signal hitreg_addr : std_logic_vector(6 downto 0);
- signal hitreg_data_out : std_logic_vector(31 downto 0);
- signal hitreg_data_ready : std_logic;
- signal hitreg_invalid : std_logic;
-
- signal srb_read_en : std_logic;
- signal srb_write_en : std_logic;
- signal srb_addr : std_logic_vector(6 downto 0);
- signal srb_data_out : std_logic_vector(31 downto 0);
- signal srb_data_ready : std_logic;
- signal srb_invalid : std_logic;
-
- signal cdb_read_en : std_logic;
- signal cdb_write_en : std_logic;
- signal cdb_data_in : std_logic_vector(31 downto 0);
- signal cdb_addr : std_logic_vector(6 downto 0);
- signal cdb_data_out : std_logic_vector(31 downto 0);
- signal cdb_data_ready : std_logic;
- signal cdb_invalid : std_logic;
-
- signal lhb_read_en : std_logic;
- signal lhb_write_en : std_logic;
- signal lhb_addr : std_logic_vector(6 downto 0);
- signal lhb_data_out : std_logic_vector(31 downto 0);
- signal lhb_data_ready : std_logic;
- signal lhb_invalid : std_logic;
-
- signal esb_read_en : std_logic;
- signal esb_write_en : std_logic;
- signal esb_addr : std_logic_vector(6 downto 0);
- signal esb_data_out : std_logic_vector(31 downto 0);
- signal esb_data_ready : std_logic;
- signal esb_invalid : std_logic;
-
- signal efb_read_en : std_logic;
- signal efb_write_en : std_logic;
- signal efb_addr : std_logic_vector(6 downto 0);
- signal efb_data_out : std_logic_vector(31 downto 0);
- signal efb_data_ready : std_logic;
- signal efb_invalid : std_logic;
-
- signal tdc_ctrl_read : std_logic;
- signal last_tdc_ctrl_read : std_logic;
- signal tdc_ctrl_write : std_logic;
- signal tdc_ctrl_addr : std_logic_vector(2 downto 0);
- signal tdc_ctrl_data_in : std_logic_vector(31 downto 0);
- signal tdc_ctrl_data_out : std_logic_vector(31 downto 0);
- signal tdc_ctrl_reg : std_logic_vector(5*32+31 downto 0);
-
signal spi_bram_addr : std_logic_vector(7 downto 0);
signal spi_bram_wr_d : std_logic_vector(7 downto 0);
signal spi_bram_rd_d : std_logic_vector(7 downto 0);
signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
signal sed_error : std_logic;
- signal bussed_rx : CTRLBUS_RX;
- signal bussed_tx : CTRLBUS_TX;
+ signal bussed_rx, bustdc_rx : CTRLBUS_RX;
+ signal bussed_tx, bustdc_tx : CTRLBUS_TX;
--TDC
signal hit_in_i : std_logic_vector(64 downto 1);
THE_MAIN_PLL : pll_in200_out100
port map(
CLK => CLK_GPLL_RIGHT,
+ RESET => '0',
CLKOP => clk_100_i,
CLKOK => clk_200_i,
LOCK => pll_lock
);
- -- generates hits for calibration uncorrelated with tdc clk
- THE_CALIBRATION_PLL : pll_in125_out20
+ pll_calibration: entity work.pll_in125_out33
port map (
CLK => CLK_GPLL_LEFT,
- CLKOP => clk_20_i,
- CLKOK => clk_125_i,
+ CLKOP => osc_int,
LOCK => open);
- OSCInst0 : OSCF -- internal oscillator with frequency of 2.5MHz
- port map (
- OSC => osc_int);
-
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
--Timing trigger in
TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
-
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
+ LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid,
+ LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg,
+ LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg,
+ LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg,
+
+ LVL1_TRG_TYPE_OUT => readout_rx.trg_type,
+ LVL1_TRG_NUMBER_OUT => readout_rx.trg_number,
+ LVL1_TRG_CODE_OUT => readout_rx.trg_code,
+ LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information,
+ LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number,
--Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
+ TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple,
+ TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout,
+ TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious,
+ TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing,
+ TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
--Response from FEE
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
- FEE_DATA_IN => fee_data_i,
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+ FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release,
+ FEE_TRG_STATUSBITS_IN => readout_tx(0).statusbits,
+ FEE_DATA_IN => readout_tx(0).data,
+ FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write,
+ FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished,
+ FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
TIME_LOCAL_OUT => local_time,
TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
TIME_TICKS_OUT => timer_ticks,
+ TEMPERATURE_OUT => timer.temperature,
STAT_DEBUG_IPU => open,
STAT_DEBUG_1 => open,
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
PORT_NUMBER => 9,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"cf80", 2 => x"d400", 3 => x"c000", 4 => x"c100",
- 5 => x"c800", 6 => x"cf00", 7 => x"d500", 8 => x"c200", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 7, 2 => 5, 3 => 7, 4 => 5,
- 5 => 3, 6 => 6, 7 => 4, 8 => 7, others => 0)
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"cf80", 2 => x"d400", 3 => x"c000",
+ 4 => x"cf00", 5 => x"d500", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 9, 1 => 7, 2 => 5, 3 => 12,
+ 4 => 6, 5 => 4, others => 0)
)
port map(
CLK => clk_100_i,
BUS_WRITE_ACK_IN(2) => spidac_ack,
BUS_NO_MORE_DATA_IN(2) => spidac_busy,
BUS_UNKNOWN_ADDR_IN(2) => '0',
- --HitRegisters
- BUS_READ_ENABLE_OUT(3) => hitreg_read_en,
- BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en,
- BUS_DATA_OUT(3*32+31 downto 3*32) => open,
- BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out,
- BUS_DATAREADY_IN(3) => hitreg_data_ready,
- BUS_WRITE_ACK_IN(3) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid,
- --Status Registers
- BUS_READ_ENABLE_OUT(4) => srb_read_en,
- BUS_WRITE_ENABLE_OUT(4) => srb_write_en,
- BUS_DATA_OUT(4*32+31 downto 4*32) => open,
- BUS_ADDR_OUT(4*16+6 downto 4*16) => srb_addr,
- BUS_ADDR_OUT(4*16+15 downto 4*16+7) => open,
+ --TDC
+ BUS_READ_ENABLE_OUT(3) => bustdc_rx.read,
+ BUS_WRITE_ENABLE_OUT(3) => bustdc_rx.write,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => bustdc_rx.data,
+ BUS_ADDR_OUT(3*16+15 downto 3*16) => bustdc_rx.addr,
+ BUS_TIMEOUT_OUT(3) => bustdc_rx.timeout,
+ BUS_DATA_IN(3*32+31 downto 3*32) => bustdc_tx.data,
+ BUS_DATAREADY_IN(3) => bustdc_tx.ack,
+ BUS_WRITE_ACK_IN(3) => bustdc_tx.ack,
+ BUS_NO_MORE_DATA_IN(3) => bustdc_tx.nack,
+ BUS_UNKNOWN_ADDR_IN(3) => bustdc_tx.unknown,
+ --Trigger logic registers
+ BUS_READ_ENABLE_OUT(4) => trig_read,
+ BUS_WRITE_ENABLE_OUT(4) => trig_write,
+ BUS_DATA_OUT(4*32+31 downto 4*32) => trig_din,
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => trig_addr,
BUS_TIMEOUT_OUT(4) => open,
- BUS_DATA_IN(4*32+31 downto 4*32) => srb_data_out,
- BUS_DATAREADY_IN(4) => srb_data_ready,
- BUS_WRITE_ACK_IN(4) => '0',
+ BUS_DATA_IN(4*32+31 downto 4*32) => trig_dout,
+ BUS_DATAREADY_IN(4) => trig_ack,
+ BUS_WRITE_ACK_IN(4) => trig_ack,
BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_UNKNOWN_ADDR_IN(4) => srb_invalid,
- ----Encoder Start Registers
- --BUS_READ_ENABLE_OUT(5) => esb_read_en,
- --BUS_WRITE_ENABLE_OUT(5) => esb_write_en,
- --BUS_DATA_OUT(5*32+31 downto 5*32) => open,
- --BUS_ADDR_OUT(5*16+6 downto 5*16) => esb_addr,
- --BUS_ADDR_OUT(5*16+15 downto 5*16+7) => open,
- --BUS_TIMEOUT_OUT(5) => open,
- --BUS_DATA_IN(5*32+31 downto 5*32) => esb_data_out,
- --BUS_DATAREADY_IN(5) => esb_data_ready,
- --BUS_WRITE_ACK_IN(5) => '0',
- --BUS_NO_MORE_DATA_IN(5) => '0',
- --BUS_UNKNOWN_ADDR_IN(5) => esb_invalid,
- ----Fifo Write Registers
- --BUS_READ_ENABLE_OUT(6) => efb_read_en,
- --BUS_WRITE_ENABLE_OUT(6) => efb_write_en,
- --BUS_DATA_OUT(6*32+31 downto 6*32) => open,
- --BUS_ADDR_OUT(6*16+6 downto 6*16) => efb_addr,
- --BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open,
- --BUS_TIMEOUT_OUT(6) => open,
- --BUS_DATA_IN(6*32+31 downto 6*32) => efb_data_out,
- --BUS_DATAREADY_IN(6) => efb_data_ready,
- --BUS_WRITE_ACK_IN(6) => '0',
- --BUS_NO_MORE_DATA_IN(6) => '0',
- --BUS_UNKNOWN_ADDR_IN(6) => efb_invalid,
- ----Lost Hit Registers
- --BUS_READ_ENABLE_OUT(7) => lhb_read_en,
- --BUS_WRITE_ENABLE_OUT(7) => lhb_write_en,
- --BUS_DATA_OUT(7*32+31 downto 7*32) => open,
- --BUS_ADDR_OUT(7*16+6 downto 7*16) => lhb_addr,
- --BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open,
- --BUS_TIMEOUT_OUT(7) => open,
- --BUS_DATA_IN(7*32+31 downto 7*32) => lhb_data_out,
- --BUS_DATAREADY_IN(7) => lhb_data_ready,
- --BUS_WRITE_ACK_IN(7) => '0',
- --BUS_NO_MORE_DATA_IN(7) => '0',
- --BUS_UNKNOWN_ADDR_IN(7) => lhb_invalid,
- --TDC config registers
- BUS_READ_ENABLE_OUT(5) => tdc_ctrl_read,
- BUS_WRITE_ENABLE_OUT(5) => tdc_ctrl_write,
- BUS_DATA_OUT(5*32+31 downto 5*32) => tdc_ctrl_data_in,
- BUS_ADDR_OUT(5*16+2 downto 5*16) => tdc_ctrl_addr,
- BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open,
- BUS_TIMEOUT_OUT(5) => open,
- BUS_DATA_IN(5*32+31 downto 5*32) => tdc_ctrl_data_out,
- BUS_DATAREADY_IN(5) => last_tdc_ctrl_read,
- BUS_WRITE_ACK_IN(5) => tdc_ctrl_write,
- BUS_NO_MORE_DATA_IN(5) => '0',
- BUS_UNKNOWN_ADDR_IN(5) => '0',
- --Trigger logic registers
- BUS_READ_ENABLE_OUT(6) => trig_read,
- BUS_WRITE_ENABLE_OUT(6) => trig_write,
- BUS_DATA_OUT(6*32+31 downto 6*32) => trig_din,
- BUS_ADDR_OUT(6*16+15 downto 6*16) => trig_addr,
- BUS_TIMEOUT_OUT(6) => open,
- BUS_DATA_IN(6*32+31 downto 6*32) => trig_dout,
- BUS_DATAREADY_IN(6) => trig_ack,
- BUS_WRITE_ACK_IN(6) => trig_ack,
- BUS_NO_MORE_DATA_IN(6) => '0',
- BUS_UNKNOWN_ADDR_IN(6) => trig_nack,
+ BUS_UNKNOWN_ADDR_IN(4) => trig_nack,
--SEU Detection
- BUS_READ_ENABLE_OUT(7) => bussed_rx.read,
- BUS_WRITE_ENABLE_OUT(7) => bussed_rx.write,
- BUS_DATA_OUT(7*32+31 downto 7*32) => bussed_rx.data,
- BUS_ADDR_OUT(7*16+15 downto 7*16) => bussed_rx.addr,
- BUS_TIMEOUT_OUT(7) => bussed_rx.timeout,
- BUS_DATA_IN(7*32+31 downto 7*32) => bussed_tx.data,
- BUS_DATAREADY_IN(7) => bussed_tx.ack,
- BUS_WRITE_ACK_IN(7) => bussed_tx.ack,
- BUS_NO_MORE_DATA_IN(7) => bussed_tx.nack,
- BUS_UNKNOWN_ADDR_IN(7) => bussed_tx.unknown,
- --Channel Debug Registers
- BUS_READ_ENABLE_OUT(8) => cdb_read_en,
- BUS_WRITE_ENABLE_OUT(8) => cdb_write_en,
- BUS_DATA_OUT(8*32+31 downto 8*32) => open,
- BUS_ADDR_OUT(8*16+6 downto 8*16) => cdb_addr,
- BUS_ADDR_OUT(8*16+15 downto 8*16+7) => open,
- BUS_TIMEOUT_OUT(8) => open,
- BUS_DATA_IN(8*32+31 downto 8*32) => cdb_data_out,
- BUS_DATAREADY_IN(8) => cdb_data_ready,
- BUS_WRITE_ACK_IN(8) => '0',
- BUS_NO_MORE_DATA_IN(8) => '0',
- BUS_UNKNOWN_ADDR_IN(8) => cdb_invalid,
+ BUS_READ_ENABLE_OUT(5) => bussed_rx.read,
+ BUS_WRITE_ENABLE_OUT(5) => bussed_rx.write,
+ BUS_DATA_OUT(5*32+31 downto 5*32) => bussed_rx.data,
+ BUS_ADDR_OUT(5*16+15 downto 5*16) => bussed_rx.addr,
+ BUS_TIMEOUT_OUT(5) => bussed_rx.timeout,
+ BUS_DATA_IN(5*32+31 downto 5*32) => bussed_tx.data,
+ BUS_DATAREADY_IN(5) => bussed_tx.ack,
+ BUS_WRITE_ACK_IN(5) => bussed_tx.ack,
+ BUS_NO_MORE_DATA_IN(5) => bussed_tx.nack,
+ BUS_UNKNOWN_ADDR_IN(5) => bussed_tx.unknown,
STAT_DEBUG => open
);
- PROC_TDC_CTRL_REG : process
- variable pos : integer;
- begin
- wait until rising_edge(clk_100_i);
- pos := to_integer(unsigned(tdc_ctrl_addr))*32;
- tdc_ctrl_data_out <= tdc_ctrl_reg(pos+31 downto pos);
- last_tdc_ctrl_read <= tdc_ctrl_read;
- if tdc_ctrl_write = '1' then
- tdc_ctrl_reg(pos+31 downto pos) <= tdc_ctrl_data_in;
- end if;
- end process;
-
---------------------------------------------------------------------------
-- SPI / Flash
---------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
- THE_TDC : TDC
+ THE_TDC : TDC_record
generic map (
- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels
- STATUS_REG_NR => 22, -- Number of status regs
- CONTROL_REG_NR => 6, -- Number of control regs - higher than 8 check tdc_ctrl_addr
- TDC_VERSION => TDC_VERSION, -- TDC version number
+ CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module
+ STATUS_REG_NR => 21, -- Number of status regs
DEBUG => c_YES,
SIMULATION => c_NO)
port map (
- RESET => reset_i,
- CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
- CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC
- TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width
- TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width
- --
+ RESET => reset_i,
+ CLK_TDC => CLK_PCLK_LEFT,
+ CLK_READOUT => clk_100_i, -- Clock for the readout
+ REFERENCE_TIME => timing_trg_received_i, -- Reference time input
+ HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
+ HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC
-- Trigger signals from handler
- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
- SPIKE_DETECTED_IN => trg_spike_detected_i,
- MULTI_TMG_TRG_IN => trg_multiple_trg_i,
- SPURIOUS_TRG_IN => trg_spurious_trg_i,
- --
- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
- TRG_CODE_IN => trg_code_i, --
- TRG_INFORMATION_IN => trg_information_i, --
- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
- --
- --Response to handler
- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
- DATA_OUT => fee_data_i, -- tdc data
- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
- --
- --Hit Counter Bus
- HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe
- HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe
- HCB_ADDR_IN => hitreg_addr, -- bus address
- HCB_DATA_OUT => hitreg_data_out, -- bus data
- HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe
- HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr
- --Status Registers Bus
- SRB_READ_EN_IN => srb_read_en, -- bus read en strobe
- SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe
- SRB_ADDR_IN => srb_addr, -- bus address
- SRB_DATA_OUT => srb_data_out, -- bus data
- SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe
- SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr
- --Channel Debug Bus
- CDB_READ_EN_IN => cdb_read_en, -- bus read en strobe
- CDB_WRITE_EN_IN => cdb_write_en, -- bus write en strobe
- CDB_ADDR_IN => cdb_addr, -- bus address
- CDB_DATA_OUT => cdb_data_out, -- bus data
- CDB_DATAREADY_OUT => cdb_data_ready, -- bus data ready strobe
- CDB_UNKNOWN_ADDR_OUT => cdb_invalid, -- bus invalid addr
- --Encoder Start Registers Bus
- ESB_READ_EN_IN => esb_read_en, -- bus read en strobe
- ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe
- ESB_ADDR_IN => esb_addr, -- bus address
- ESB_DATA_OUT => esb_data_out, -- bus data
- ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe
- ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr
- --Fifo Write Registers Bus
- EFB_READ_EN_IN => efb_read_en, -- bus read en strobe
- EFB_WRITE_EN_IN => efb_write_en, -- bus write en strobe
- EFB_ADDR_IN => efb_addr, -- bus address
- EFB_DATA_OUT => efb_data_out, -- bus data
- EFB_DATAREADY_OUT => efb_data_ready, -- bus data ready strobe
- EFB_UNKNOWN_ADDR_OUT => efb_invalid, -- bus invalid addr
- --Lost Hit Registers Bus
- LHB_READ_EN_IN => lhb_read_en, -- bus read en strobe
- LHB_WRITE_EN_IN => lhb_write_en, -- bus write en strobe
- LHB_ADDR_IN => lhb_addr, -- bus address
- LHB_DATA_OUT => lhb_data_out, -- bus data
- LHB_DATAREADY_OUT => lhb_data_ready, -- bus data ready strobe
- LHB_UNKNOWN_ADDR_OUT => lhb_invalid, -- bus invalid addr
- --
- LOGIC_ANALYSER_OUT => logic_analyser_i,
- CONTROL_REG_IN => tdc_ctrl_reg);
-
+ BUSRDO_RX => readout_rx,
+ BUSRDO_TX => readout_tx(0),
+ -- Slow control bus
+ BUS_RX => bustdc_rx,
+ BUS_TX => bustdc_tx,
+ -- Dubug signals
+ INFO_IN => timer,
+ LOGIC_ANALYSER_OUT => logic_analyser_i
+ );
gen_select_fast_mapping : if USE_HPTDC_FASTMODE_PINOUT = 1 generate
-- For single edge measurements
- gen_single : if USE_DOUBLE_EDGE = 0 generate
+ gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
hit_in_i <= inputs_i;
end generate;
-- For ToT Measurements
- gen_double : if USE_DOUBLE_EDGE = 1 generate
+ gen_double : if DOUBLE_EDGE_TYPE = 2 generate
Gen_Hit_In_Signals : for i in 1 to 32 generate
hit_in_i(i*2-1) <= inputs_i(i-1);
hit_in_i(i*2) <= not inputs_i(i-1);
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
+# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_i_c 2x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
+# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_i_c TO CLKNET clk_100_i_c 5x;
system("ln -s ../../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
#edit the lpf file according to tdc settings
- system("unlink compile_tdc.pl");
- system("ln -s ../../tdc/scripts/compile_tdc.pl");
- system ("./compile_tdc.pl", $WORKDIR, $TOPNAME, "config");
+ system("unlink $WORKDIR/compile_tdc.pl");
+ system("ln -s ../../../tdc/scripts/compile_tdc.pl $WORKDIR/");
+ system ("./$WORKDIR/compile_tdc.pl", $WORKDIR, $TOPNAME, "config");
}
if ($include_GBE) {
chdir $WORKDIR;
if ($syn==1 || $all==1) {
- system ("./../compile_tdc.pl", $WORKDIR, $TOPNAME, "prj") if ($include_TDC); ## edit prj file for different designs
+ system ("./compile_tdc.pl", $WORKDIR, $TOPNAME, "prj") if ($include_TDC); ## edit prj file for different designs
print GREEN, "Starting synthesis process...\n\n", RESET;
$c="$synplify_path/bin/synplify_premier_dp -batch ../$TOPNAME.prj";
use strict;
use Cwd;
-my @compile_list = ("trb3_periph_32PinAddOn", "trb3_periph_ADA", "trb3_periph_gpin", "trb3_periph_padiwa",
-# "trb3_periph_hadesstart", "cbmtof", "trb3sc", "dirich",
-# "trb3_periph_hub", "trb3_central_cts",
- );
+my %compile_list=(
+ trb3_periph_32PinAddOn =>{path=>"../../trb3/32PinAddOn"},
+ trb3_periph_ADA =>{path=>"../../trb3/ADA_Addon"},
+ trb3_periph_gpin =>{path=>"../../trb3/gpin"},
+ trb3_periph_padiwa =>{path=>"../../trb3/wasa"},
+# trb3_periph_hadesstart =>{path=>"../../trb3/hadesstart"},
+# trb3_periph_hub =>{path=>"../../trb3/hub"},
+# trb3_central_cts =>{path=>"../../trb3/cts"},
+ cbmtof =>{path=>"../../trb3/cbmtof"},
+# trb3sc =>{path=>"../../trb3sc/tdctemplate"},
+# dirich =>{path=>"../../dirich/dirich"},
+ );
+
+
+
+###################################################################################
+#Options for the script
+my $help = $ARGV[0];
+
+if ($help eq "-h") {
+ system("./compile.pl -h");
+ exit;
+}
+
my $cwd = getcwd();
+my $tab = 1;
-for my $i (0 .. $#compile_list) {
- my $design = $compile_list[$i];
- my $tab = $i+1;
+for my $design (sort keys %compile_list) {
+ my $path = $compile_list{$design}{path};
+ print "$path\n";
print "\033]777;tabbedex;new_tab\007";
sleep 0.1;
print "\033]777;tabbedex;make_current;$tab\007";
print "\033]777;tabbedex;set_tab_name;$design\007";
- print "\033]777;tabbedex;interactive_command;cd $cwd\007";
- print "\033]777;tabbedex;interactive_command;./compile.pl -d $design\007";
+ print "\033]777;tabbedex;interactive_command;cd $cwd; cd $path\007";
+ print "\033]777;tabbedex;interactive_command;./compile.pl @ARGV\007";
sleep 1;
+ $tab = $tab+1;
}
+++ /dev/null
-config_compile_gsi.pl
\ No newline at end of file
+++ /dev/null
-TOPNAME => "trb3sc_tdctemplate",
-project_path => "../trb3sc/tdctemplate",
-lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
-lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.5_x64',
-synplify_path => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
-synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
-#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-
-nodelist_file => 'nodelist_frankfurt.txt',
-par_options => '../../base/trb3_periph.p2t',
-
-
-#Include only necessary lpf files
-#pinout_file => '', #name of pin-out file, if not equal TOPNAME
-include_TDC => 0,
-include_GBE => 0,
-
-#Report settings
-firefox_open => 0,
-twr_number_of_errors => 20,
-
+++ /dev/null
-TOPNAME => "trb3_periph_32PinAddOn",
-project_path => "32PinAddOn",
-lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
-lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/opt/lattice/diamond/3.6_x64',
-synplify_path => '/opt/synplicity/K-2015.09',
-#synplify_command => "/opt/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
-synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
-
-nodelist_file => '../nodes_lxhadeb07.txt',
-par_options => '../../base/trb3_periph.p2t',
-
-#Include only necessary lpf files
-include_TDC => 1,
-include_GBE => 0,
-
-#Report settings
-firefox_open => 0,
-twr_number_of_errors => 20,
--TDC settings
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
- constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --change names in constraints file
- --ring buffer size:
- -- 0->32
- -- 1->64
- -- 2->96
- -- 3->128
- -- 5->64dyn
- -- 7->128dyn
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size
+ -- mode: 0, 1, 2, 3, 7
+ -- size: 32, 64, 96, 128, dyn
+ constant TDC_DATA_FORMAT : integer range 0 to 15 := 0; --type of data format for the TDC
+ -- 0: Single fine time as the sum of the two transitions
+ -- 1: Double fine time, individual transitions
+ -- 13: Debug - single fine time and the chain for the 0x3ff hits
+ -- 14: Debug - single fine time and the ROM addresses for the two transitions
+ -- 15: Debug - complete carry chain dump
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 1024; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+Familyname => 'LatticeECP3',
+Devicename => 'LFE3-150EA',
+Package => 'FPBGA672',
+Speedgrade => '8',
+
TOPNAME => "trb3_periph_padiwa",
lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/opt/lattice/diamond/3.5_x64/',
-synplify_path => '/opt/synplicity/J-2015.03-SP1',
-#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
-synplify_command => "/opt/synplicity/J-2015.03-SP1/bin/synplify_premier_dp",
+lattice_path => '/opt/lattice/diamond/3.6_x64',
+synplify_path => '/opt/synplicity/K-2015.09',
+#synplify_command => "/opt/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
nodelist_file => '../nodes_lxhadeb07.txt',
+par_options => '../base/trb3_periph_padiwa.p2t',
+#Include only necessary lpf files
include_TDC => 1,
include_GBE => 0,
-
+#Report settings
twr_number_of_errors => 20,
firefox_open => 0,
-w
--i 15
--l 5
--n 1
-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
-s 12
--t 10
+-t 1
-c 1
-e 2
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
+-i 15
-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
+
+
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+# load configuration derived from config.vhd by compile_constraints.pl
+source workdir/trb3_periph_padiwa_prjconfig.tcl
# implementation: "workdir"
impl -add workdir -type fpga
add_file -vhdl -lib work "../base/code/input_statistics.vhd"
add_file -vhdl -lib work "../base/code/sedcheck.vhd"
-#add_file -vhdl -lib work "tdc_release/Adder_304.vhd"
+
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
-#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
-#add_file -vhdl -lib work "tdc_release/Channel_fast.vhd"
add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
-#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-#add_file -vhdl -lib work "tdc_release/Readout.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-#add_file -vhdl -lib work "tdc_release/TDC.vhd"
add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
add_file -vhdl -lib work "tdc_release/up_counter.vhd"
-
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_DynThr_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_DynThr_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
+
+if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+}
+if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+}
+
add_file -vhdl -lib work "trb3_periph_padiwa.vhd"
-MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
-MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
+# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
+# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET CLK_PCLK_LEFT_c TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/*" CLKNET clk_100_internal 2x;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x;
+# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" CLKNET clk_100_internal TO CLKNET clk_100_internal 5x;
jspc29 / trb3.git / commitdiff