-- use sc.components.all;
entity hub is
generic (
- HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 4
+ HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 16
);
port (
LVDS_CLK_200P : in std_logic;
SFP_OUT_N : out std_logic_vector(15 downto 0);
SFP_OUT_P : out std_logic_vector(15 downto 0);
--tempsens
- FS_PE_11 : inout std_logic;
+ FS_PE_11 : inout std_logic--;
+ --etrax_interface
+ -- FS_PE : inout std_logic_vector(17 downto 5)
---------------------------------------------------------------------------
-- sim
- ---------------------------------------------------------------------------
- OPT_DATA_IN : in std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_OUT : out std_logic_vector(16*HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
+-- ---------------------------------------------------------------------------
+-- OPT_DATA_IN : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+-- OPT_DATA_OUT : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0);
+-- OPT_DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+-- OPT_DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0)
);
end hub;
architecture hub of hub is
MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0);
MED_STAT_OP : out std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0);
MED_CTRL_OP : in std_logic_vector (HOW_MANY_CHANNELS*16-1 downto 0)
-
);
end component;
component pll_ref
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
- MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0));
+ MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
+ ETRAX_CTRL : in std_logic_vector (15 downto 0)
+ );
end component;
component simpleupcounter_16bit
port (
end component;
component DCS
-- synthesis translate_off
+ --sim
generic (
DCSMODE : string := "LOW_LOW");
-- synthesis translate_on
SEL : in std_logic;
DCSOUT : out std_logic);
end component;
+ component hub_etrax_interface
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS : inout std_logic_vector(17 downto 5);
+ EXTERNAL_ADDRESS : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
+ EXTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
+ EXTERNAL_ACK : out std_logic;
+ EXTERNAL_VALID : in std_logic;
+ EXTERNAL_MODE : out std_logic_vector(7 downto 0);
+ FPGA_REGISTER_00 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_01 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_02 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_03 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_04 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_05 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_06 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_07 : out std_logic_vector(31 downto 0);
+ FPGA_REGISTER_08 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_09 : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0A : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0B : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0C : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0D : in std_logic_vector(31 downto 0);
+ FPGA_REGISTER_0E : out std_logic_vector(31 downto 0);
+ EXTERNAL_RESET : out std_logic);
+ end component;
-----------------------------------------------------------------------------
-- FLEXI_PCS
-----------------------------------------------------------------------------
signal hub_register_0a_i : std_logic_vector(7 downto 0);
signal hub_register_0b_i : std_logic_vector(7 downto 0);
signal hub_register_0c_i : std_logic_vector(7 downto 0);
- signal hub_register_0d_i : std_logic_vector(7 downto 0);
- signal hub_register_0e_i : std_logic_vector(7 downto 0);
+ signal hub_register_0d_i : std_logic_vector(7 downto 0):=x"06";
+ signal hub_register_0e_i : std_logic_vector(7 downto 0):=x"00";
signal hub_register_0f_i : std_logic_vector(7 downto 0);
signal hub_register_10_i : std_logic_vector(7 downto 0);
signal hub_register_11_i : std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- other
-----------------------------------------------------------------------------
- signal hub_register_0e_and_0d : std_logic_vector(15 downto 0);
+ signal hub_register_0e_and_0d : std_logic_vector(15 downto 0) := x"0006";
signal cv_counter : std_logic_vector(31 downto 0);
signal cv_countera : std_logic_vector(31 downto 0);
signal serdes_ref_clk : std_logic;
signal hub_register_0e_and_0d_synch : std_logic_vector(15 downto 0);
signal test_signal : std_logic_vector(1 downto 0);
signal pulse_test : std_logic;
- signal saved_ready : std_logic_vector(HOW_MANY_CHANNELS-2 downto 0);
- signal all_ready : std_logic;
+ signal saved_lvl1_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
+ signal saved_lvl2_ready : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0):=(others => '0');
+ signal all_lvl1_ready : std_logic;
+ signal all_lvl2_ready : std_logic;
signal flexi_pcs_ref_clk : std_logic;
signal lok_i : std_logic_vector(16 downto 1);
signal not_used_lok : std_logic_vector(15 downto 0);
signal channels_locked : std_logic_vector(16 downto 1);
signal switch_rx_clk : std_logic;
signal lock_pattern : std_logic_vector(HOW_MANY_CHANNELS-1 downto 0);
+ signal all_lvl1_ready_delay1 : std_logic;
+ signal all_lvl1_ready_delay2 : std_logic;
+ signal all_lvl2_ready_delay1 : std_logic;
+ signal all_lvl2_ready_delay2 : std_logic;
+ -- etrax interface
+ signal external_address_i : std_logic_vector(31 downto 0);
+ signal external_data_out_i : std_logic_vector(31 downto 0);
+ signal external_data_in_i : std_logic_vector(31 downto 0);
+ signal external_ack_i : std_logic;
+ signal external_valid_i : std_logic;
+ signal external_mode_i : std_logic_vector(7 downto 0);
+ signal data_valid_i : std_logic;
+ signal debug_register_00_i : std_logic_vector(7 downto 0);
+ signal test2 : std_logic_vector(1 downto 0);
+ signal med_read_counter : std_logic_vector(3 downto 0);
+ -- simulation
+ signal rx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal tx_k_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal cv_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0);
+ signal rx_clk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0);
+ signal ref_pclk_sim : std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0);
+
begin
GLOBAL_RESET: process(LVDS_CLK_200P,global_reset_cnt)
begin
test_signal(1) <= pulse_test;
test_signal(0) <= pulse_test;
REF_CLK_SELECT: DCS
- -- synthesis translate_off
+ -- synthesis translate_off
+ --sim
generic map (
DCSMODE => DCSMODE)
-- synthesis translate_on
end if;
end if;
end process SWITCH_CLOCK;
- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
- begin
- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
- end generate LOK_STATUS_DIOD_EN;
+-- LOK_STATUS_DIOD_EN : for synch_fsm_state in 0 to HOW_MANY_CHANNELS-1 generate
+-- begin
+-- used_channels_locked(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+-- end generate LOK_STATUS_DIOD_EN;
--lock_pattern(15 downto HOW_MANY_CHANNELS) <= lok_i(16 downto HOW_MANY_CHANNELS +1);
QUAD_GENERATE : for bit_index in 0 to ((HOW_MANY_CHANNELS+3)/4-1) generate
ref_pclk => ref_pclk(bit_index)
);
end generate QUAD_GENERATE;
- word_align_en <= not rx_rst_i;
+ -- word_align_en <= not rx_rst_i;
+ --sim
+-- rx_k_sim(0) <= not OPT_DATA_VALID_IN(0);
+-- rx_k_sim(1) <= '0';
+-- rx_k_sim(2) <= not OPT_DATA_VALID_IN(1);
+-- rx_k_sim(3) <= '0';
+-- rx_k_sim(4) <= not OPT_DATA_VALID_IN(2);
+-- rx_k_sim(5) <= '0';
+
+-- OPT_DATA_VALID_OUT(0) <= not tx_k_sim(0);
+-- OPT_DATA_VALID_OUT(1) <= not tx_k_sim(2);
+-- OPT_DATA_VALID_OUT(2) <= not tx_k_sim(4);
+-- cv_sim <= (others => '0');
+-- rx_clk_sim <= (others => LVDS_CLK_200P);
+-- ref_pclk_sim <= (others => LVDS_CLK_200P);
+ --end sim
FLEXI_PCS_INT : flexi_PCS_synch
generic map (
HOW_MANY_CHANNELS => HOW_MANY_CHANNELS)
port map (
SYSTEM_CLK => LVDS_CLK_200P,
- CLK => ref_pclk,--,
- RX_CLK => rx_clk_i,
+ CLK => ref_pclk,--,ref_pclk_sim,--ref_pclk,--,sim
+ RX_CLK => rx_clk_i,--rx_clk_sim,--rx_clk_i,--sim
RESET => global_reset_i,
- RXD => rxd_i,
+ RXD => rxd_i,--OPT_DATA_IN,--rxd_i,--sim
MED_DATA_OUT => med_data_out_i,
- RX_K => rx_k_i,
+ RX_K => rx_k_i,--rx_k_sim,--rx_k_i,--sim
RX_RST => rx_rst_i,
- CV => cv_i,
+ CV => cv_i,--cv_sim,--cv_i,--sim
MED_DATA_IN => med_data_in_i,
- TXD_SYNCH => txd_synch_i,
- TX_K => tx_k_i,
+ TXD_SYNCH => txd_synch_i,--OPT_DATA_OUT,--txd_synch_i,--sim
+ TX_K => tx_k_i, --tx_k_sim,--tx_k_i, --sim
FLEXI_PCS_SYNCH_STATUS => flexi_pcs_synch_status_i,
MED_DATAREADY_IN => med_dataready_in_i,--data_valid_in_i,--med_dataready_in_i,
MED_DATAREADY_OUT => med_dataready_out_i,
MED_STAT_OP => med_stat_op_i,
MED_CTRL_OP => med_ctrl_op_i
);
- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
+-- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
-- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0);
- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
+-- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
-- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0);
--- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
--- med_read_in_i <= (others => '1'); --test
+-- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
+-- med_read_in_i <= (others => '1'); --test
+
+ HUB_API: trb_net16_hub_base
+ port map (
+ CLK => LVDS_CLK_200P,
+ RESET => global_reset_i,
+ CLK_EN => '1',
+ MED_DATAREADY_OUT => med_dataready_in_i,
+ MED_DATA_OUT => med_data_in_i,
+ MED_PACKET_NUM_OUT => med_packet_num_in_i,
+ MED_READ_IN => med_read_out_i,
+ MED_DATAREADY_IN => med_dataready_out_i,
+ MED_DATA_IN => med_data_out_i,
+ MED_PACKET_NUM_IN => med_packet_num_out_i,
+ MED_READ_OUT => med_read_in_i,
+ MED_ERROR_IN => med_error_out_i,
+ MED_STAT_OP => med_stat_op_i,
+ MED_CTRL_OP => med_ctrl_op_i,
+ APL_DATA_IN => (others => '0'),
+ APL_PACKET_NUM_IN => (others => '0'),
+ APL_DATAREADY_IN => (others => '0'),
+ APL_READ_OUT => open,
+ APL_SHORT_TRANSFER_IN => (others => '0'),
+ APL_DTYPE_IN => (others => '0'),
+ APL_ERROR_PATTERN_IN => (others => '0'),
+ APL_SEND_IN => (others => '0'),
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ APL_DATA_OUT => open,
+ APL_PACKET_NUM_OUT => open,
+ APL_TYP_OUT => open,
+ APL_DATAREADY_OUT => open,
+ APL_READ_IN => (others => '0'),
+ APL_RUN_OUT => open,
+ APL_MY_ADDRESS_IN => (others => '0'),
+ APL_SEQNR_OUT => open,
+ TRG_GOT_TRIGGER_OUT => open,
+ TRG_ERROR_PATTERN_OUT => open,
+ TRG_DTYPE_OUT => open,
+ TRG_SEQNR_OUT => open,
+ TRG_ERROR_PATTERN_IN => (others => '0'),
+ TRG_RELEASE_IN => (others => '0'),
+ ONEWIRE => FS_PE_11,
+ HUB_STAT_CHANNEL => hub_stat_channel_i,
+ HUB_STAT_GEN => hub_stat_gen_i,
+ MPLEX_CTRL => mplex_ctrl_i,
+ MPLEX_STAT => open,
+ ETRAX_CTRL => hub_register_0e_and_0d
+ );
- HUB_API: trb_net16_hub_base
- port map (
- CLK => ref_pclk(0),
- RESET => global_reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_in_i,
- MED_DATA_OUT => med_data_in_i,
- MED_PACKET_NUM_OUT => med_packet_num_in_i,
- MED_READ_IN => med_read_out_i,
- MED_DATAREADY_IN => med_dataready_out_i,
- MED_DATA_IN => med_data_out_i,
- MED_PACKET_NUM_IN => med_packet_num_out_i,
- MED_READ_OUT => med_read_in_i,
- MED_ERROR_IN => med_error_out_i,
- MED_STAT_OP => med_stat_op_i,
- MED_CTRL_OP => med_ctrl_op_i,
- APL_DATA_IN => (others => '0'),
- APL_PACKET_NUM_IN => (others => '0'),
- APL_DATAREADY_IN => (others => '0'),
- APL_READ_OUT => open,
- APL_SHORT_TRANSFER_IN => (others => '0'),
- APL_DTYPE_IN => (others => '0'),
- APL_ERROR_PATTERN_IN => (others => '0'),
- APL_SEND_IN => (others => '0'),
- APL_TARGET_ADDRESS_IN => (others => '0'),
- APL_DATA_OUT => open,
- APL_PACKET_NUM_OUT => open,
- APL_TYP_OUT => open,
- APL_DATAREADY_OUT => open,
- APL_READ_IN => (others => '0'),
- APL_RUN_OUT => open,
- APL_MY_ADDRESS_IN => (others => '0'),
- APL_SEQNR_OUT => open,
- TRG_GOT_TRIGGER_OUT => open,
- TRG_ERROR_PATTERN_OUT => open,
- TRG_DTYPE_OUT => open,
- TRG_SEQNR_OUT => open,
- TRG_ERROR_PATTERN_IN => (others => '0'),
- TRG_RELEASE_IN => (others => '0'),
- ONEWIRE => FS_PE_11,
- HUB_STAT_CHANNEL => hub_stat_channel_i,
- HUB_STAT_GEN => hub_stat_gen_i,
- MPLEX_CTRL => mplex_ctrl_i,
- MPLEX_STAT => open
- );
+ TRB_HUB_INT : trb_hub_interface
+ port map (
+ CLK => ref_pclk(0),
+ RESET => ADO_TTL(0),
+ STROBE => ADO_TTL(9),
+ internal_data_in => ADO_TTL(18 downto 11),
+ internal_data_out => ADO_TTL(42 downto 35),
+ internal_address => ADO_TTL(34 downto 19),
+ internal_mode => ADO_TTL(10),
+ VALID_DATA_SENT => ADO_TTL(8),
+ HUB_REGISTER_00 => hub_register_00_i,
+ HUB_REGISTER_01 => hub_register_01_i,
+ HUB_REGISTER_02 => hub_register_02_i,
+ HUB_REGISTER_03 => hub_register_03_i,
+ HUB_REGISTER_04 => hub_register_04_i,
+ HUB_REGISTER_05 => hub_register_05_i,
+ HUB_REGISTER_06 => hub_register_06_i,
+ HUB_REGISTER_07 => hub_register_07_i,
+ HUB_REGISTER_08 => hub_register_08_i,
+ HUB_REGISTER_09 => hub_register_09_i,
+ HUB_REGISTER_0a => hub_register_0a_i,
+ HUB_REGISTER_0b => hub_register_0b_i,
+ HUB_REGISTER_0c => hub_register_0c_i,
+ HUB_REGISTER_0d => hub_register_0d_i,
+ HUB_REGISTER_0e => hub_register_0e_i,
+ HUB_REGISTER_0f => hub_register_0f_i,
+ HUB_REGISTER_10 => hub_register_10_i,
+ HUB_REGISTER_11 => hub_register_11_i,
+ HUB_REGISTER_12 => hub_register_12_i,
+ HUB_REGISTER_13 => hub_register_13_i,
+ HUB_REGISTER_14 => hub_register_14_i,
+ HUB_REGISTER_15 => hub_register_15_i,
+ HUB_REGISTER_16 => hub_register_16_i
+ );
+-------------------------------------------------------------------------------
+-- Just lvl1 and lvl2 without trbnet
+-------------------------------------------------------------------------------
+-- CONNECT_ALL: for channel_nr in 1 to HOW_MANY_CHANNELS -1 generate
+-- med_dataready_in_i(channel_nr) <= med_dataready_out_i(0);
+-- med_data_in_i(channel_nr*16+15 downto channel_nr*16) <= med_data_out_i(15 downto 0);
+-- SAVE_LVL1_DATA_READY: process(LVDS_CLK_200P, global_reset_i, med_dataready_out_i, med_data_out_i)
+-- begin
+-- if rising_edge(LVDS_CLK_200P) then
+-- if global_reset_i = '1' or all_lvl1_ready = '1' or all_lvl1_ready_delay2 = '1' then
+-- saved_lvl1_ready(channel_nr) <= '0';
+-- elsif med_dataready_out_i(channel_nr) = '1' and med_data_out_i(channel_nr*16+15 downto channel_nr*16+12) = x"1" and hub_register_0e_and_0d(channel_nr) = '1'then
+-- saved_lvl1_ready(channel_nr) <= '1';
+-- end if;
+-- end if;
+-- end process SAVE_LVL1_DATA_READY;
+-- SAVE_LVL2_DATA_READY: process(LVDS_CLK_200P, global_reset_i, med_dataready_out_i, med_data_out_i)
+-- begin
+-- if rising_edge(LVDS_CLK_200P) then
+-- if global_reset_i = '1' or all_lvl2_ready = '1' or all_lvl2_ready_delay2 = '1' then
+-- saved_lvl2_ready(channel_nr) <= '0';
+-- elsif med_dataready_out_i(channel_nr) = '1' and med_data_out_i(channel_nr*16+15 downto channel_nr*16+12) = x"2" and hub_register_0e_and_0d(channel_nr) = '1'then
+-- saved_lvl2_ready(channel_nr) <= '1';
+-- end if;
+-- end if;
+-- end process SAVE_LVL2_DATA_READY;
+-- end generate CONNECT_ALL;
+
+-- SET_LVL1_LVL2_READY: process (LVDS_CLK_200P, global_reset_i)
+-- begin
+-- if rising_edge(LVDS_CLK_200P) then
+-- if global_reset_i = '1' or all_lvl1_ready_delay1 = '1' or all_lvl1_ready_delay2 = '1' or hub_register_0e_and_0d = x"0000" then -- asynchronous reset (active low)
+-- all_lvl1_ready <= '0';
+-- all_lvl2_ready <= '0';
+-- elsif saved_lvl1_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
+-- all_lvl1_ready <= '1';
+-- all_lvl2_ready <= '0';
+-- elsif saved_lvl1_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) and saved_lvl2_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
+-- all_lvl1_ready <= '1';
+-- all_lvl2_ready <= '0';
+-- elsif saved_lvl2_ready = hub_register_0e_and_0d(HOW_MANY_CHANNELS-1 downto 0) then
+-- all_lvl1_ready <= '0';
+-- all_lvl2_ready <= '1';
+-- else
+-- all_lvl1_ready <= '0';
+-- all_lvl2_ready <= '0';
+-- end if;
+-- end if;
+-- end process SET_LVL1_LVl2_READY;
+-- DELAY_READY: process (LVDS_CLK_200P, global_reset_i)
+-- begin -- process DELAY_READY
+-- if rising_edge(LVDS_CLK_200P) then
+-- if global_reset_i = '1' then -- asynchronous reset (active low)
+-- all_lvl1_ready_delay1 <= '0';
+-- all_lvl1_ready_delay2 <= '0';
+-- all_lvl2_ready_delay1 <= '0';
+-- all_lvl2_ready_delay2 <= '0';
+-- else
+-- all_lvl1_ready_delay1 <= all_lvl1_ready;
+-- all_lvl1_ready_delay2 <= all_lvl1_ready_delay1;
+-- all_lvl2_ready_delay1 <= all_lvl2_ready;
+-- all_lvl2_ready_delay2 <= all_lvl2_ready_delay1;
+
+-- end if;
+-- end if;
+-- end process DELAY_READY;
+-- med_read_in_i(0) <= '1';--med_read_counter(3) or med_read_counter(2);
+-- -- med_dataready_in_i(0) <= all_lready;--med_dataready_out_i(1);
+-- SEND_LVL1_LVL2_ACK: process (LVDS_CLK_200P, global_reset_i)
+-- begin
+-- if rising_edge(LVDS_CLK_200P) then
+-- if global_reset_i = '1' then
+-- med_dataready_in_i(0) <= '0';
+-- med_data_in_i(15 downto 0) <= x"0000";
+-- elsif all_lvl1_ready = '1' or all_lvl1_ready_delay1 = '1' or all_lvl1_ready_delay2 = '1' then
+-- med_dataready_in_i(0) <= '1';
+-- med_data_in_i(15 downto 0) <= x"1000";
+-- elsif all_lvl2_ready = '1' or all_lvl2_ready_delay1 = '1' or all_lvl2_ready_delay2 = '1'then
+-- med_dataready_in_i(0) <= '1';
+-- med_data_in_i(15 downto 0) <= x"2000";
+-- else
+-- med_dataready_in_i(0) <= '0';
+-- med_data_in_i(15 downto 0) <= x"0000";
+-- end if;
+-- end if;
+-- end process SEND_LVL1_LVL2_ACK;
+-- med_read_in_i(HOW_MANY_CHANNELS-1 downto 1) <= (others => '1');
+
+-- -- saved_ready(0) <= '1';
+-- -- MAKE_RAED: process (LVDS_CLK_200P, global_reset_i)
+-- -- begin -- process MAKE_RAED
+-- -- if rising_edge(LVDS_CLK_200P) then
+-- -- if global_reset_i = '1' then -- asynchronous reset (active low)
+-- -- med_read_counter <= (others => '0');
+-- -- else
+-- -- med_read_counter <= med_read_counter + 1;
+-- -- end if;
+-- -- end if;
+-- -- end process MAKE_RAED;
+
+
+
+-------------------------------------------------------------------------------
+-- end "Just lvl1 without trbnet"
+-------------------------------------------------------------------------------
process (LVDS_CLK_200P, global_reset_i, med_dataready_out_i)
begin
if rising_edge(LVDS_CLK_200P) then
end if;
end process;
process (rx_clk_i(0), global_reset_i, rx_k_i(0))
-
begin
if rising_edge(rx_clk_i(0)) then
if global_reset_i = '1' then -- asynchronous reset (active low)
end if;
end process;
registered_signals(4 downto 3) <= rx_k_i(1) & rx_k_i(0);
--- TRB_HUB_INT : trb_hub_interface
--- port map (
--- CLK => ref_pclk(0),
--- RESET => global_reset_i,
--- STROBE => ADO_TTL(9),
--- internal_data_in => ADO_TTL(18 downto 11),
--- internal_data_out => ADO_TTL(42 downto 35),
--- internal_address => ADO_TTL(34 downto 19),
--- internal_mode => ADO_TTL(10),
--- VALID_DATA_SENT => ADO_TTL(8),
--- HUB_REGISTER_00 => hub_register_00_i,
--- HUB_REGISTER_01 => hub_register_01_i,
--- HUB_REGISTER_02 => hub_register_02_i,
--- HUB_REGISTER_03 => hub_register_03_i,
--- HUB_REGISTER_04 => hub_register_04_i,
--- HUB_REGISTER_05 => hub_register_05_i,
--- HUB_REGISTER_06 => hub_register_06_i,
--- HUB_REGISTER_07 => hub_register_07_i,
--- HUB_REGISTER_08 => hub_register_08_i,
--- HUB_REGISTER_09 => hub_register_09_i,
--- HUB_REGISTER_0a => hub_register_0a_i,
--- HUB_REGISTER_0b => hub_register_0b_i,
--- HUB_REGISTER_0c => hub_register_0c_i,
--- HUB_REGISTER_0d => hub_register_0d_i,
--- HUB_REGISTER_0e => hub_register_0e_i,
--- HUB_REGISTER_0f => hub_register_0f_i,
--- HUB_REGISTER_10 => hub_register_10_i,
--- HUB_REGISTER_11 => hub_register_11_i,
--- HUB_REGISTER_12 => hub_register_12_i,
--- HUB_REGISTER_13 => hub_register_13_i,
--- HUB_REGISTER_14 => hub_register_14_i,
--- HUB_REGISTER_15 => hub_register_15_i,
--- HUB_REGISTER_16 => hub_register_16_i
--- );
--- ADO_TTL(34 downto 9) <= (others => 'Z');
-
- SYNCH_DATA: process (ref_pclk(0), global_reset_i)
- begin -- process SYNCH_DATA
- if falling_edge(ref_pclk(0)) then
- if global_reset_i = '1' then
- hub_register_0a_i_synch <= (others => '0');
- hub_register_0e_and_0d_synch <= (others => '0');
- else
- hub_register_0a_i_synch <= hub_register_0a_i;
- hub_register_0e_and_0d_synch <= hub_register_0e_and_0d;
- end if;
- end if;
- end process SYNCH_DATA;
-
- hub_register_00_i <= flexi_pcs_synch_status_i(7 downto 0);
- hub_register_01_i <= hub_stat_gen_i(15 downto 8);
- hub_register_02_i <= rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
- hub_register_03_i <= rxd_i(15 downto 8); --cv_counter_ch1;
- hub_register_04_i <= hub_stat_gen_i(7 downto 0);
+-- SYNCH_DATA: process (ref_pclk(0), global_reset_i)
+-- begin -- process SYNCH_DATA
+-- if falling_edge(ref_pclk(0)) then
+-- if global_reset_i = '1' then
+-- hub_register_0a_i_synch <= (others => '0');
+-- hub_register_0e_and_0d_synch <= (others => '0');
+-- else
+-- hub_register_0a_i_synch <= hub_register_0a_i;
+-- hub_register_0e_and_0d_synch <= hub_register_0e_and_0d;
+-- end if;
+-- end if;
+-- end process SYNCH_DATA;
+
+-- hub_register_00_i(7 downto 0) <= flexi_pcs_synch_status_i(7 downto 0);
+-- hub_register_01_i(7 downto 0) <= hub_stat_gen_i(15 downto 8);
+ hub_register_02_i(7 downto 0) <= saved_lvl1_ready(7 downto 0);--rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
+ hub_register_03_i(7 downto 0) <= saved_lvl1_ready(15 downto 8);--rxd_i(15 downto 8); --cv_counter_ch1;
+ hub_register_04_i(7 downto 0) <= saved_lvl2_ready(7 downto 0);--hub_stat_gen_i(7 downto 0);
-- hub_register_04_i<= rxd_synch_i(39 downto 32);
- hub_register_05_i <= rxd_i(31 downto 24);
- hub_register_10_i <= med_data_out_i(31 downto 24);--rxd_i(7+8*16 downto 0+8*16); --; --rxd_1_a(15 downto 8);
+ hub_register_05_i(7 downto 0) <= saved_lvl2_ready(15 downto 8);--rxd_i(31 downto 24);
+ hub_register_10_i(7 downto 0) <= med_data_out_i(31 downto 24);--rxd_i(7+8*16 downto 0+8*16); --; --rxd_1_a(15 downto 8);
-- hub_register_11_i <= rxd_i(23+8*16 downto 16+8*16); --cv_counter_ch1;
-- hub_register_12_i <= rxd_i(39+8*16 downto 32+8*16);
-- hub_register_13_i <= rxd_i(63+8*16 downto 56+8*16);
-- hub_register_15_i <= flexi_pcs_synch_status_i(39+8*16 downto 32+8*16);
-- hub_register_16_i <= flexi_pcs_synch_status_i(63+8*16 downto 56+8*16);
- hub_register_06_i <= tx_k_i(1 downto 0) & med_error_out_i(5 downto 0);
- hub_register_07_i <= hub_stat_gen_i(31 downto 24);--flexi_pcs_synch_status_i(39 downto 32);
- hub_register_08_i <= hub_stat_gen_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48);
- hub_register_09_i <= med_data_out_i(23 downto 16);--x"0" & data_valid_out_i(3 downto 0);
+ hub_register_06_i(7 downto 0) <= tx_k_i(1 downto 0) & med_error_out_i(5 downto 0);
+ hub_register_07_i(7 downto 0) <= hub_stat_gen_i(31 downto 24);--flexi_pcs_synch_status_i(39 downto 32);
+ hub_register_08_i(7 downto 0) <= hub_stat_gen_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48);
+ hub_register_09_i(7 downto 0) <= med_data_out_i(23 downto 16);--x"0" & data_valid_out_i(3 downto 0);
hub_register_0e_and_0d <= hub_register_0e_i & hub_register_0d_i;
-- txd_i(15 downto 0) <= hub_register_0e_and_0d;
-- txd_i(31 downto 16) <= hub_register_0e_and_0d;
-- txd_i(47 downto 32) <= hub_register_0e_and_0d;
-- txd_i(63 downto 48) <= hub_register_0e_and_0d;
- hub_register_11_i <= hub_stat_channel_i(7 downto 0);--flexi_pcs_synch_status_i(55 downto 48);
- hub_register_12_i <= hub_stat_channel_i(15 downto 8);--flexi_pcs_synch_status_i(55 downto 48);
- hub_register_13_i <= med_dataready_out_i(0)& med_dataready_in_i(0) & med_dataready_out_i(0)®istered_signals(4 downto 0);
- hub_register_14_i <= flexi_pcs_synch_status_i (15 downto 8);
- hub_register_15_i <= x"0" & med_packet_num_out_i(3 downto 0);
+ hub_register_11_i(7 downto 0) <= hub_stat_channel_i(7 downto 0);--flexi_pcs_synch_status_i(55 downto 48);
+ hub_register_12_i(7 downto 0) <= hub_stat_channel_i(15 downto 8);--flexi_pcs_synch_status_i(55 downto 48);
+ hub_register_13_i(7 downto 0) <= med_dataready_out_i(0)& med_dataready_in_i(0) & med_dataready_out_i(0)®istered_signals(4 downto 0);
+ hub_register_14_i(7 downto 0) <= flexi_pcs_synch_status_i (15 downto 8);
+ hub_register_15_i(7 downto 0) <= x"0" & med_packet_num_out_i(3 downto 0);
-- hub_register_13_i <= hub_stat_channel_i(23 downto 16);--flexi_pcs_synch_status_i(55 downto 48);
-- hub_register_14_i <= hub_stat_channel_i(31 downto 24);--flexi_pcs_synch_status_i(55 downto 48);
-- txd_i(255 downto 64) <= hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d & hub_register_0e_and_0d &
lok_i(synch_fsm_state+1) <= not flexi_pcs_synch_status_i(2+synch_fsm_state*16);
end generate LOK_STATUS_DIOD_EN;
+ LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate
+ begin
+ hub_register_00_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16);
+ end generate LOK_STATUS_REGISTER_0;
+
+ LOK_STATUS_REGISTER_1 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 - 8) generate
+ begin
+ hub_register_01_i(synch_fsm_state) <= flexi_pcs_synch_status_i(2+synch_fsm_state*16+8*16);
+ end generate LOK_STATUS_REGISTER_1;
+
LOK_STATUS_DIOD_DIS : for not_connected in 0 to 16-HOW_MANY_CHANNELS-1 generate
begin
WHEN_NOT_ALL_EN : if HOW_MANY_CHANNELS < 16 generate
end if;
end if;
end process CV_COUNTERaab;
- RT(16 downto 8) <= cv_counter(31 downto 23);
+ RT(8) <= cv_counter(23);
+ RT(9) <= med_read_in_i(0);
+ RT(16 downto 10) <= flexi_pcs_synch_status_i(7 downto 1);
RT(2) <= flexi_pcs_ref_clk;--cv_counter(0);
RT(1) <= not switch_rx_clk;--ref_pclk(0);
RT(3) <= LVDS_CLK_200P;
- RT(4) <= cv_countera(0);
+ RT(4) <= rx_k_i(0);
- RT(5) <= serdes_ref_clk;
- RT(6) <= serdes_ref_clks;
- RT(7) <= serdes_ref_lock;
+ RT(5) <= med_dataready_out_i(0);--serdes_ref_clk;
+ RT(6) <= med_data_out_i(0);--serdes_ref_clks;
+ RT(7) <= med_data_out_i(1);--serdes_ref_lock;
---------------------------------------------------------------------------
-- simulation
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