signal bus_debug_tx_in, bus_flash_tx_in, busflash_tx, busspi_tx, busadc_tx, bussed_tx,
busuart_tx, busflashset_tx, busmon_tx, bustrig_tx, busctrl_tx : CTRLBUS_TX;
-signal spi_sdi, spi_sdo, spi_sck : std_logic;
+signal spi_sdi, spi_sdo, spi_sck : std_logic_vector(15 downto 0);
signal spi_cs : std_logic_vector(15 downto 0);
signal lcd_cs, lcd_dc, lcd_mosi, lcd_sck, lcd_rst : std_logic;
signal uart_rx, uart_tx : std_logic;
SPI_SCK_OUT => spi_sck
);
SPI_CS_OUT <= spi_cs;
- SPI_CLK_OUT <= (others => spi_sck);
- SPI_MOSI_OUT <= (others => spi_sdo);
- spi_sdi <= (HEADER_IO(4) and not spi_cs(8)) or
- (ADC_MISO and not spi_cs(7)) or
- or_all(SPI_MISO_IN and not spi_cs and x"fe7f");
+ SPI_CLK_OUT <= spi_sck;
+ SPI_MOSI_OUT <= spi_sdo;
- ADC_CLK <= not spi_sck;
+ spi_sdi <= SPI_MISO_IN(15 downto 9) & HEADER_IO(4) & ADC_MISO & SPI_MISO_IN(6 downto 0);
+
+ ADC_CLK <= not spi_sck(7);
ADC_CS <= spi_cs(7);
- ADC_MOSI <= spi_sdo;
+ ADC_MOSI <= spi_sdo(7);
busspi_tx.unknown <= '0';
end generate;
HEADER_IO(6) <= lcd_cs;
end generate;
gen_nolcdio : if INCLUDE_LCD = 0 generate
- HEADER_IO(3) <= spi_sdo;
+ HEADER_IO(3) <= spi_sdo(8);
-- HEADER_IO(4) <= ;
- HEADER_IO(5) <= spi_sck;
+ HEADER_IO(5) <= spi_sck(8);
HEADER_IO(6) <= spi_cs(8);
end generate;