new PWM generator with less ressource usage for temperature compensation

diff --git a/wasa/source/pwm.vhd b/wasa/source/pwm.vhd
index 38d2383f7d1fd774485bf5d9dd2aecc106dee037..20f0625f3b51ac5f2d91ad347ecc7fdbb8372a74 100644 (file)
--- a/wasa/source/pwm.vhd
+++ b/wasa/source/pwm.vhd
@@ -24,8 +24,8 @@ end entity;
 
 architecture pwm_arch of pwm_generator is
 
-type ram_t is array(0 to 15) of unsigned(16 downto 0);
-signal set : ram_t := (others => '0' & x"87C1");
+type ram_t is array(0 to 15) of unsigned(15 downto 0);
+signal set : ram_t := (others => x"87C1");
 signal set_tmp : ram_t;
 
 type cnt_t is array(0 to 15) of unsigned(16 downto 0);
@@ -35,25 +35,32 @@ signal last_flag : std_logic_vector(15 downto 0) := (others => '0');
 signal flag      : std_logic_vector(15 downto 0) := (others => '0');
 signal pwm_i     : std_logic_vector(15 downto 0) := (others => '0');
 
+signal i         : integer range 0 to 15 := 0;
 
 begin
 
 PROC_MEM : process begin
   wait until rising_edge(CLK);
   if WRITE_IN = '1' then
---     set(to_integer(unsigned(ADDR_IN)))(16) <= '0';
-    set(to_integer(unsigned(ADDR_IN)))(15 downto 0) <= unsigned(DATA_IN);
+    set(to_integer(unsigned(ADDR_IN))) <= unsigned(DATA_IN);
   end if;
-  DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN)))(15 downto 0));
+  DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN))));
 end process;
 
 
+GEN_REAL_VALUES : process begin
+  wait until rising_edge(CLK);
+  set_tmp(i) <= unsigned(signed(set(i)) + COMP_IN);
+  i <= i + 1;
+end process;
+
+
+
 gen_channels : for i in 0 to 15 generate
   flag(i)      <= cnt(i)(16);
   last_flag(i) <= flag(i) when rising_edge(CLK);
   pwm_i(i)     <= (last_flag(i) xor flag(i)) when rising_edge(CLK);
-  set_tmp(i)   <= unsigned(signed(set(i)) + resize(COMP_IN,17));
-  cnt(i)       <= cnt(i) + set_tmp(i) when rising_edge(CLK);
+  cnt(i)       <= cnt(i) + resize(set_tmp(i),17) when rising_edge(CLK);
 end generate;