--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_32_data" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2013 06 23 23:52:13.976" version="4.8" type="Module" synthesis="" source_format="VHDL">
+ <Package>
+ <File name="fifo_32_data.lpc" type="lpc" modified="2013 06 23 23:52:12.000"/>
+ <File name="fifo_32_data.vhd" type="top_level_vhdl" modified="2013 06 23 23:52:12.000"/>
+ <File name="fifo_32_data_tmpl.vhd" type="template_vhdl" modified="2013 06 23 23:52:12.000"/>
+ <File name="tb_fifo_32_data_tmpl.vhd" type="testbench_vhdl" modified="2013 06 23 23:52:12.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=4.8
+ModuleName=fifo_32_data
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=06/23/2013
+Time=23:52:12
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=1
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+EnECC=0
+EnFWFT=0
--- VHDL netlist generated by SCUBA Diamond_2.0_Production (151)
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
-- Module Version: 4.8
---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe -1 -pf -1 -e
+--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe 1 -pf -1 -fill -e
--- Thu Dec 6 21:58:22 2012
+-- Sun Jun 23 23:52:12 2013
library IEEE;
use IEEE.std_logic_1164.all;
RdEn: in std_logic;
Reset: in std_logic;
Q: out std_logic_vector(31 downto 0);
+ WCNT: out std_logic_vector(10 downto 0);
Empty: out std_logic;
- Full: out std_logic);
+ Full: out std_logic;
+ AlmostEmpty: out std_logic);
end fifo_32_data;
architecture Structure of fifo_32_data is
-- internal signal declarations
+ signal invout_2: std_logic;
signal invout_1: std_logic;
- signal invout_0: std_logic;
signal rden_i_inv: std_logic;
+ signal invout_0: std_logic;
+ signal cnt_con_inv: std_logic;
+ signal r_nw_inv: std_logic;
+ signal fcnt_en_inv_inv: std_logic;
signal fcnt_en: std_logic;
signal empty_i: std_logic;
signal empty_d: std_logic;
signal cmp_le_1: std_logic;
signal cmp_le_1_c: std_logic;
signal cmp_ci_1: std_logic;
- signal fcount_0: std_logic;
- signal fcount_1: std_logic;
signal co0_2: std_logic;
- signal fcount_2: std_logic;
- signal fcount_3: std_logic;
signal co1_2: std_logic;
- signal fcount_4: std_logic;
- signal fcount_5: std_logic;
signal co2_2: std_logic;
- signal fcount_6: std_logic;
- signal fcount_7: std_logic;
signal co3_2: std_logic;
signal wren_i: std_logic;
- signal fcount_8: std_logic;
- signal fcount_9: std_logic;
signal co4_2: std_logic;
signal wren_i_inv: std_logic;
- signal fcount_10: std_logic;
signal cmp_ge_d1: std_logic;
signal cmp_ge_d1_c: std_logic;
signal iwcount_0: std_logic;
signal co5_1: std_logic;
signal wcount_10: std_logic;
signal co4_3: std_logic;
- signal scuba_vhi: std_logic;
signal ircount_0: std_logic;
signal ircount_1: std_logic;
signal rcount_0: std_logic;
signal ircount_10: std_logic;
signal co5_2: std_logic;
signal rcount_10: std_logic;
- signal scuba_vlo: std_logic;
signal co4_4: std_logic;
+ signal scuba_vhi: std_logic;
+ signal cmp_ci_2: std_logic;
+ signal fcnt_en_inv: std_logic;
+ signal r_nw: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_5: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_5: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_5: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_5: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal co4_5: std_logic;
+ signal fcount_10: std_logic;
+ signal ae_d: std_logic;
+ signal ae_d_c: std_logic;
+ signal scuba_vlo: std_logic;
-- local component declarations
component AGEB2
attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_32_data.lpc";
attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is "";
attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC";
+ attribute GSR of FF_35 : label is "ENABLED";
attribute GSR of FF_34 : label is "ENABLED";
attribute GSR of FF_33 : label is "ENABLED";
attribute GSR of FF_32 : label is "ENABLED";
attribute GSR of FF_1 : label is "ENABLED";
attribute GSR of FF_0 : label is "ENABLED";
attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
- AND2_t3: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+ AND2_t4: AND2
+ port map (A=>WrEn, B=>invout_2, Z=>wren_i);
- INV_3: INV
- port map (A=>full_i, Z=>invout_1);
+ INV_8: INV
+ port map (A=>full_i, Z=>invout_2);
- AND2_t2: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+ AND2_t3: AND2
+ port map (A=>RdEn, B=>invout_1, Z=>rden_i);
- INV_2: INV
- port map (A=>empty_i, Z=>invout_0);
+ INV_7: INV
+ port map (A=>empty_i, Z=>invout_1);
- AND2_t1: AND2
+ AND2_t2: AND2
port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
- XOR2_t0: XOR2
+ XOR2_t1: XOR2
port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
- INV_1: INV
+ INV_6: INV
port map (A=>rden_i, Z=>rden_i_inv);
- INV_0: INV
+ INV_5: INV
port map (A=>wren_i, Z=>wren_i_inv);
LUT4_1: ROM16X1A
port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
AD0=>full_i, DO0=>full_d);
+ AND2_t0: AND2
+ port map (A=>rden_i, B=>invout_0, Z=>r_nw);
+
+ INV_4: INV
+ port map (A=>wren_i, Z=>invout_0);
+
+ INV_3: INV
+ port map (A=>fcnt_en, Z=>fcnt_en_inv);
+
+ INV_2: INV
+ port map (A=>cnt_con, Z=>cnt_con_inv);
+
+ INV_1: INV
+ port map (A=>r_nw, Z=>r_nw_inv);
+
+ INV_0: INV
+ port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv);
+
pdp_ram_0_0_1: DP16KC
generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000",
WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED",
DOB13=>Q(31), DOB14=>open, DOB15=>open, DOB16=>open,
DOB17=>open);
- FF_34: FD1P3DX
+ FF_35: FD1P3DX
port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_0);
- FF_33: FD1P3DX
+ FF_34: FD1P3DX
port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_1);
- FF_32: FD1P3DX
+ FF_33: FD1P3DX
port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_2);
- FF_31: FD1P3DX
+ FF_32: FD1P3DX
port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_3);
- FF_30: FD1P3DX
+ FF_31: FD1P3DX
port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_4);
- FF_29: FD1P3DX
+ FF_30: FD1P3DX
port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_5);
- FF_28: FD1P3DX
+ FF_29: FD1P3DX
port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_6);
- FF_27: FD1P3DX
+ FF_28: FD1P3DX
port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_7);
- FF_26: FD1P3DX
+ FF_27: FD1P3DX
port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_8);
- FF_25: FD1P3DX
+ FF_26: FD1P3DX
port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_9);
- FF_24: FD1P3DX
+ FF_25: FD1P3DX
port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset,
Q=>fcount_10);
- FF_23: FD1S3BX
+ FF_24: FD1S3BX
port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
- FF_22: FD1S3DX
+ FF_23: FD1S3DX
port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
- FF_21: FD1P3DX
+ FF_22: FD1P3DX
port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_0);
- FF_20: FD1P3DX
+ FF_21: FD1P3DX
port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_1);
- FF_19: FD1P3DX
+ FF_20: FD1P3DX
port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_2);
- FF_18: FD1P3DX
+ FF_19: FD1P3DX
port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_3);
- FF_17: FD1P3DX
+ FF_18: FD1P3DX
port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_4);
- FF_16: FD1P3DX
+ FF_17: FD1P3DX
port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_5);
- FF_15: FD1P3DX
+ FF_16: FD1P3DX
port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_6);
- FF_14: FD1P3DX
+ FF_15: FD1P3DX
port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_7);
- FF_13: FD1P3DX
+ FF_14: FD1P3DX
port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_8);
- FF_12: FD1P3DX
+ FF_13: FD1P3DX
port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_9);
- FF_11: FD1P3DX
+ FF_12: FD1P3DX
port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset,
Q=>wcount_10);
- FF_10: FD1P3DX
+ FF_11: FD1P3DX
port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_0);
- FF_9: FD1P3DX
+ FF_10: FD1P3DX
port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_1);
- FF_8: FD1P3DX
+ FF_9: FD1P3DX
port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_2);
- FF_7: FD1P3DX
+ FF_8: FD1P3DX
port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_3);
- FF_6: FD1P3DX
+ FF_7: FD1P3DX
port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_4);
- FF_5: FD1P3DX
+ FF_6: FD1P3DX
port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_5);
- FF_4: FD1P3DX
+ FF_5: FD1P3DX
port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_6);
- FF_3: FD1P3DX
+ FF_4: FD1P3DX
port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_7);
- FF_2: FD1P3DX
+ FF_3: FD1P3DX
port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_8);
- FF_1: FD1P3DX
+ FF_2: FD1P3DX
port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_9);
- FF_0: FD1P3DX
+ FF_1: FD1P3DX
port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset,
Q=>rcount_10);
+ FF_0: FD1S3BX
+ port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty);
+
bdcnt_bctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1,
NC0=>iwcount_10, NC1=>open);
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
r_ctr_cia: FADD2B
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4,
NC0=>ircount_8, NC1=>ircount_9);
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
r_ctr_5: CU2
port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2,
NC0=>ircount_10, NC1=>open);
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ ae_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open,
+ S1=>open);
+
+ ae_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv, B1=>r_nw,
+ CI=>cmp_ci_2, LE=>co0_5);
+
+ ae_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_5, LE=>co1_5);
+
+ ae_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_5, LE=>co2_5);
+
+ ae_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_5, LE=>co3_5);
+
+ ae_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_5, LE=>co4_5);
+
+ ae_cmp_5: ALEB2
+ port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co4_5, LE=>ae_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a2: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ WCNT(10) <= fcount_10;
Empty <= empty_i;
Full <= full_i;
end Structure;
SCLK_OUT : out std_logic;\r
SDIO_INOUT : inout std_logic;\r
CSB_OUT : out std_logic;\r
- \r
+\r
+ -- Internal Interface\r
+ INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);\r
+ COMMAND_ACK_OUT : out std_logic;\r
+ SPI_DATA : out std_logic_vector(31 downto 0);\r
+ SPI_LOCK_IN : in std_logic;\r
+\r
-- Slave bus \r
SLV_READ_IN : in std_logic;\r
SLV_WRITE_IN : in std_logic;\r
\r
architecture Behavioral of adc_spi_master is\r
\r
- signal sdio_i : std_logic;\r
- signal sdio_x : std_logic;\r
- signal sdio : std_logic;\r
+ signal sdio_i : std_logic;\r
+ signal sdio_x : std_logic;\r
+ signal sdio : std_logic;\r
\r
- signal sclk_o : std_logic;\r
+ signal sclk_o : std_logic;\r
+ signal command_ack_o : std_logic;\r
\r
-- SPI Master\r
signal csb_o : std_logic;\r
slv_unknown_addr_o <= '0';\r
slv_ack_o <= '0';\r
spi_start <= '0';\r
-\r
+ command_ack_o <= '0';\r
+ \r
spi_chipid <= (others => '0'); \r
spi_rw_bit <= '0'; \r
spi_registerid <= (others => '0'); \r
spi_register_value_read <= (others => '0');\r
\r
else\r
- slv_ack_o <= '1';\r
+ slv_data_out_o <= (others => '0');\r
slv_unknown_addr_o <= '0';\r
slv_no_more_data_o <= '0';\r
- slv_data_out_o <= (others => '0');\r
+\r
spi_start <= '0';\r
- \r
+ command_ack_o <= '0';\r
+\r
+ --if (spi_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then\r
+ -- spi_rw_bit <= INTERNAL_COMMAND_IN(30);\r
+ -- spi_registerid <= INTERNAL_COMMAND_IN(20 downto 8);\r
+ -- spi_register_data <= INTERNAL_COMMAND_IN(7 downto 0); \r
+ -- spi_start <= '1';\r
+ -- command_ack_o <= '1';\r
+ -- slv_ack_o <= '1';\r
+ --\r
+ --elsif (SLV_WRITE_IN = '1') then\r
if (SLV_WRITE_IN = '1') then\r
if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then\r
spi_rw_bit <= SLV_DATA_IN(30);\r
spi_registerid <= SLV_DATA_IN(20 downto 8);\r
spi_register_data <= SLV_DATA_IN(7 downto 0); \r
spi_start <= '1';\r
+ slv_ack_o <= '1';\r
+ else\r
+ slv_ack_o <= '1';\r
end if;\r
-\r
+ \r
elsif (SLV_READ_IN = '1') then\r
if (spi_busy = '1') then\r
- slv_data_out_o <= (others => '0');\r
slv_no_more_data_o <= '1';\r
slv_ack_o <= '0';\r
else\r
- slv_data_out_o <= reg_data;\r
+ slv_data_out_o <= reg_data;\r
+ slv_ack_o <= '1';\r
end if;\r
\r
else\r
- slv_ack_o <= '0';\r
+ slv_ack_o <= '0';\r
end if;\r
+ \r
end if;\r
end if; \r
end process PROC_SLAVE_BUS;\r
-----------------------------------------------------------------------------\r
\r
-- SPI Outputs\r
- SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1')\r
- else 'Z';\r
+ SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1')\r
+ else 'Z';\r
\r
- SCLK_OUT <= sclk_o or\r
- sclk_sendbyte or\r
- sclk_readbyte;\r
-\r
- CSB_OUT <= csb_o;\r
+ SCLK_OUT <= sclk_o or\r
+ sclk_sendbyte or\r
+ sclk_readbyte;\r
\r
+ CSB_OUT <= csb_o;\r
+ COMMAND_ACK_OUT <= command_ack_o;\r
+ \r
-- Slave Bus\r
SLV_DATA_OUT <= slv_data_out_o; \r
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
);
-end Gray_Decoder;
+end entity;
architecture Gray_Decoder of Gray_Decoder is
GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0)
);
-end Gray_Encoder;
+end entity;
architecture Behavioral of Gray_Encoder is
PULSE_OUT : out std_logic
);
-end level_to_pulse;
+end entity;
architecture Behavioral of level_to_pulse is
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
pulse_o <= '0';
- STATE <= WAIT_LOW;
+ STATE <= IDLE;
else
pulse_o <= '0';
case STATE is
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.nxyter_components.all;
-
-entity nx_data_buffer is
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- Data Buffer FIFO
- DATA_IN : in std_logic_vector(31 downto 0);
- DATA_CLK_IN : in std_logic;
-
- -- Slave bus
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-
-end nx_data_buffer;
-
-architecture Behavioral of nx_data_buffer is
- -- FIFO Input Handler
- signal fifo_next_word : std_logic_vector(31 downto 0);
- signal fifo_full : std_logic;
- signal fifo_write_enable : std_logic;
-
- -- FIFO Read Handler
- signal fifo_o : std_logic_vector(31 downto 0);
- signal fifo_empty : std_logic;
- signal fifo_read_start : std_logic;
-
- signal fifo_read_enable : std_logic;
- signal fifo_read_busy : std_logic;
- signal fifo_no_data : std_logic;
- signal fifo_read_done : std_logic;
- signal fifo_data : std_logic_vector(31 downto 0);
-
- type STATES is (S_IDLE,
- S_NOP1,
- S_NOP2,
- S_READ_WORD
- );
-
- signal STATE : STATES;
-
- -- Slave Bus
- signal slv_data_out_o : std_logic_vector(31 downto 0);
- signal slv_no_more_data_o : std_logic;
- signal slv_unknown_addr_o : std_logic;
- signal slv_ack_o : std_logic;
-
- signal register_fifo_status : std_logic_vector(31 downto 0);
-
- signal data_wait : std_logic;
-
-begin
-
- DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= '0';
- DEBUG_OUT(2) <= data_wait;
- DEBUG_OUT(3) <= fifo_read_done;
- DEBUG_OUT(4) <= fifo_read_busy;
- DEBUG_OUT(5) <= fifo_write_enable;
- DEBUG_OUT(6) <= fifo_full;
- DEBUG_OUT(7) <= fifo_empty;
- DEBUG_OUT(8) <= fifo_read_enable;
- DEBUG_OUT(9) <= slv_ack_o;
- DEBUG_OUT(10) <= fifo_no_data;
- DEBUG_OUT(11) <= fifo_read_start;
- DEBUG_OUT(15 downto 12) <= fifo_o(3 downto 0);
-
- -----------------------------------------------------------------------------
- -- FIFO Input Handler
- -----------------------------------------------------------------------------
-
- -- Send data to FIFO
- fifo_32_data_1: fifo_32_data
- port map (
- Data => fifo_next_word,
- Clock => CLK_IN,
- WrEn => fifo_write_enable,
- RdEn => fifo_read_enable,
- Reset => RESET_IN,
- Q => fifo_o,
- Empty => fifo_empty,
- Full => fifo_full
- );
-
- PROC_FIFO_WRITE_HANDLER: process(CLK_IN)
- begin
- if(rising_edge(CLK_IN)) then
- if(RESET_IN = '1') then
- fifo_write_enable <= '0';
- else
- fifo_write_enable <= '0';
- fifo_next_word <= x"deadbeef";
-
- if (DATA_CLK_IN = '1' and fifo_full = '0') then
- fifo_next_word <= DATA_IN;
- fifo_write_enable <= '1';
- end if;
-
- end if;
- end if;
- end process PROC_FIFO_WRITE_HANDLER;
-
- -----------------------------------------------------------------------------
- -- FIFO Output Handler
- -----------------------------------------------------------------------------
-
- PROC_FIFO_READ_WORD: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- fifo_read_enable <= '0';
- fifo_read_busy <= '0';
- fifo_data <= (others => '0');
- fifo_read_done <= '0';
- fifo_no_data <= '1';
- STATE <= S_IDLE;
- else
- fifo_read_busy <= '0';
- fifo_no_data <= '0';
- fifo_read_done <= '0';
- fifo_data <= (others => '0');
- fifo_read_enable <= '0';
-
- case STATE is
- when S_IDLE =>
- if (fifo_read_start = '1') then
- if (fifo_empty = '0') then
- fifo_read_enable <= '1';
- fifo_read_busy <= '1';
- STATE <= S_NOP1;
- else
- fifo_no_data <= '1';
- fifo_read_done <= '1';
- STATE <= S_IDLE;
- end if;
- else
- STATE <= S_IDLE;
- end if;
-
- when S_NOP1 =>
- fifo_read_busy <= '1';
- STATE <= S_NOP2;
-
- when S_NOP2 =>
- fifo_read_busy <= '1';
- STATE <= S_READ_WORD;
-
- when S_READ_WORD =>
- fifo_read_busy <= '0';
- fifo_data <= fifo_o;
- fifo_read_done <= '1';
- STATE <= S_IDLE;
-
- end case;
- end if;
- end if;
-
- end process PROC_FIFO_READ_WORD;
-
- -----------------------------------------------------------------------------
- -- Slave Bus Slow Control
- -----------------------------------------------------------------------------
-
- register_fifo_status(0) <= fifo_write_enable;
- register_fifo_status(1) <= fifo_full;
- register_fifo_status(3 downto 2) <= (others => '0');
- register_fifo_status(4) <= fifo_read_enable;
- register_fifo_status(5) <= fifo_empty;
- register_fifo_status(7 downto 6) <= (others => '0');
- register_fifo_status(31 downto 8) <= (others => '0');
-
- PROC_SLAVE_BUS: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
-
- fifo_read_start <= '0';
- data_wait <= '0';
- else
- slv_data_out_o <= (others => '0');
- slv_ack_o <= '0';
- slv_unknown_addr_o <= '0';
- slv_no_more_data_o <= '0';
-
- fifo_read_start <= '0';
- data_wait <= '0';
-
- if (data_wait = '1') then
- if (fifo_read_done = '0') then
- data_wait <= '1';
- else
- if (fifo_no_data = '0') then
- slv_data_out_o <= fifo_data;
- slv_ack_o <= '1';
- else
- slv_no_more_data_o <= '1';
- slv_ack_o <= '0';
- end if;
- data_wait <= '0';
- end if;
-
- elsif (SLV_READ_IN = '1') then
- case SLV_ADDR_IN is
- when x"0000" =>
- fifo_read_start <= '1';
- data_wait <= '1';
-
- when x"0001" =>
- slv_data_out_o <= register_fifo_status;
- slv_ack_o <= '1';
-
- when others =>
- slv_unknown_addr_o <= '1';
- end case;
-
- elsif (SLV_WRITE_IN = '1') then
- case SLV_ADDR_IN is
- when others =>
- slv_unknown_addr_o <= '1';
- slv_ack_o <= '0';
- end case;
-
- else
- slv_ack_o <= '0';
- end if;
- end if;
- end if;
- end process PROC_SLAVE_BUS;
-
--- Output Signals
- SLV_DATA_OUT <= slv_data_out_o;
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
- SLV_ACK_OUT <= slv_ack_o;
-
-end Behavioral;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);\r
\r
-- ADC Ports\r
- ADC_CLK_DAT_SRC_IN : in std_logic;\r
+ ADC_CLK_DAT_IN : in std_logic;\r
ADC_FCLK_IN : in std_logic_vector(1 downto 0);\r
ADC_DCLK_IN : in std_logic_vector(1 downto 0);\r
ADC_SAMPLE_CLK_OUT : out std_logic;\r
-----------------------------------------------------------------------------\r
\r
-- ADC Handler\r
- signal adc_dat_clk : std_logic;\r
- signal adc_dat_clk_lock : std_logic;\r
signal adc_reset_r : std_logic;\r
+ signal adc_reset_l : std_logic;\r
signal adc_reset : std_logic;\r
\r
signal adc_data : std_logic_vector(11 downto 0);\r
signal adc_data_valid : std_logic;\r
\r
- -- ADC FIFO Handler\r
--- signal adc_fifo_reset : std_logic;\r
--- signal adc_fifo_next_word : std_logic_vector(11 downto 0);\r
--- signal adc_fifo_almost_empty : std_logic;\r
--- signal adc_fifo_full : std_logic;\r
--- signal adc_fifo_empty : std_logic;\r
--- signal adc_fifo_read_enable : std_logic;\r
--- signal adc_fifo_write_enable : std_logic;\r
--- signal adc_read_enable_pause : std_logic;\r
--- \r
--- signal adc_fifo_data_valid_t : std_logic;\r
--- signal adc_fifo_data_valid : std_logic;\r
--- signal adc_fifo_data : std_logic_vector(11 downto 0);\r
- \r
signal adc_data_t : std_logic_vector(11 downto 0);\r
signal adc_new_data : std_logic;\r
signal adc_new_data_ctr : unsigned(3 downto 0);\r
\r
signal reset_resync_ctr : std_logic;\r
signal reset_parity_error_ctr : std_logic;\r
- signal adc_fifo_delay_r : std_logic_vector(5 downto 0);\r
signal fifo_reset_r : std_logic;\r
\r
signal valid_data_d : std_logic;\r
DEBUG_OUT(4) <= adc_new_data;\r
DEBUG_OUT(5) <= new_data_o;\r
DEBUG_OUT(6) <= nx_fifo_data_valid;\r
- --DEBUG_OUT(7) <= adc_fifo_data_valid;\r
DEBUG_OUT(7) <= valid_data_d;--(others => '0');\r
DEBUG_OUT(15 downto 8) <= nx_timestamp_reg;\r
--DEBUG_OUT(15 downto 8) <= (others => '0');\r
-- ADC CLK DOMAIN\r
-----------------------------------------------------------------------------\r
\r
- pll_adc_clk192_1: pll_adc_clk192\r
- port map (\r
- CLK => ADC_CLK_DAT_SRC_IN,\r
- CLKOP => adc_dat_clk,\r
- LOCK => adc_dat_clk_lock\r
- );\r
-\r
adc_ad9222_1: entity work.adc_ad9222\r
generic map (\r
CHANNELS => 4,\r
port map (\r
CLK => CLK_IN,\r
CLK_ADCREF => adc_sample_clk,\r
- CLK_ADCDAT => adc_dat_clk,\r
+ CLK_ADCDAT => ADC_CLK_DAT_IN,\r
RESTART_IN => adc_reset,\r
ADCCLK_OUT => ADC_SAMPLE_CLK_OUT,\r
\r
DEBUG => open\r
);\r
\r
--- pulse_to_level_1: pulse_to_level\r
--- generic map (\r
--- NUM_CYCLES => "10000"\r
--- )\r
--- port map (\r
--- CLK_IN => CLK_IN,\r
--- RESET_IN => RESET_IN,\r
--- PULSE_IN => adc_reset_r,\r
--- LEVEL_OUT => adc_reset\r
--- );\r
- \r
- adc_reset <= adc_reset_r;\r
-\r
--- PROC_ADC_RESET: proc(CLK_IN)\r
--- begin\r
--- if( rising_edge(CLK_IN) ) then\r
--- if (RESET_IN = '1' or reset_parity_error_ctr = '1') then\r
--- adc_reset <= '0';\r
--- else\r
--- if (adc_reset_start = '1') then\r
--- adc_reset <= '1';\r
--- \r
--- end generate (adc_reset_start = '1');\r
--- adc_reset\r
--- end if;\r
--- end if;\r
--- end if;\r
+ adc_reset <= adc_reset_l or RESET_IN;\r
+\r
+ pulse_to_level_1: pulse_to_level\r
+ generic map (\r
+ NUM_CYCLES => "10000"\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ PULSE_IN => adc_reset_r,\r
+ LEVEL_OUT => adc_reset_l\r
+ );\r
\r
-----------------------------------------------------------------------------\r
-- NX_TIMESTAMP_CLK_IN Domain\r
\r
nx_fifo_reset <= RESET_IN or fifo_reset_r;\r
\r
--- fifo_12_adc_1: fifo_12_adc\r
--- port map (\r
--- Data => adc_fifo_next_word,\r
--- Clock => CLK_IN,\r
--- WrEn => adc_fifo_write_enable,\r
--- RdEn => adc_fifo_read_enable,\r
--- Reset => adc_fifo_reset,\r
--- AmEmptyThresh => adc_fifo_delay_r,\r
--- Q => adc_fifo_data,\r
--- Empty => adc_fifo_empty,\r
--- Full => adc_fifo_full,\r
--- AlmostEmpty => adc_fifo_almost_empty\r
--- );\r
---\r
--- adc_fifo_reset <= RESET_IN;\r
- \r
-\r
-- -- Reset NX_TIMESTAMP_CLK Domain\r
-- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN)\r
-- begin\r
end if;\r
end process PROC_ADC_DATA_READ; \r
\r
- -- ADC FIFO Write Handler\r
--- PROC_ADC_FIFO_WRITE_ENABLE: process(CLK_IN)\r
--- begin\r
--- if( rising_edge(CLK_IN) ) then\r
--- if( RESET_IN = '1' ) then\r
--- adc_fifo_next_word <= x"bee";\r
--- adc_fifo_write_enable <= '0';\r
--- else\r
--- if (adc_data_valid = '1' and adc_fifo_full = '0') then\r
--- adc_fifo_next_word <= adc_data; \r
--- adc_fifo_write_enable <= '1';\r
--- else\r
--- adc_fifo_next_word <= x"bee";\r
--- adc_fifo_write_enable <= '0';\r
--- end if;\r
--- end if;\r
--- end if;\r
--- end process PROC_ADC_FIFO_WRITE_ENABLE;\r
---\r
--- -- ADC FIFO Read Handler\r
--- PROC_ADC_FIFO_READ_ENABLE: process(CLK_IN)\r
--- begin\r
--- if( rising_edge(CLK_IN) ) then\r
--- if( RESET_IN = '1' or fifo_reset_r = '1') then\r
--- adc_fifo_read_enable <= '0';\r
--- adc_read_enable_pause <= '0';\r
--- adc_fifo_data_valid_t <= '0';\r
--- adc_fifo_data_valid <= '0';\r
--- else\r
--- if (adc_fifo_almost_empty = '0' and adc_read_enable_pause = '0') then\r
--- adc_fifo_read_enable <= '1';\r
--- adc_read_enable_pause <= '1';\r
--- else\r
--- adc_fifo_read_enable <= '0';\r
--- adc_read_enable_pause <= '0';\r
--- end if;\r
---\r
--- -- Delay read signal by one CLK\r
--- adc_fifo_data_valid_t <= adc_fifo_read_enable;\r
--- adc_fifo_data_valid <= adc_fifo_data_valid_t;\r
---\r
--- end if;\r
--- end if;\r
--- end process PROC_ADC_FIFO_READ_ENABLE;\r
- \r
--- PROC_ADC_FIFO_READ: process(CLK_IN)\r
--- begin\r
--- if( rising_edge(CLK_IN) ) then\r
--- if (RESET_IN = '1' or fifo_reset_r = '1') then\r
--- adc_data_t <= (others => '0');\r
--- adc_new_data <= '0';\r
--- adc_new_data_ctr <= (others => '0');\r
--- else\r
--- if (adc_fifo_data_valid = '1') then\r
--- adc_data_t <= adc_fifo_data;\r
--- adc_new_data <= '1';\r
--- adc_new_data_ctr <= adc_new_data_ctr + 1;\r
--- else\r
--- adc_data_t <= x"aff";\r
--- adc_new_data <= '0';\r
--- end if;\r
--- end if;\r
--- end if;\r
--- end process PROC_ADC_FIFO_READ;\r
-\r
-----------------------------------------------------------------------------\r
-- Output handler\r
-----------------------------------------------------------------------------\r
reset_resync_ctr <= '0';\r
reset_parity_error_ctr <= '0';\r
nx_fifo_delay_r <= "01000";\r
- adc_fifo_delay_r <= "000010";\r
fifo_reset_r <= '0';\r
adc_clk_delay <= "111";\r
adc_reset_r <= '0';\r
when x"0001" =>\r
slv_data_out_o(0) <= nx_fifo_full;\r
slv_data_out_o(1) <= nx_fifo_empty;\r
- slv_data_out_o(2) <= '0'; --adc_fifo_full;\r
- slv_data_out_o(3) <= '0'; -- adc_fifo_empty;\r
+ slv_data_out_o(2) <= '0';\r
+ slv_data_out_o(3) <= '0';\r
slv_data_out_o(4) <= nx_fifo_data_valid;\r
- slv_data_out_o(5) <= adc_new_data; --adc_fifo_data_valid;\r
+ slv_data_out_o(5) <= adc_new_data;\r
slv_data_out_o(29 downto 5) <= (others => '0');\r
slv_data_out_o(30) <= '0';\r
slv_data_out_o(31) <= reg_nx_frame_synced;\r
when x"0004" => \r
if (SLV_DATA_IN < x"0000_001c" and\r
SLV_DATA_IN > x"0000_0001") then\r
- nx_fifo_delay_r <= SLV_DATA_IN(4 downto 0);\r
+ nx_fifo_delay_r <= SLV_DATA_IN(4 downto 0);\r
fifo_reset_r <= '1';\r
end if;\r
slv_ack_o <= '1';\r
when "110" => adc_clk_delay <= "110";\r
when "111" => adc_clk_delay <= "111";\r
end case;\r
+ adc_reset_r <= '1';\r
end if;\r
slv_ack_o <= '1';\r
\r
signal adc_data_o : std_logic_vector(11 downto 0);\r
signal data_valid_o : std_logic;\r
\r
- signal nx_notempty_ctr : unsigned (1 downto 0); \r
signal nx_token_return_o : std_logic;\r
signal nx_nomore_data_o : std_logic;\r
\r
begin\r
\r
-- Debug Line\r
--- DEBUG_OUT(0) <= CLK_IN;\r
--- DEBUG_OUT(1) <= new_timestamp;\r
--- DEBUG_OUT(2) <= nx_token_return_o;-- new_timestamp;\r
- DEBUG_OUT(0) <= data_valid_o;\r
- DEBUG_OUT(3 downto 1) <= channel_o(2 downto 0);\r
- DEBUG_OUT(15 downto 4) <= adc_data;\r
+ DEBUG_OUT(0) <= CLK_IN;\r
+ DEBUG_OUT(1) <= nx_token_return_o;\r
+ DEBUG_OUT(2) <= nx_nomore_data_o;\r
+ DEBUG_OUT(3) <= data_valid_o;\r
+ DEBUG_OUT(4) <= new_timestamp;\r
+ DEBUG_OUT(8 downto 5) <= (others => '0');\r
+ DEBUG_OUT(15 downto 9) <= channel_o;\r
--DEBUG_OUT(6 downto 4) <= timestamp_status_o;\r
--DEBUG_OUT(7) <= nx_token_return_o;\r
--DEBUG_OUT(8) <= invalid_adc;--nx_nomore_data_o;\r
timestamp_status_o <= (others => '0');\r
adc_data_o <= (others => '0');\r
data_valid_o <= '0';\r
- nx_notempty_ctr <= (others => '0');\r
nx_token_return_o <= '0';\r
- nx_nomore_data_o <= '1';\r
+ nx_nomore_data_o <= '0';\r
\r
invalid_frame_ctr <= (others => '0');\r
overflow_ctr <= (others => '0');\r
timestamp_status_o <= (others => '0');\r
adc_data_o <= (others => '0');\r
data_valid_o <= '0';\r
- nx_token_return_o <= '0';\r
- nx_nomore_data_o <= '0';\r
-\r
+ \r
invalid_adc <= '0';\r
\r
if (new_timestamp = '1') then\r
case valid_frame_bits is\r
+\r
+ -- Data Frame\r
when "1000" =>\r
---- Check Overflow\r
if ((status_bits(0) = '1') and (clear_counters = '0')) then\r
adc_data_o <= adc_data;\r
data_valid_o <= '1';\r
\r
- nx_notempty_ctr <= (others => '0');\r
-\r
-- Rate Counter\r
if (nx_rate_timer < x"186a0") then\r
- nx_valid_ctr <= nx_valid_ctr + 1;\r
+ nx_valid_ctr <= nx_valid_ctr + 1;\r
end if;\r
\r
if (adc_data = x"aff") then\r
invalid_adc <= '1';\r
end if;\r
- \r
+\r
+ nx_token_return_o <= '0';\r
+ nx_nomore_data_o <= '0';\r
+ \r
+ -- Token return and nomore_data\r
when "0000" =>\r
- case nx_notempty_ctr is\r
- when "00" =>\r
- nx_token_return_o <= '1';\r
- nx_notempty_ctr <= nx_notempty_ctr + 1;\r
-\r
- when "01" =>\r
- nx_nomore_data_o <= '1';\r
- nx_notempty_ctr <= nx_notempty_ctr + 1;\r
- \r
- when others => null;\r
- end case;\r
+ nx_token_return_o <= '1';\r
+ nx_nomore_data_o <= nx_token_return_o;\r
\r
when others =>\r
-- Invalid frame, not empty, discard timestamp\r
if (clear_counters = '0') then\r
invalid_frame_ctr <= invalid_frame_ctr + 1;\r
end if;\r
- nx_notempty_ctr <= (others => '0');\r
+ nx_token_return_o <= '0';\r
+ nx_nomore_data_o <= '0';\r
+ \r
end case;\r
- end if;\r
+ else\r
+ nx_token_return_o <= nx_token_return_o;\r
+ nx_nomore_data_o <= nx_nomore_data_o;\r
+ end if; -- new_timestamp = '1'\r
\r
-- Trigger Rate\r
if (nx_rate_timer < x"186a0") then\r
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.nxyter_components.all;
+
+entity nx_event_buffer is
+ generic (
+ BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RESET_DATA_BUFFER_IN : in std_logic;
+ NXYTER_OFFLINE_IN : in std_logic;
+
+ -- Data Buffer FIFO
+ DATA_IN : in std_logic_vector(31 downto 0);
+ DATA_CLK_IN : in std_logic;
+ EVT_NOMORE_DATA_IN : in std_logic;
+
+ -- LVL2 Trigger
+ LVL2_TRIGGER_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+
+ --Response from FEE
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_DATA_ALMOST_FULL_IN : in std_logic;
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+
+end entity;
+
+architecture Behavioral of nx_event_buffer is
+
+ --Data channel
+ signal fee_data_o : std_logic_vector(31 downto 0);
+ signal fee_data_write_o : std_logic;
+ signal fee_data_finished_o : std_logic;
+ signal fee_almost_full_o : std_logic;
+ signal trigger_busy_o : std_logic;
+ signal evt_data_flush : std_logic;
+
+ type STATES is (S_IDLE,
+ S_FLUSH_BUFFER_WAIT
+ );
+ signal STATE : STATES;
+
+ -- FIFO
+ signal fifo_reset : std_logic;
+ signal fifo_read_enable : std_logic;
+
+ -- FIFO Input Handler
+ signal fifo_next_word : std_logic_vector(31 downto 0);
+ signal fifo_full : std_logic;
+ signal fifo_write_enable : std_logic;
+
+ -- NOMORE_DATA RS FlipFlop
+ signal flush_end : std_logic;
+
+ -- FIFO Read Handler
+ signal fifo_o : std_logic_vector(31 downto 0);
+ signal fifo_empty : std_logic;
+ signal fifo_write_ctr : std_logic_vector(10 downto 0);
+ signal fifo_read_start : std_logic;
+
+ signal fifo_read_enable_s : std_logic;
+ signal fifo_read_busy : std_logic;
+ signal fifo_no_data : std_logic;
+ signal fifo_read_done : std_logic;
+ signal fifo_data : std_logic_vector(31 downto 0);
+
+ type R_STATES is (R_IDLE,
+ R_NOP1,
+ R_NOP2,
+ R_READ_WORD
+ );
+
+ signal R_STATE : R_STATES;
+
+ -- Event Buffer Output Handler
+ signal evt_data_clk : std_logic;
+ signal evt_data_flushed : std_logic;
+
+ signal fifo_read_enable_f : std_logic;
+ signal fifo_read_enable_f2 : std_logic;
+ signal fifo_flush_ctr : unsigned(10 downto 0);
+
+ signal evt_data_flushed_x : std_logic;
+ signal fifo_flush_ctr_x : unsigned(10 downto 0);
+ signal flush_end_reset : std_logic;
+ signal flush_end_reset_x : std_logic;
+
+ type F_STATES is (F_IDLE,
+ F_FLUSH,
+ F_END
+ );
+
+ signal F_STATE, F_NEXT_STATE : F_STATES;
+
+ -- Slave Bus
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
+
+ signal register_fifo_status : std_logic_vector(31 downto 0);
+
+ signal data_wait : std_logic;
+
+ signal evt_data_flush_r : std_logic;
+
+begin
+
+ DEBUG_OUT(0) <= CLK_IN;
+ --DEBUG_OUT(1) <= evt_data_flush_r;
+ DEBUG_OUT(2) <= evt_data_clk;
+ DEBUG_OUT(3) <= fifo_empty;
+ DEBUG_OUT(4) <= fifo_read_enable;
+ DEBUG_OUT(5) <= evt_data_flushed;
+ DEBUG_OUT(6) <= '0';
+ DEBUG_OUT(7) <= EVT_NOMORE_DATA_IN;
+ --DEBUG_OUT(15 downto 8) <= evt_data_o(31 downto 24);
+
+ DEBUG_OUT(8) <= LVL2_TRIGGER_IN;
+ DEBUG_OUT(11 downto 9) <= (others => '0');
+ DEBUG_OUT(13) <= fee_data_write_o;
+ DEBUG_OUT(14) <= fee_data_finished_o;
+ DEBUG_OUT(15) <= FEE_DATA_ALMOST_FULL_IN;
+
+ -----------------------------------------------------------------------------
+ --
+ -----------------------------------------------------------------------------
+
+ PROC_DATA_HANDLER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ fee_data_finished_o <= '0';
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ else
+ fee_data_finished_o <= '0';
+ trigger_busy_o <= '1';
+
+ case STATE is
+ when S_IDLE =>
+ if (NXYTER_OFFLINE_IN = '1') then
+ fee_data_finished_o <= '1';
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ elsif (LVL2_TRIGGER_IN = '1') then
+ evt_data_flush <= '1';
+ STATE <= S_FLUSH_BUFFER_WAIT;
+ else
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
+ end if;
+
+ when S_FLUSH_BUFFER_WAIT =>
+ if (evt_data_flushed = '0') then
+ STATE <= S_FLUSH_BUFFER_WAIT;
+ else
+ fee_data_finished_o <= '1';
+ STATE <= S_IDLE;
+ end if;
+
+ end case;
+ end if;
+ end if;
+
+ end process PROC_DATA_HANDLER;
+
+ -----------------------------------------------------------------------------
+ -- FIFO Input Handler
+ -----------------------------------------------------------------------------
+
+ -- Send data to FIFO
+ fifo_32_data_1: fifo_32_data
+ port map (
+ Data => fifo_next_word,
+ Clock => CLK_IN,
+ WrEn => fifo_write_enable,
+ RdEn => fifo_read_enable,
+ Reset => fifo_reset,
+ Q => fifo_o,
+ WCNT => fifo_write_ctr,
+ Empty => fifo_empty,
+ Full => fifo_full
+ );
+
+ fifo_reset <= RESET_IN or RESET_DATA_BUFFER_IN;
+ fifo_read_enable <= fifo_read_enable_f or fifo_read_enable_s;
+
+ PROC_FIFO_WRITE_HANDLER: process(CLK_IN)
+ begin
+ if(rising_edge(CLK_IN)) then
+ if(RESET_IN = '1' or RESET_DATA_BUFFER_IN = '1') then
+ fifo_write_enable <= '0';
+ else
+ fifo_write_enable <= '0';
+ fifo_next_word <= x"deadbeef";
+
+ if (DATA_CLK_IN = '1' and fifo_full = '0') then
+ fifo_next_word <= DATA_IN;
+ fifo_write_enable <= '1';
+ end if;
+
+ end if;
+ end if;
+ end process PROC_FIFO_WRITE_HANDLER;
+
+ PROC_FLUSH_END_RS: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' or flush_end_reset = '1') then
+ flush_end <= '0';
+ else
+ if (EVT_NOMORE_DATA_IN = '1') then
+ flush_end <= '1';
+ end if;
+ end if;
+ end if;
+ end process PROC_FLUSH_END_RS;
+
+ PROC_FLUSH_BUFFER_TRANSFER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ evt_data_clk <= '0';
+ evt_data_flushed <= '0';
+ fifo_flush_ctr <= (others => '0');
+ fifo_read_enable_f2 <= '0';
+ flush_end_reset <= '0';
+ F_STATE <= F_IDLE;
+ else
+ evt_data_flushed <= evt_data_flushed_x;
+ fifo_flush_ctr <= fifo_flush_ctr_x;
+ flush_end_reset <= flush_end_reset_x;
+ F_STATE <= F_NEXT_STATE;
+
+ fifo_read_enable_f2 <= fifo_read_enable_f;
+ evt_data_clk <= fifo_read_enable_f2;
+ end if;
+ end if;
+ end process PROC_FLUSH_BUFFER_TRANSFER;
+
+ PROC_FLUSH_BUFFER: process(F_STATE,
+ evt_data_flush,
+ fifo_empty,
+ evt_data_clk,
+ flush_end
+ )
+ begin
+ -- Defaults
+ fifo_read_enable_f <= '0';
+ fifo_flush_ctr_x <= fifo_flush_ctr;
+ evt_data_flushed_x <= '0';
+ flush_end_reset_x <= '0';
+
+ -- Multiplexer fee_data_o
+ if (evt_data_clk = '1') then
+ fee_data_o <= fifo_o;
+ fee_data_write_o <= '1';
+ else
+ fee_data_o <= (others => '1');
+ fee_data_write_o <= '0';
+ end if;
+
+ -- FIFO Read Handler
+ case F_STATE is
+ when F_IDLE =>
+ if (evt_data_flush = '1') then
+ fifo_flush_ctr_x <= (others => '0');
+ flush_end_reset_x <= '1';
+ F_NEXT_STATE <= F_FLUSH;
+ else
+ F_NEXT_STATE <= F_IDLE;
+ end if;
+
+ when F_FLUSH =>
+ if (fifo_empty = '0') then
+ fifo_read_enable_f <= '1';
+ fifo_flush_ctr_x <= fifo_flush_ctr + 1;
+ F_NEXT_STATE <= F_FLUSH;
+ else
+ if (flush_end = '0') then
+ F_NEXT_STATE <= F_FLUSH;
+ else
+ F_NEXT_STATE <= F_END;
+ end if;
+ end if;
+
+ when F_END =>
+ evt_data_flushed_x <= '1';
+ F_NEXT_STATE <= F_IDLE;
+
+ end case;
+ end process PROC_FLUSH_BUFFER;
+
+ -----------------------------------------------------------------------------
+ -- FIFO Output Handler
+ -----------------------------------------------------------------------------
+
+ PROC_FIFO_READ_WORD: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ fifo_read_enable_s <= '0';
+ fifo_read_busy <= '0';
+ fifo_data <= (others => '0');
+ fifo_read_done <= '0';
+ fifo_no_data <= '1';
+ R_STATE <= R_IDLE;
+ else
+ fifo_read_busy <= '0';
+ fifo_no_data <= '0';
+ fifo_read_done <= '0';
+ fifo_data <= (others => '0');
+ fifo_read_enable_s <= '0';
+
+ case R_STATE is
+ when R_IDLE =>
+ if (fifo_read_start = '1') then
+ if (fifo_empty = '0') then
+ fifo_read_enable_s <= '1';
+ fifo_read_busy <= '1';
+ R_STATE <= R_NOP1;
+ else
+ fifo_no_data <= '1';
+ fifo_read_done <= '1';
+ R_STATE <= R_IDLE;
+ end if;
+ else
+ R_STATE <= R_IDLE;
+ end if;
+
+ when R_NOP1 =>
+ fifo_read_busy <= '1';
+ R_STATE <= R_NOP2;
+
+ when R_NOP2 =>
+ fifo_read_busy <= '1';
+ R_STATE <= R_READ_WORD;
+
+ when R_READ_WORD =>
+ fifo_read_busy <= '0';
+ fifo_data <= fifo_o;
+ fifo_read_done <= '1';
+ R_STATE <= R_IDLE;
+
+ end case;
+ end if;
+ end if;
+
+ end process PROC_FIFO_READ_WORD;
+
+ -----------------------------------------------------------------------------
+ -- Slave Bus Slow Control
+ -----------------------------------------------------------------------------
+
+ register_fifo_status(0) <= fifo_write_enable;
+ register_fifo_status(1) <= fifo_full;
+ register_fifo_status(3 downto 2) <= (others => '0');
+ register_fifo_status(4) <= fifo_read_enable;
+ register_fifo_status(5) <= fifo_empty;
+ register_fifo_status(7 downto 6) <= (others => '0');
+ register_fifo_status(31 downto 8) <= (others => '0');
+
+ PROC_SLAVE_BUS: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+
+ fifo_read_start <= '0';
+ data_wait <= '0';
+ evt_data_flush_r <= '0';
+ else
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+
+ fifo_read_start <= '0';
+ data_wait <= '0';
+ evt_data_flush_r <= '0';
+
+ if (data_wait = '1') then
+ if (fifo_read_done = '0') then
+ data_wait <= '1';
+ else
+ if (fifo_no_data = '0') then
+ slv_data_out_o <= fifo_data;
+ slv_ack_o <= '1';
+ else
+ slv_no_more_data_o <= '1';
+ slv_ack_o <= '0';
+ end if;
+ data_wait <= '0';
+ end if;
+
+ elsif (SLV_READ_IN = '1') then
+ case SLV_ADDR_IN is
+ when x"0000" =>
+ fifo_read_start <= '1';
+ data_wait <= '1';
+
+ when x"0001" =>
+ slv_data_out_o(10 downto 0) <= fifo_write_ctr;
+ slv_data_out_o(31 downto 11) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0002" =>
+ slv_data_out_o(10 downto 0) <= std_logic_vector(fifo_flush_ctr);
+ slv_data_out_o(31 downto 11) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0003" =>
+ slv_data_out_o <= register_fifo_status;
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ end case;
+
+ elsif (SLV_WRITE_IN = '1') then
+ case SLV_ADDR_IN is
+
+ when x"0000" =>
+ evt_data_flush_r <= '1';
+ slv_ack_o <= '1';
+
+ when others =>
+ slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+
+ else
+ slv_ack_o <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_SLAVE_BUS;
+
+-- Output Signals
+ TRIGGER_BUSY_OUT <= trigger_busy_o;
+
+ FEE_DATA_OUT <= fee_data_o;
+ FEE_DATA_WRITE_OUT <= fee_data_write_o;
+ FEE_DATA_FINISHED_OUT <= fee_data_finished_o;
+
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
+
+end Behavioral;
SDA_INOUT : inout std_logic;\r
SCL_INOUT : inout std_logic;\r
\r
+ -- Internal Interface\r
+ INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);\r
+ COMMAND_BUSY_OUT : out std_logic;\r
+ I2C_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ I2C_LOCK_IN : in std_logic;\r
+ \r
-- Slave bus \r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_NO_MORE_DATA_OUT : out std_logic;\r
- SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
\r
-- Debug Line\r
DEBUG_OUT : out std_logic_vector(15 downto 0)\r
\r
architecture Behavioral of nx_i2c_master is\r
\r
- signal sda_i : std_logic;\r
- signal sda_x : std_logic;\r
- signal sda : std_logic;\r
-\r
- signal scl_i : std_logic;\r
- signal scl_x : std_logic;\r
- signal scl : std_logic;\r
+ signal sda_i : std_logic;\r
+ signal sda_x : std_logic;\r
+ signal sda : std_logic;\r
+ \r
+ signal scl_i : std_logic;\r
+ signal scl_x : std_logic;\r
+ signal scl : std_logic;\r
+ signal command_busy_o : std_logic;\r
\r
-- I2C Master \r
signal sda_o : std_logic;\r
signal readbyte_seq_start : std_logic;\r
signal sendbyte_byte : std_logic_vector(7 downto 0);\r
signal read_seq_ctr : std_logic;\r
- signal reg_data : std_logic_vector(31 downto 0);\r
+ signal i2c_data : std_logic_vector(31 downto 0);\r
\r
signal i2c_busy_x : std_logic;\r
signal startstop_select_x : std_logic;\r
signal sendbyte_byte_x : std_logic_vector(7 downto 0);\r
signal readbyte_seq_start_x : std_logic;\r
signal read_seq_ctr_x : std_logic;\r
- signal reg_data_x : std_logic_vector(31 downto 0);\r
+ signal i2c_data_x : std_logic_vector(31 downto 0);\r
\r
signal sda_startstop : std_logic;\r
signal scl_startstop : std_logic;\r
signal slv_no_more_data_o : std_logic;\r
signal slv_unknown_addr_o : std_logic;\r
signal slv_ack_o : std_logic;\r
+\r
signal i2c_chipid : std_logic_vector(6 downto 0);\r
signal i2c_rw_bit : std_logic;\r
signal i2c_registerid : std_logic_vector(7 downto 0);\r
signal i2c_register_data : std_logic_vector(7 downto 0);\r
signal i2c_register_value_read : std_logic_vector(7 downto 0);\r
\r
+ signal disable_slave_bus : std_logic; \r
+ signal internal_command : std_logic;\r
+ signal internal_command_d : std_logic;\r
+ signal i2c_data_internal_o : std_logic_vector(31 downto 0);\r
+ signal i2c_data_slave : std_logic_vector(31 downto 0);\r
+\r
begin\r
\r
+ -- Debug\r
+ DEBUG_OUT(0) <= CLK_IN;\r
+ DEBUG_OUT(8 downto 1) <= i2c_data(7 downto 0);\r
+ DEBUG_OUT(12 downto 9) <= i2c_data(31 downto 28);\r
+ DEBUG_OUT(13) <= i2c_busy;\r
+ DEBUG_OUT(14) <= internal_command;\r
+ DEBUG_OUT(15) <= internal_command_d;\r
+\r
-- Start / Stop Sequence\r
nx_i2c_startstop_1: nx_i2c_startstop\r
generic map (\r
SDA_IN => sda\r
);\r
\r
- -- Debug Line\r
- -- DEBUG_OUT(0) <= not sendbyte_ack;\r
- -- DEBUG_OUT(1) <= sda_o;\r
- -- DEBUG_OUT(2) <= scl_o;\r
- -- DEBUG_OUT(3) <= sda_startstop;\r
- -- DEBUG_OUT(4) <= scl_startstop;\r
- -- DEBUG_OUT(5) <= sda_sendbyte;\r
- -- DEBUG_OUT(6) <= scl_sendbyte;\r
- -- DEBUG_OUT(7) <= sda_readbyte;\r
- -- DEBUG_OUT(8) <= scl_readbyte;\r
- -- DEBUG_OUT(9) <= i2c_start;\r
- \r
- -- DEBUG_OUT(8) <= i2c_start;\r
- -- DEBUG_OUT(15 downto 10) <= (others => '0');\r
- DEBUG_OUT(0) <= i2c_start;\r
- DEBUG_OUT(15 downto 14) <= (others => '0');\r
- DEBUG_OUT(13 downto 9) <= reg_data(28 downto 24);\r
- DEBUG_OUT(8 downto 1) <= reg_data(7 downto 0);\r
-\r
- -- Sync I2C Lines\r
+ -- Sync I2C Lines\r
sda_i <= SDA_INOUT;\r
scl_i <= SCL_INOUT;\r
\r
sendbyte_seq_start <= '0';\r
readbyte_seq_start <= '0';\r
sendbyte_byte <= (others => '0');\r
- reg_data <= (others => '0');\r
+ i2c_data <= (others => '0');\r
read_seq_ctr <= '0';\r
STATE <= S_RESET;\r
else\r
sendbyte_seq_start <= sendbyte_seq_start_x;\r
readbyte_seq_start <= readbyte_seq_start_x;\r
sendbyte_byte <= sendbyte_byte_x;\r
- reg_data <= reg_data_x;\r
+ i2c_data <= i2c_data_x;\r
read_seq_ctr <= read_seq_ctr_x;\r
STATE <= NEXT_STATE;\r
end if;\r
sendbyte_done,\r
sendbyte_ack,\r
readbyte_done,\r
- startstop_done)\r
+ startstop_done\r
+ )\r
\r
begin\r
-- Defaults\r
sendbyte_seq_start_x <= '0';\r
sendbyte_byte_x <= (others => '0');\r
readbyte_seq_start_x <= '0';\r
- reg_data_x <= reg_data;\r
+ i2c_data_x <= i2c_data;\r
read_seq_ctr_x <= read_seq_ctr;\r
\r
case STATE is\r
\r
when S_RESET =>\r
- reg_data_x <= (others => '0');\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_data_x <= (others => '0');\r
+ NEXT_STATE <= S_IDLE;\r
\r
when S_IDLE =>\r
if (i2c_start = '1') then\r
- reg_data_x <= x"8000_0000"; -- Set Running , clear all other bits \r
- NEXT_STATE <= S_START;\r
+ i2c_data_x <= x"8000_0000"; -- Set Running, clear all other bits \r
+ NEXT_STATE <= S_START;\r
else\r
- i2c_busy_x <= '0';\r
- reg_data_x <= reg_data and x"7fff_ffff"; -- clear running bit;\r
- read_seq_ctr_x <= '0';\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_busy_x <= '0';\r
+ i2c_data_x <= i2c_data and x"7fff_ffff"; -- clear running bit;\r
+ read_seq_ctr_x <= '0';\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
-- I2C START Sequence \r
else\r
scl_o <= '0';\r
if (sendbyte_ack = '0') then\r
- reg_data_x <= reg_data or x"0100_0000";\r
+ i2c_data_x <= i2c_data or x"0100_0000";\r
NEXT_STATE <= S_STOP;\r
else\r
if (read_seq_ctr = '0') then\r
else\r
scl_o <= '0';\r
if (sendbyte_ack = '0') then\r
- reg_data_x <= reg_data or x"0200_0000";\r
+ i2c_data_x <= i2c_data or x"0200_0000";\r
NEXT_STATE <= S_STOP;\r
else\r
if (i2c_rw_bit = '0') then\r
else\r
scl_o <= '0';\r
if (sendbyte_ack = '0') then\r
- reg_data_x <= reg_data or x"0400_0000";\r
+ i2c_data_x <= i2c_data or x"0400_0000";\r
end if;\r
NEXT_STATE <= S_STOP;\r
end if;\r
NEXT_STATE <= S_GET_DATA_WAIT;\r
else\r
scl_o <= '0';\r
- reg_data_x(7 downto 0) <= readbyte_byte; \r
+ i2c_data_x(7 downto 0) <= readbyte_byte; \r
NEXT_STATE <= S_STOP;\r
end if;\r
\r
if (startstop_done = '0') then\r
NEXT_STATE <= S_STOP_WAIT;\r
else\r
- reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit\r
- NEXT_STATE <= S_IDLE;\r
+ i2c_data_x <= i2c_data or x"4000_0000"; -- Set DONE Bit\r
+ NEXT_STATE <= S_IDLE;\r
end if;\r
\r
end case;\r
end process PROC_I2C_MASTER;\r
\r
+ PROC_I2C_DATA_MULTIPLEXER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ i2c_data_internal_o <= (others => '0');\r
+ i2c_data_slave <= (others => '0');\r
+ command_busy_o <= '0';\r
+ else\r
+ if (internal_command = '0' and internal_command_d = '0') then \r
+ i2c_data_slave <= i2c_data;\r
+ else\r
+ i2c_data_internal_o <= i2c_data;\r
+ end if;\r
+ end if;\r
+ command_busy_o <= i2c_busy;\r
+ end if;\r
+ end process PROC_I2C_DATA_MULTIPLEXER;\r
+ \r
-----------------------------------------------------------------------------\r
-- TRBNet Slave Bus\r
-----------------------------------------------------------------------------\r
-- D[31] I2C_GO 0 => don't do anything on I2C,\r
-- 1 => start I2C access\r
-- D[30] I2C_ACTION 0 => write byte, 1 => read byte\r
- -- D[29:24] I2C_SPEED set to all '1'\r
+ -- D[29:24] I2C_SPEED set all to '1'\r
-- D[23:16] I2C_ADDRESS address of I2C chip\r
-- D[15:8] I2C_CMD command byte for access\r
-- D[7:0] I2C_DATA data to be written\r
slv_unknown_addr_o <= '0';\r
slv_ack_o <= '0';\r
i2c_start <= '0';\r
+ internal_command <= '0';\r
+ internal_command_d <= '0';\r
\r
i2c_chipid <= (others => '0'); \r
i2c_rw_bit <= '0'; \r
i2c_register_value_read <= (others => '0');\r
\r
else\r
- slv_ack_o <= '1';\r
slv_unknown_addr_o <= '0';\r
slv_no_more_data_o <= '0';\r
slv_data_out_o <= (others => '0');\r
i2c_start <= '0';\r
- \r
- if (SLV_WRITE_IN = '1') then\r
- if (i2c_busy = '0' and SLV_DATA_IN(31) = '1') then\r
- i2c_rw_bit <= SLV_DATA_IN(30);\r
- i2c_chipid <= SLV_DATA_IN(22 downto 16);\r
- i2c_registerid <= SLV_DATA_IN(15 downto 8);\r
- i2c_register_data <= SLV_DATA_IN(7 downto 0); \r
- i2c_start <= '1';\r
- end if;\r
\r
+ internal_command_d <= internal_command;\r
+ \r
+ if (i2c_busy = '0' and internal_command_d = '1') then\r
+ internal_command <= '0';\r
+ slv_ack_o <= '0';\r
+\r
+ elsif (i2c_busy = '0' and INTERNAL_COMMAND_IN(31) = '1') then\r
+ -- Internal Interface Command\r
+ i2c_rw_bit <= INTERNAL_COMMAND_IN(30);\r
+ i2c_chipid <= INTERNAL_COMMAND_IN(22 downto 16);\r
+ i2c_registerid <= INTERNAL_COMMAND_IN(15 downto 8);\r
+ i2c_register_data <= INTERNAL_COMMAND_IN(7 downto 0); \r
+ i2c_start <= '1';\r
+ internal_command <= '1';\r
+ slv_ack_o <= '0';\r
+\r
+ elsif (SLV_WRITE_IN = '1') then\r
+ if (internal_command = '0' and\r
+ I2C_LOCK_IN = '0' and\r
+ i2c_busy = '0' and\r
+ SLV_DATA_IN(31) = '1') then\r
+ i2c_rw_bit <= SLV_DATA_IN(30);\r
+ i2c_chipid <= SLV_DATA_IN(22 downto 16);\r
+ i2c_registerid <= SLV_DATA_IN(15 downto 8);\r
+ i2c_register_data <= SLV_DATA_IN(7 downto 0); \r
+ i2c_start <= '1';\r
+ slv_ack_o <= '1';\r
+ else\r
+ slv_no_more_data_o <= '1';\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ \r
elsif (SLV_READ_IN = '1') then\r
- if (i2c_busy = '1') then\r
+ if (internal_command = '0' and\r
+ I2C_LOCK_IN = '0' and\r
+ i2c_busy = '0') then\r
+ slv_data_out_o <= i2c_data_slave;\r
+ slv_ack_o <= '1';\r
+ else\r
slv_data_out_o <= (others => '0');\r
slv_no_more_data_o <= '1';\r
slv_ack_o <= '0';\r
- else\r
- slv_data_out_o <= reg_data;\r
end if;\r
\r
else\r
- slv_ack_o <= '0';\r
+ slv_ack_o <= '0';\r
end if;\r
+\r
end if;\r
end if; \r
end process PROC_SLAVE_BUS;\r
-----------------------------------------------------------------------------\r
\r
-- I2C Outputs\r
- SDA_INOUT <= '0' when (sda_o = '0' or\r
- sda_startstop = '0' or\r
- sda_sendbyte = '0' or\r
- sda_readbyte = '0')\r
- else 'Z';\r
+ SDA_INOUT <= '0' when (sda_o = '0' or\r
+ sda_startstop = '0' or\r
+ sda_sendbyte = '0' or\r
+ sda_readbyte = '0')\r
+ else 'Z';\r
\r
- SCL_INOUT <= '0' when (scl_o = '0' or\r
- scl_startstop = '0' or\r
- scl_sendbyte = '0' or\r
- scl_readbyte = '0')\r
- else 'Z';\r
+ SCL_INOUT <= '0' when (scl_o = '0' or\r
+ scl_startstop = '0' or\r
+ scl_sendbyte = '0' or\r
+ scl_readbyte = '0')\r
+ else 'Z';\r
+\r
+ COMMAND_BUSY_OUT <= command_busy_o;\r
+ I2C_DATA_OUT <= i2c_data_internal_o;\r
\r
-- Slave Bus\r
SLV_DATA_OUT <= slv_data_out_o; \r
S_READ_BYTE,\r
S_UNSET_SCL1,\r
S_SET_SCL1,\r
- s_GET_BIT,\r
+ S_GET_BIT,\r
S_SET_SCL2,\r
S_UNSET_SCL2,\r
S_NEXT_BIT,\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+\r
+entity nx_setup is\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ I2C_COMMAND_OUT : out std_logic_vector(31 downto 0);\r
+ I2C_COMMAND_BUSY_IN : in std_logic;\r
+ I2C_DATA_IN : in std_logic_vector(31 downto 0);\r
+ I2C_LOCK : out std_logic;\r
+\r
+ SPI_COMMAND_OUT : out std_logic_vector(31 downto 0);\r
+ SPI_COMMAND_BUSY_IN : in std_logic;\r
+ SPI_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SPI_LOCK : out std_logic;\r
+ \r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of nx_setup is\r
+\r
+ -- Send I2C Command\r
+ type I2C_STATES is (I2C_IDLE,\r
+ I2C_WAIT_BUSY_HIGH,\r
+ I2C_WAIT_BUSY_LOW\r
+ );\r
+\r
+ signal I2C_STATE : I2C_STATES;\r
+ \r
+ signal spi_command_o : std_logic_vector(31 downto 0);\r
+ signal i2c_lock_o : std_logic;\r
+ signal i2c_command_o : std_logic_vector(31 downto 0);\r
+ signal i2c_command : std_logic_vector(31 downto 0);\r
+ signal i2c_command_busy : std_logic;\r
+ signal i2c_command_done : std_logic;\r
+ signal i2c_data : std_logic_vector(31 downto 0);\r
+\r
+ -- Write I2C Registers\r
+ type W_STATES is (W_IDLE,\r
+ W_NEXT_REGISTER,\r
+ W_NOP,\r
+ W_REGISTER,\r
+ W_WAIT_DONE\r
+ );\r
+\r
+ signal W_STATE, W_STATE_RETURN : W_STATES;\r
+\r
+ signal write_defaults_start : std_logic;\r
+ signal write_i2c_command : std_logic_vector(31 downto 0);\r
+ signal write_i2c_lock : std_logic; \r
+ signal w_register_ctr : unsigned(7 downto 0);\r
+ \r
+ signal nx_ram_output_addr_i : std_logic_vector(5 downto 0);\r
+ signal nx_ram_input_addr_i : std_logic_vector(5 downto 0);\r
+ signal nx_ram_input_i : std_logic_vector(7 downto 0);\r
+ signal nx_ram_write_i : std_logic;\r
+\r
+ -- Read I2C Registers\r
+ type R_STATES is (R_IDLE,\r
+ R_REGISTER,\r
+ R_NEXT_REGISTER,\r
+ R_WAIT_DONE\r
+ );\r
+ \r
+ signal R_STATE, R_STATE_RETURN : R_STATES;\r
+\r
+ signal read_defaults_start : std_logic;\r
+ signal read_i2c_command : std_logic_vector(31 downto 0);\r
+ signal read_i2c_lock : std_logic; \r
+ signal r_register_ctr : unsigned(7 downto 0);\r
+ \r
+ -- RAM Handler\r
+ signal nx_ram_input_addr : std_logic_vector(5 downto 0);\r
+ signal nx_ram_input : std_logic_vector(7 downto 0);\r
+ signal nx_ram_write : std_logic;\r
+ \r
+ signal nx_ram_output_addr : std_logic_vector(5 downto 0);\r
+ signal nx_ram_output : std_logic_vector(7 downto 0);\r
+ \r
+ -- TRBNet Slave Bus\r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+\r
+ signal nx_ram_output_addr_s : std_logic_vector(5 downto 0);\r
+ signal nx_ram_input_addr_s : std_logic_vector(5 downto 0);\r
+ signal nx_ram_input_s : std_logic_vector(7 downto 0);\r
+ signal nx_ram_write_s : std_logic;\r
+ \r
+ signal register_mem_read_s : std_logic;\r
+ signal register_mem_read : std_logic;\r
+\r
+ type register_access_type_t is array(0 to 45) of std_logic;\r
+ constant register_access_type : register_access_type_t :=\r
+ ('1','1','1','1','1','1','1','1', -- 7\r
+ '1','1','1','1','1','1','1','1', -- 15\r
+ '1','1','1','1','1','1','1','1', -- 23\r
+ '1','1','1','1','1','1','0','0', -- 31\r
+ '1','1','0','0','0','0','1','1', --39\r
+ '0','0','1','1','1','1' -- 45\r
+ );\r
+\r
+\r
+ signal read_write_ding : std_logic;\r
+ \r
+begin\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- DEBUG\r
+ -----------------------------------------------------------------------------\r
+\r
+ DEBUG_OUT(0) <= CLK_IN;\r
+ DEBUG_OUT(1) <= read_defaults_start;\r
+ DEBUG_OUT(2) <= write_defaults_start;\r
+ DEBUG_OUT(3) <= i2c_lock_o;\r
+ DEBUG_OUT(4) <= i2c_command_busy;\r
+ DEBUG_OUT(5) <= i2c_command_done;\r
+ DEBUG_OUT(6) <= I2C_COMMAND_BUSY_IN;\r
+ DEBUG_OUT(7) <= register_mem_read_s;\r
+ DEBUG_OUT(8) <= register_mem_read;\r
+ DEBUG_OUT(15 downto 9) <= (others => '0'); \r
+ \r
+ -----------------------------------------------------------------------------\r
+ \r
+ -- Simple RAM to hold all nXyter I2C register settings\r
+\r
+ \r
+ ram_dp_1: ram_dp\r
+ generic map (\r
+ depth => 6,\r
+ width => 8\r
+ )\r
+ port map (\r
+ CLK => CLK_IN,\r
+ wr1 => nx_ram_write,\r
+ a1 => nx_ram_input_addr,\r
+ dout1 => open,\r
+ din1 => nx_ram_input,\r
+ a2 => nx_ram_output_addr,\r
+ dout2 => nx_ram_output \r
+ );\r
+\r
+ nx_ram_output_addr <= nx_ram_output_addr_s or nx_ram_output_addr_i;\r
+ nx_ram_input_addr <= nx_ram_input_addr_s or nx_ram_input_addr_i;\r
+ nx_ram_input <= nx_ram_input_s or nx_ram_input_i;\r
+ nx_ram_write <= nx_ram_write_s or nx_ram_write_i;\r
+ \r
+ ----------------------------------------------------------------------\r
+\r
+ i2c_lock_o <= write_i2c_lock or read_i2c_lock;\r
+ i2c_command <= write_i2c_command or read_i2c_command;\r
+\r
+ PROC_SEND_I2C_COMMAND: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ i2c_command_o <= (others => '0');\r
+ i2c_command_busy <= '0';\r
+ i2c_command_done <= '0';\r
+ i2c_data <= (others => '0');\r
+ I2C_STATE <= I2C_IDLE;\r
+ else\r
+ i2c_command_o <= (others => '0');\r
+ i2c_command_busy <= '0';\r
+ i2c_command_done <= '0';\r
+ \r
+ case I2C_STATE is\r
+\r
+ when I2C_IDLE =>\r
+ if (i2c_command(31) = '1') then\r
+ i2c_command_o <= i2c_command;\r
+ i2c_command_busy <= '1';\r
+ I2C_STATE <= I2C_WAIT_BUSY_HIGH;\r
+ else\r
+ I2C_STATE <= I2C_IDLE;\r
+ end if;\r
+\r
+ when I2C_WAIT_BUSY_HIGH =>\r
+ if (I2C_COMMAND_BUSY_IN = '0') then\r
+ i2c_command_o <= i2c_command_o;\r
+ i2c_command_busy <= '1';\r
+ I2C_STATE <= I2C_WAIT_BUSY_HIGH;\r
+ else\r
+ i2c_command_busy <= '1';\r
+ I2C_STATE <= I2C_WAIT_BUSY_LOW;\r
+ end if;\r
+\r
+ when I2C_WAIT_BUSY_LOW =>\r
+ if (I2C_COMMAND_BUSY_IN = '1') then\r
+ i2c_command_busy <= '1';\r
+ I2C_STATE <= I2C_WAIT_BUSY_LOW;\r
+ else\r
+ i2c_data <= I2C_DATA_IN;\r
+ i2c_command_done <= '1';\r
+ i2c_command_busy <= '1';\r
+ I2C_STATE <= I2C_IDLE;\r
+ end if;\r
+ end case;\r
+ \r
+ end if;\r
+ end if;\r
+ end process PROC_SEND_I2C_COMMAND;\r
+\r
+PROC_WRITE_REGISTERS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ write_i2c_lock <= '0';\r
+ write_i2c_command <= (others => '0');\r
+ w_register_ctr <= (others => '0');\r
+ \r
+ nx_ram_output_addr_i <= (others => '0');\r
+\r
+ W_STATE_RETURN <= W_IDLE;\r
+ W_STATE <= W_IDLE;\r
+ else\r
+ write_i2c_command <= (others => '0');\r
+ write_i2c_lock <= '1';\r
+\r
+ nx_ram_output_addr_i <= (others => '0');\r
+ read_write_ding <= '0';\r
+ \r
+ case W_STATE is\r
+\r
+ when W_IDLE =>\r
+ if (write_defaults_start = '1') then\r
+ w_register_ctr <= (others => '0');\r
+ W_STATE <= W_NEXT_REGISTER;\r
+ else\r
+ write_i2c_lock <= '0';\r
+ W_STATE <= W_IDLE;\r
+ end if;\r
+\r
+ when W_NEXT_REGISTER =>\r
+ if (w_register_ctr <= x"2d") then\r
+ nx_ram_output_addr_i <= w_register_ctr(5 downto 0);\r
+ W_STATE <= W_NOP;\r
+ else\r
+ W_STATE <= W_IDLE;\r
+ end if;\r
+\r
+ when W_NOP =>\r
+ read_write_ding <= '1';\r
+ W_STATE <= W_REGISTER;\r
+ \r
+ when W_REGISTER =>\r
+ if (register_access_type(\r
+ to_integer(unsigned(w_register_ctr))) = '1') \r
+ then\r
+ write_i2c_command(31 downto 16) <= x"bf08";\r
+ write_i2c_command(15 downto 8) <= w_register_ctr;\r
+ write_i2c_command(7 downto 0) <= nx_ram_output;\r
+ W_STATE_RETURN <= W_NEXT_REGISTER;\r
+ W_STATE <= W_WAIT_DONE;\r
+ else\r
+ W_STATE <= W_NEXT_REGISTER;\r
+ end if;\r
+\r
+ w_register_ctr <= w_register_ctr + 1;\r
+ \r
+ when W_WAIT_DONE =>\r
+ if (i2c_command_done = '0') then\r
+ W_STATE <= W_WAIT_DONE;\r
+ else\r
+ W_STATE <= W_STATE_RETURN;\r
+ end if;\r
+\r
+ end case;\r
+ end if;\r
+ end if;\r
+ end process PROC_WRITE_REGISTERS;\r
+\r
+ PROC_READ_REGISTERS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ read_i2c_command <= (others => '0');\r
+ read_i2c_lock <= '0';\r
+ r_register_ctr <= (others => '0');\r
+\r
+ nx_ram_input_addr_i <= (others => '0');\r
+ nx_ram_input_i <= (others => '0');\r
+ nx_ram_write_i <= '0';\r
+\r
+ R_STATE_RETURN <= R_IDLE;\r
+ R_STATE <= R_IDLE;\r
+ else\r
+ read_i2c_command <= (others => '0');\r
+ read_i2c_lock <= '1';\r
+\r
+ nx_ram_input_addr_i <= (others => '0');\r
+ nx_ram_input_i <= (others => '0');\r
+ nx_ram_write_i <= '0';\r
+\r
+ case R_STATE is\r
+ when R_IDLE =>\r
+ if (read_defaults_start = '1') then\r
+ r_register_ctr <= (others => '0');\r
+ R_STATE <= R_REGISTER;\r
+ else\r
+ read_i2c_lock <= '0';\r
+ R_STATE <= R_IDLE;\r
+ end if;\r
+\r
+ when R_REGISTER =>\r
+ if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+ read_i2c_command(31 downto 16) <= x"ff08";\r
+ read_i2c_command(15 downto 8) <= r_register_ctr;\r
+ read_i2c_command(7 downto 0) <= (others => '0');\r
+ R_STATE_RETURN <= R_NEXT_REGISTER;\r
+ R_STATE <= R_WAIT_DONE;\r
+ else\r
+ R_STATE <= R_NEXT_REGISTER;\r
+ end if;\r
+ \r
+ when R_NEXT_REGISTER =>\r
+ if (register_access_type(to_integer(r_register_ctr)) = '1') then\r
+ nx_ram_input_i <= i2c_data(7 downto 0);\r
+ else\r
+ nx_ram_input_i <= x"be";\r
+ end if;\r
+ nx_ram_write_i <= '1';\r
+ nx_ram_input_addr_i <= r_register_ctr(5 downto 0);\r
+ \r
+ if (r_register_ctr <= x"2d") then\r
+ r_register_ctr <= r_register_ctr + 1;\r
+ R_STATE <= R_REGISTER;\r
+ else\r
+ R_STATE <= R_IDLE;\r
+ end if;\r
+ \r
+ when R_WAIT_DONE =>\r
+ if (i2c_command_done = '0') then\r
+ R_STATE <= R_WAIT_DONE;\r
+ else\r
+ R_STATE <= R_STATE_RETURN;\r
+ end if;\r
+\r
+ end case;\r
+ end if;\r
+ end if;\r
+ end process PROC_READ_REGISTERS;\r
+ \r
+ PROC_SLAVE_BUS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ write_defaults_start <= '0';\r
+ read_defaults_start <= '0';\r
+ register_mem_read_s <= '0';\r
+ register_mem_read <= '0';\r
+ nx_ram_output_addr_s <= (others => '0'); \r
+ nx_ram_input_addr_s <= (others => '0');\r
+ nx_ram_input_s <= (others => '0');\r
+ nx_ram_write_s <= '0';\r
+ else \r
+ slv_data_out_o <= (others => '0');\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ write_defaults_start <= '0';\r
+ read_defaults_start <= '0';\r
+ register_mem_read_s <= '0';\r
+ register_mem_read <= register_mem_read_s;\r
+ nx_ram_output_addr_s <= (others => '0');\r
+ nx_ram_input_addr_s <= (others => '0');\r
+ nx_ram_input_s <= (others => '0');\r
+ nx_ram_write_s <= '0';\r
+\r
+ if (register_mem_read = '1') then\r
+ slv_data_out_o(7 downto 0) <= nx_ram_output;\r
+ slv_data_out_o(31 downto 8) <= (others => '0');\r
+ slv_ack_o <= '1';\r
+\r
+ \r
+ elsif (SLV_WRITE_IN = '1') then\r
+ if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
+ if (i2c_lock_o = '1') then\r
+ slv_no_more_data_o <= '1';\r
+ slv_ack_o <= '0';\r
+ else\r
+ if (register_access_type(\r
+ to_integer(unsigned(SLV_ADDR_IN(5 downto 0)))) = '1')\r
+ then\r
+ nx_ram_input_addr_s <= SLV_ADDR_IN(5 downto 0);\r
+ nx_ram_input_s <= SLV_DATA_IN(7 downto 0);\r
+ nx_ram_write_s <= '1';\r
+ end if;\r
+ slv_ack_o <= '1';\r
+ end if;\r
+\r
+ else\r
+ case SLV_ADDR_IN is\r
+ when x"0040" =>\r
+ write_defaults_start <= '1';\r
+ slv_ack_o <= '1';\r
+ \r
+ when x"0041" =>\r
+ read_defaults_start <= '1';\r
+ slv_ack_o <= '1';\r
+ \r
+ when others => \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0'; \r
+ \r
+ end case; \r
+ end if;\r
+\r
+ elsif (SLV_READ_IN = '1') then\r
+ if (SLV_ADDR_IN >= x"0000" and SLV_ADDR_IN <= x"002d") then\r
+ nx_ram_output_addr_s <= SLV_ADDR_IN(5 downto 0);\r
+ register_mem_read_s <= '1';\r
+ slv_ack_o <= '0';\r
+ else\r
+ case SLV_ADDR_IN is \r
+ when x"0040" => \r
+ slv_data_out_o <= x"deadbeef";\r
+ slv_ack_o <= '1';\r
+ \r
+ when x"0041" => \r
+ slv_data_out_o <= i2c_data;\r
+ slv_ack_o <= '1';\r
+ \r
+ when others => \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
+ \r
+ end case; \r
+ end if;\r
+\r
+ else \r
+ slv_ack_o <= '0';\r
+ end if;\r
+\r
+ end if;\r
+ end if; \r
+ end process PROC_SLAVE_BUS;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+ \r
+ I2C_COMMAND_OUT <= i2c_command_o;\r
+ I2C_LOCK <= i2c_lock_o;\r
+ \r
+ SPI_COMMAND_OUT <= spi_command_o;\r
+ spi_command_o <= (others => '0');\r
+\r
+ -- Slave Bus\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
+\r
+end Behavioral;\r
\r
entity nx_trigger_handler is\r
port (\r
- CLK_IN : in std_logic;\r
- RESET_IN : in std_logic;\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
\r
- -- IN\r
- TRIGGER_IN : in std_logic;\r
- TRIGGER_RELEASE_IN : in std_logic;\r
+ NXYTER_OFFLINE_IN : in std_logic;\r
+ \r
+ --LVL1 trigger\r
+ LVL1_TRG_DATA_VALID_IN : in std_logic; -- timing trigger valid, later\r
+ LVL1_VALID_TIMING_TRG_IN : in std_logic; -- timing trigger synced\r
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- timing trigger raw\r
+ LVL1_INVALID_TRG_IN : in std_logic; -- ???\r
\r
- -- OUT\r
- TRIGGER_OUT : out std_logic;\r
- TIMESTAMP_HOLD_OUT : out std_logic;\r
- TRIGGER_BUSY_OUT : out std_logic;\r
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);\r
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);\r
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);\r
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);\r
+\r
+ FEE_TRG_RELEASE_OUT : out std_logic;\r
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);\r
+\r
+ -- Internal FPGA Trigger\r
+ INTERNAL_TRIGGER_IN : in std_logic;\r
\r
- -- Slave bus \r
- SLV_READ_IN : in std_logic;\r
- SLV_WRITE_IN : in std_logic;\r
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
- SLV_ACK_OUT : out std_logic;\r
- SLV_NO_MORE_DATA_OUT : out std_logic;\r
- SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ -- Trigger FeedBack\r
+ TRIGGER_VALIDATE_BUSY_IN : in std_logic;\r
+ LVL2_TRIGGER_BUSY_IN : in std_logic;\r
\r
- -- Debug Line\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ -- OUT\r
+ VALIDATE_TRIGGER_OUT : out std_logic;\r
+ TIMESTAMP_HOLD_OUT : out std_logic;\r
+ LVL2_TRIGGER_OUT : out std_logic;\r
+ EVENT_BUFFER_CLEAR_OUT : out std_logic;\r
+ FAST_CLEAR_OUT : out std_logic;\r
+ TRIGGER_BUSY_OUT : out std_logic;\r
+ \r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ \r
+ -- Debug Line \r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
);\r
end entity;\r
\r
architecture Behavioral of nx_trigger_handler is\r
\r
- signal start_cycle : std_logic;\r
- signal wait_timer_init : unsigned(7 downto 0);\r
- signal wait_timer_done : std_logic;\r
- signal trigger_o : std_logic;\r
- signal timestamp_hold_o : std_logic;\r
- signal trigger_busy_o : std_logic;\r
- \r
+ -- Trigger Handler\r
+ signal validate_trigger_o : std_logic;\r
+ signal timestamp_hold : std_logic;\r
+ signal lvl2_trigger_o : std_logic;\r
+ signal evt_buffer_clear_o : std_logic;\r
+ signal fast_clear_o : std_logic;\r
+ signal trigger_busy_o : std_logic;\r
+ signal fee_trg_release_o : std_logic;\r
+ signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);\r
+\r
type STATES is (S_IDLE,\r
- S_START,\r
- S_WAIT_TRIGGER_RELEASE\r
+ S_CTS_TRIGGER,\r
+ S_WAIT_TRG_DATA_VALID,\r
+ S_WAIT_LVL2_TRIGGER_DONE,\r
+ S_FEE_TRIGGER_RELEASE,\r
+ S_WAIT_FEE_TRIGGER_RELEASE_ACK,\r
+ S_INTERNAL_TRIGGER,\r
+ S_WAIT_TRIGGER_VALIDATE_ACK,\r
+ S_WAIT_TRIGGER_VALIDATE_DONE\r
);\r
signal STATE : STATES;\r
- \r
- -- TRBNet Slave Bus \r
+\r
+ -- Timestamp Hold Handler\r
+ type TS_STATES is (TS_IDLE,\r
+ TS_WAIT_TIMER_DONE\r
+ );\r
+ signal TS_STATE : TS_STATES;\r
+\r
+ signal timestamp_hold_o : std_logic;\r
+ signal wait_timer_init : unsigned(7 downto 0);\r
+ signal wait_timer_done : std_logic;\r
+ \r
+ -- TRBNet Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
signal slv_no_more_data_o : std_logic;\r
signal slv_unknown_addr_o : std_logic;\r
\r
-- Debug Line\r
DEBUG_OUT(0) <= CLK_IN;\r
- DEBUG_OUT(1) <= TRIGGER_IN;\r
- DEBUG_OUT(2) <= trigger_o;\r
- DEBUG_OUT(3) <= timestamp_hold_o;\r
- DEBUG_OUT(4) <= wait_timer_done;\r
- DEBUG_OUT(15 downto 5) <= (others => '0');\r
+ DEBUG_OUT(1) <= LVL1_VALID_TIMING_TRG_IN;\r
+ DEBUG_OUT(2) <= LVL1_TRG_DATA_VALID_IN;\r
+ DEBUG_OUT(3) <= INTERNAL_TRIGGER_IN;\r
+ DEBUG_OUT(4) <= TRIGGER_VALIDATE_BUSY_IN;\r
+ DEBUG_OUT(5) <= LVL2_TRIGGER_BUSY_IN;\r
+\r
+ DEBUG_OUT(6) <= validate_trigger_o;\r
+ DEBUG_OUT(7) <= timestamp_hold_o;\r
+ DEBUG_OUT(8) <= lvl2_trigger_o;\r
+ DEBUG_OUT(9) <= evt_buffer_clear_o;\r
+ DEBUG_OUT(10) <= fee_trg_release_o;\r
+ DEBUG_OUT(11) <= trigger_busy_o;\r
+ \r
+ DEBUG_OUT(15 downto 12) <= (others => '0');\r
\r
-- Timer\r
nx_timer_1: nx_timer\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1') then\r
- trigger_o <= '0';\r
- timestamp_hold_o <= '0';\r
- trigger_busy_o <= '1';\r
- wait_timer_init <= (others => '0');\r
- STATE <= S_IDLE;\r
+ validate_trigger_o <= '0';\r
+ timestamp_hold <= '0';\r
+ lvl2_trigger_o <= '0';\r
+ fee_trg_release_o <= '0';\r
+ fee_trg_statusbits_o <= (others => '0');\r
+ evt_buffer_clear_o <= '0';\r
+ trigger_busy_o <= '0';\r
+ STATE <= S_IDLE;\r
else\r
- trigger_o <= '0';\r
- timestamp_hold_o <= '0';\r
- trigger_busy_o <= '1';\r
- wait_timer_init <= (others => '0');\r
+ validate_trigger_o <= '0';\r
+ timestamp_hold <= '0';\r
+ lvl2_trigger_o <= '0';\r
+ fee_trg_release_o <= '0';\r
+ fee_trg_statusbits_o <= (others => '0');\r
+ evt_buffer_clear_o <= '0';\r
+ trigger_busy_o <= '1';\r
\r
case STATE is\r
when S_IDLE =>\r
- if (TRIGGER_IN = '1') then\r
- trigger_o <= '1';\r
- timestamp_hold_o <= '1';\r
- STATE <= S_START;\r
+ if (LVL1_VALID_TIMING_TRG_IN = '1') then\r
+ if (NXYTER_OFFLINE_IN = '1') then\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+ else\r
+ STATE <= S_CTS_TRIGGER;\r
+ end if;\r
+ elsif (INTERNAL_TRIGGER_IN = '1') then\r
+ STATE <= S_INTERNAL_TRIGGER;\r
+ else\r
+ trigger_busy_o <= '0';\r
+ STATE <= S_IDLE;\r
+ end if; \r
+\r
+ -- CTS Trigger Handler\r
+ when S_CTS_TRIGGER =>\r
+ evt_buffer_clear_o <= '1';\r
+ validate_trigger_o <= '1';\r
+ timestamp_hold <= '1';\r
+ lvl2_trigger_o <= '1';\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+\r
+ when S_WAIT_TRG_DATA_VALID =>\r
+ if (LVL1_TRG_DATA_VALID_IN = '0') then\r
+ STATE <= S_WAIT_TRG_DATA_VALID;\r
+ else\r
+ STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
+ end if;\r
+\r
+ when S_WAIT_LVL2_TRIGGER_DONE =>\r
+ if (LVL2_TRIGGER_BUSY_IN = '1') then\r
+ STATE <= S_WAIT_LVL2_TRIGGER_DONE;\r
+ else\r
+ STATE <= S_FEE_TRIGGER_RELEASE;\r
+ end if;\r
+\r
+ when S_FEE_TRIGGER_RELEASE =>\r
+ fee_trg_release_o <= '1';\r
+ STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
+ \r
+ when S_WAIT_FEE_TRIGGER_RELEASE_ACK =>\r
+ if (LVL1_TRG_DATA_VALID_IN = '1') then\r
+ STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;\r
else\r
- trigger_busy_o <= '0';\r
- STATE <= S_IDLE;\r
+ STATE <= S_IDLE;\r
end if;\r
+ \r
+ -- Internal Trigger Handler\r
+ when S_INTERNAL_TRIGGER =>\r
+ validate_trigger_o <= '1';\r
+ timestamp_hold <= '1';\r
+ evt_buffer_clear_o <= '1';\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
\r
- when S_START =>\r
- STATE <= S_WAIT_TRIGGER_RELEASE;\r
+ when S_WAIT_TRIGGER_VALIDATE_ACK =>\r
+ if (TRIGGER_VALIDATE_BUSY_IN = '0') then\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;\r
+ else\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
+ end if;\r
\r
- when S_WAIT_TRIGGER_RELEASE =>\r
- if (TRIGGER_RELEASE_IN = '0') then\r
- STATE <= S_WAIT_TRIGGER_RELEASE;\r
+ when S_WAIT_TRIGGER_VALIDATE_DONE =>\r
+ if (TRIGGER_VALIDATE_BUSY_IN = '1') then\r
+ STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;\r
else\r
- STATE <= S_IDLE;\r
+ STATE <= S_IDLE;\r
end if;\r
\r
end case;\r
end if;\r
end process PROC_TRIGGER_HANDLER;\r
\r
+ PROC_SEND_TIMSTAMP_HOLD: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if (RESET_IN = '1' or NXYTER_OFFLINE_IN = '1') then\r
+ wait_timer_init <= (others => '0');\r
+ timestamp_hold_o <= '0';\r
+ TS_STATE <= TS_IDLE;\r
+ else\r
+ wait_timer_init <= (others => '0');\r
+ timestamp_hold_o <= '0';\r
+\r
+ case TS_STATE is\r
+\r
+ when TS_IDLE =>\r
+ if (timestamp_hold = '0') then\r
+ TS_STATE <= TS_IDLE;\r
+ else\r
+ wait_timer_init <= reg_timestamp_hold_delay;\r
+ TS_STATE <= TS_WAIT_TIMER_DONE;\r
+ end if;\r
+\r
+ when TS_WAIT_TIMER_DONE =>\r
+ if (wait_timer_done = '0') then\r
+ TS_STATE <= TS_WAIT_TIMER_DONE;\r
+ else\r
+ timestamp_hold_o <= '1';\r
+ TS_STATE <= TS_IDLE;\r
+ end if;\r
+\r
+ end case;\r
+ \r
+ end if;\r
+ end if;\r
+ end process PROC_SEND_TIMSTAMP_HOLD;\r
+\r
-----------------------------------------------------------------------------\r
-- TRBNet Slave Bus\r
-----------------------------------------------------------------------------\r
slv_data_out_o <= (others => '0');\r
slv_no_more_data_o <= '0';\r
slv_unknown_addr_o <= '0';\r
- start_cycle <= '0';\r
slv_ack_o <= '0';\r
- reg_timestamp_hold_delay <= x"01";\r
+ reg_timestamp_hold_delay <= x"3f";\r
else\r
slv_unknown_addr_o <= '0';\r
slv_no_more_data_o <= '0';\r
slv_data_out_o <= (others => '0');\r
slv_ack_o <= '0';\r
- start_cycle <= '0';\r
\r
if (SLV_WRITE_IN = '1') then\r
case SLV_ADDR_IN is\r
when x"0000" =>\r
- reg_timestamp_hold_delay <= SLV_DATA_IN(7 downto 0);\r
- slv_ack_o <= '1';\r
+ if (unsigned(SLV_DATA_IN(7 downto 0)) > 0) then\r
+ reg_timestamp_hold_delay <= unsigned(SLV_DATA_IN(7 downto 0));\r
+ end if;\r
+ slv_ack_o <= '1';\r
\r
when others =>\r
- slv_unknown_addr_o <= '1';\r
+ slv_unknown_addr_o <= '1';\r
\r
end case;\r
\r
when x"0000" =>\r
slv_data_out_o(7 downto 0) <=\r
std_logic_vector(reg_timestamp_hold_delay);\r
- slv_data_out_o(31 downto 8) <= (others => '0');\r
+ slv_data_out_o(31 downto 8) <= (others => '0');\r
slv_ack_o <= '1';\r
\r
when others =>\r
-----------------------------------------------------------------------------\r
-- Output Signals\r
-----------------------------------------------------------------------------\r
- \r
+\r
-- Trigger Output\r
- TRIGGER_OUT <= trigger_o;\r
- TIMESTAMP_HOLD_OUT <= timestamp_hold_o;\r
- TRIGGER_BUSY_OUT <= trigger_busy_o;\r
- \r
- -- Slave Bus\r
- SLV_DATA_OUT <= slv_data_out_o; \r
- SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
- SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
- SLV_ACK_OUT <= slv_ack_o; \r
+ VALIDATE_TRIGGER_OUT <= validate_trigger_o;\r
+ TIMESTAMP_HOLD_OUT <= timestamp_hold_o;\r
+ LVL2_TRIGGER_OUT <= lvl2_trigger_o;\r
+ EVENT_BUFFER_CLEAR_OUT <= evt_buffer_clear_o;\r
+ FAST_CLEAR_OUT <= fast_clear_o;\r
+ TRIGGER_BUSY_OUT <= trigger_busy_o;\r
+ FEE_TRG_RELEASE_OUT <= fee_trg_release_o;\r
+ FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;\r
+\r
+ -- Slave Bus \r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
\r
end Behavioral;\r
ADC_DATA_IN : in std_logic_vector(11 downto 0);
NX_TOKEN_RETURN_IN : in std_logic;
NX_NOMORE_DATA_IN : in std_logic;
-
+
+ TRIGGER_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
TIMESTAMP_REF_IN : in unsigned(11 downto 0);
- TRIGGER_IN : in std_logic;
-
+
-- Outputs
- PROCESS_BUSY_OUT : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
- DATA_FIFO_RESET_OUT : out std_logic;
+ NOMORE_DATA_OUT : out std_logic;
-- Slave bus
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
SLV_ACK_OUT : out std_logic;
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic;
signal timestamp_ref : unsigned(11 downto 0);
-- Process Channel_Status
- signal channel_index : unsigned(6 downto 0);
- signal channel_wait : unsigned(127 downto 0);
- signal channel_done : unsigned(127 downto 0);
+ signal channel_index : std_logic_vector(6 downto 0);
+ signal channel_wait : std_logic_vector(127 downto 0);
+ signal channel_done : std_logic_vector(127 downto 0);
signal channel_all_done : std_logic;
-
+
+ -- Channel Status Commands
type CS_CMDS is (CS_RESET,
CS_TOKEN_UPDATE,
CS_SET_WAIT,
-- Process Trigger Handler
signal store_to_fifo : std_logic;
- signal data_fifo_reset_o : std_logic;
- signal process_busy_o : std_logic;
+ signal trigger_busy_o : std_logic;
+ signal nomore_data_o : std_logic;
signal wait_timer_init : unsigned(11 downto 0);
- signal token_return_ctr : unsigned(3 downto 0);
+ signal token_return_ctr : std_logic;
signal ch_status_cmd_tr : CS_CMDS;
type STATES is (S_IDLE,
S_WAIT_DATA,
S_PROCESS_START,
S_WAIT_PROCESS_END,
- S_WRITE_TRAILER
+ S_WRITE_TRAILER,
+ S_SET_NOMORE_DATA
);
signal STATE : STATES;
signal trigger_window_width : unsigned(11 downto 0);
signal trigger_window_delay : unsigned(11 downto 0);
signal readout_time_max : unsigned(11 downto 0);
-
+
+ signal window_lower_thr_r : std_logic_vector(11 downto 0);
+ signal window_upper_thr_r : std_logic_vector(11 downto 0);
+
begin
-- Debug Line
- DEBUG_OUT(0) <= store_to_fifo;
- DEBUG_OUT(1) <= data_fifo_reset_o;
- DEBUG_OUT(2) <= process_busy_o;
- DEBUG_OUT(3) <= channel_all_done;
- DEBUG_OUT(4) <= data_clk_o;
- DEBUG_OUT(5) <= t_data_clk_o;
- DEBUG_OUT(6) <= out_of_window_l;
- DEBUG_OUT(7) <= out_of_window_h;
- DEBUG_OUT(14 downto 8) <= (others => '0');
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(2) <= trigger_busy_o;
+ DEBUG_OUT(3) <= channel_all_done;
+ DEBUG_OUT(4) <= data_clk_o;
+ DEBUG_OUT(5) <= t_data_clk_o;
+ DEBUG_OUT(6) <= out_of_window_l;
+ DEBUG_OUT(7) <= out_of_window_h;
+ DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN;
+ DEBUG_OUT(9) <= NX_NOMORE_DATA_IN;
+ DEBUG_OUT(10) <= store_to_fifo;
+ DEBUG_OUT(15 downto 11) <= (others => '0');
-- Timer
nx_timer_1: nx_timer
data_clk_o <= '0';
out_of_window_l <= '0';
out_of_window_h <= '0';
+ window_lower_thr_r <= (others => '0');
+ window_upper_thr_r <= (others => '0');
else
data_o <= (others => '0');
data_clk_o <= '0';
out_of_window_h <= '0';
ch_status_cmd_pr <= CS_NONE;
- if (store_to_fifo = '1' and DATA_CLK_IN = '1') then
+ if (DATA_CLK_IN = '1' and store_to_fifo = '1') then
ts_ref := timestamp_ref - x"010";
window_lower_thr := trigger_window_delay;
window_upper_thr := window_lower_thr + trigger_window_width;
deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref;
+ window_lower_thr_r <= window_lower_thr;
+ window_upper_thr_r <= window_upper_thr;
+
case readout_mode is
when x"0" => -- RefValue + valid and window filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
if (deltaT < window_lower_thr) then
- out_of_window_l <= '1';
- data_clk_o <= '0';
+ out_of_window_l <= '1';
+ data_clk_o <= '0';
-- IN LUT-Data bit setzten.
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_WAIT;
elsif (deltaT > window_upper_thr) then
- out_of_window_h <= '1';
- data_clk_o <= '0';
+ out_of_window_h <= '1';
+ data_clk_o <= '0';
-- In LUT-Done Bit setzten
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_DONE;
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_DONE;
else
- --data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
+ -- IN LUT-Data bit setzten.
+ channel_index <= CHANNEL_IN;
+ ch_status_cmd_pr <= CS_SET_WAIT;
+
data_o(11 downto 0) <= deltaT;
- data_o(15 downto 12) <= (others => '0');
- --data_o(22 downto 16) <= CHANNEL_IN;
- --data_o(27 downto 23) <= (others => '0');
- --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN;
- --data_o(31) <= '0';
- data_o(27 downto 16) <= ADC_DATA_IN;
- data_o(31 downto 28) <= (others => '0');
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= '0';
data_clk_o <= '1';
- -- IN LUT-Data bit setzten.
- channel_index <= CHANNEL_IN;
- ch_status_cmd_pr <= CS_SET_WAIT;
end if;
end if;
when x"1" => -- RefValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- --data_o( 1 downto 0) <= TIMESTAMP_IN(1 downto 0);
- data_o(11 downto 0) <= deltaT;
- data_o(15 downto 12) <= (others => '0');
- -- data_o(22 downto 16) <= CHANNEL_IN;
- -- data_o(27 downto 23) <= (others => '0');
- -- data_o(30 downto 28) <= TIMESTAMP_STATUS_IN;
- -- data_o(31) <= '0';
- data_o(27 downto 16) <= ADC_DATA_IN;
- data_o(31 downto 28) <= (others => '0');
- data_clk_o <= '1';
+ data_o(11 downto 0) <= deltaT;
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= '0';
+ data_clk_o <= '1';
end if;
when x"3" => -- RefValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
- data_o(13 downto 12) <= (others => '0');
- data_o(15 downto 14) <= (others => '0');
- -- data_o(27 downto 16) <= ts_ref;
- -- data_o(31) <= '0';
- data_o(27 downto 16) <= ADC_DATA_IN;
- data_o(31 downto 28) <= (others => '0');
+ data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= '0';
data_clk_o <= '1';
end if;
when x"4" => -- RawValue
- data_o(13 downto 0) <= TIMESTAMP_IN;
- data_o(15 downto 14) <= (others => '0');
- --data_o(22 downto 16) <= CHANNEL_IN;
- --data_o(27 downto 23) <= (others => '0');
- --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN;
- --data_o(31) <= '0';
- data_o(27 downto 16) <= ADC_DATA_IN;
- data_o(31 downto 28) <= (others => '0');
- data_clk_o <= '1';
+ data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= '0';
+ data_clk_o <= '1';
when x"5" => -- RawValue + valid filter
if (TIMESTAMP_STATUS_IN(1) = '0') then
- data_o(13 downto 0) <= TIMESTAMP_IN;
- data_o(15 downto 14) <= (others => '0');
- --data_o(22 downto 16) <= CHANNEL_IN;
- --data_o(27 downto 23) <= (others => '0');
- --data_o(30 downto 28) <= TIMESTAMP_STATUS_IN;
- --data_o(31) <= '0';
- data_o(27 downto 16) <= ADC_DATA_IN;
- data_o(31 downto 28) <= (others => '0');
- data_clk_o <= '1';
+ data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2);
+ data_o(23 downto 12) <= ADC_DATA_IN;
+ data_o(30 downto 24) <= CHANNEL_IN;
+ data_o(31) <= '0';
+ data_clk_o <= '1';
end if;
when others => null;
-----------------------------------------------------------------------------
PROC_TRIGGER_HANDLER: process(CLK_IN)
+ variable min_validation_time : unsigned(23 downto 0);
+
begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
store_to_fifo <= '0';
- data_fifo_reset_o <= '0';
- process_busy_o <= '0';
+ trigger_busy_o <= '0';
+ nomore_data_o <= '0';
wait_timer_init <= (others => '0');
t_data_o <= (others => '0');
t_data_clk_o <= '0';
busy_time_ctr <= (others => '0');
- token_return_ctr <= (others => '0');
+ token_return_ctr <= '0';
ch_status_cmd_tr <= CS_RESET;
STATE <= S_IDLE;
else
store_to_fifo <= '0';
- data_fifo_reset_o <= '0';
wait_timer_init <= (others => '0');
- process_busy_o <= '1';
+ trigger_busy_o <= '1';
+ nomore_data_o <= '0';
t_data_o <= (others => '0');
t_data_clk_o <= '0';
- token_return_ctr <= token_return_ctr;
ch_status_cmd_tr <= CS_NONE;
+ min_validation_time := x"020" +
+ (trigger_window_delay * 2 +
+ trigger_window_delay / 2) +
+ (trigger_window_width * 2 +
+ trigger_window_width / 2);
+
case STATE is
when S_IDLE =>
if (TRIGGER_IN = '1') then
- busy_time_ctr <= (others => '0');
- STATE <= S_TRIGGER;
+ busy_time_ctr <= (others => '0');
+ STATE <= S_TRIGGER;
else
- process_busy_o <= '0';
- STATE <= S_IDLE;
+ trigger_busy_o <= '0';
+ STATE <= S_IDLE;
end if;
when S_TRIGGER =>
- ch_status_cmd_tr <= CS_RESET;
- data_fifo_reset_o <= '1';
- wait_timer_init <= x"020"; -- wait 320ns for first event
- STATE <= S_WAIT_DATA;
+ ch_status_cmd_tr <= CS_RESET;
+ wait_timer_init <= x"020"; -- wait 320ns for first event
+ STATE <= S_WAIT_DATA;
when S_WAIT_DATA =>
if (wait_timer_done = '0') then
- STATE <= S_WAIT_DATA;
+ STATE <= S_WAIT_DATA;
else
- STATE <= S_PROCESS_START;
+ STATE <= S_PROCESS_START;
end if;
when S_PROCESS_START =>
- token_return_ctr <= (others => '0');
- wait_timer_init <= readout_time_max;
- store_to_fifo <= '1';
- STATE <= S_WAIT_PROCESS_END;
+ token_return_ctr <= '0';
+ wait_timer_init <= readout_time_max;
+ store_to_fifo <= '1';
+ STATE <= S_WAIT_PROCESS_END;
when S_WAIT_PROCESS_END =>
if (wait_timer_done = '1' or
channel_all_done = '1' or
- NX_NOMORE_DATA_IN = '1') then
- STATE <= S_WRITE_TRAILER;
+ (NX_NOMORE_DATA_IN = '1' and
+ busy_time_ctr > min_validation_time(11 downto 0))
+ )
+ then
+ STATE <= S_WRITE_TRAILER;
else
- store_to_fifo <= '1';
- STATE <= S_WAIT_PROCESS_END;
+ store_to_fifo <= '1';
+ STATE <= S_WAIT_PROCESS_END;
-- Check Token_Return
- if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
- if (token_return_ctr > 0) then
- ch_status_cmd_tr <= CS_TOKEN_UPDATE;
+ if (busy_time_ctr > min_validation_time(11 downto 0)) then
+ if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
+ if (token_return_ctr = '1') then
+ ch_status_cmd_tr <= CS_TOKEN_UPDATE;
+ end if;
+ token_return_ctr <= token_return_ctr or '1';
end if;
- token_return_ctr <= token_return_ctr + 1;
end if;
- end if;
+ end if;
+
when S_WRITE_TRAILER =>
- t_data_o <= x"deadaffe";
- t_data_clk_o <= '1';
- ch_status_cmd_tr <= CS_RESET;
- STATE <= S_IDLE;
-
+ t_data_o <= x"deadaffe";
+ t_data_clk_o <= '1';
+ ch_status_cmd_tr <= CS_RESET;
+ STATE <= S_SET_NOMORE_DATA;
+
+ when S_SET_NOMORE_DATA =>
+ nomore_data_o <= '1';
+ STATE <= S_IDLE;
end case;
if (STATE /= S_IDLE) then
- busy_time_ctr <= busy_time_ctr + 1;
+ busy_time_ctr <= busy_time_ctr + 1;
end if;
end if;
end if;
end process PROC_TRIGGER_HANDLER;
+
+ -----------------------------------------------------------------------------
+ -- Channel Status Handler
+ -----------------------------------------------------------------------------
+
+ PROC_CHANNEL_STATUS_CMD: process(ch_status_cmd_tr,
+ ch_status_cmd_pr)
+ begin
+ if (ch_status_cmd_tr /= CS_NONE) then
+ channel_status_cmd <= ch_status_cmd_tr;
+ elsif (ch_status_cmd_pr /= CS_NONE) then
+ channel_status_cmd <= ch_status_cmd_pr;
+ else
+ channel_status_cmd <= CS_NONE;
+ end if;
+ end process PROC_CHANNEL_STATUS_CMD;
+
+
+ PROC_CHANNEL_STATUS: process(CLK_IN)
+ constant all_one : std_logic_vector(127 downto 0) := (others => '1');
+
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1') then
+ channel_wait <= (others => '0');
+ channel_done <= (others => '0');
+ channel_all_done <= '0';
+
+ else
+ -- Check done status
+ if (channel_done = all_one) then
+ channel_all_done <= '1';
+ end if;
+
+ -- Process Command
+ case channel_status_cmd is
+
+ when CS_RESET =>
+ channel_wait <= (others => '0');
+ channel_done <= (others => '0');
+ channel_all_done <= '0';
+
+ when CS_TOKEN_UPDATE =>
+ channel_done <= channel_done or (not channel_wait);
+ channel_wait <= (others => '0');
+
+ when CS_SET_WAIT =>
+ channel_wait(to_integer(unsigned(channel_index))) <= '1';
+
+ when CS_SET_DONE =>
+ channel_done(to_integer(unsigned(channel_index))) <= '1';
+
+ when others => null;
+
+ end case;
+ end if;
+ end if;
+ end process PROC_CHANNEL_STATUS;
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
slv_ack_o <= '1';
when x"0005" =>
+ slv_data_out_o(11 downto 0) <= timestamp_ref;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0006" =>
+ slv_data_out_o(11 downto 0) <= window_lower_thr_r;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0007" =>
+ slv_data_out_o(11 downto 0) <= window_upper_thr_r;
+ slv_data_out_o(31 downto 12) <= (others => '0');
+ slv_ack_o <= '1';
+
+ when x"0008" =>
slv_data_out_o <=
std_logic_vector(channel_done(31 downto 0));
slv_ack_o <= '1';
- when x"0006" =>
+
+ when x"0009" =>
slv_data_out_o <=
std_logic_vector(channel_done(63 downto 32));
slv_ack_o <= '1';
- when x"0007" =>
+
+ when x"000a" =>
slv_data_out_o <=
std_logic_vector(channel_done(95 downto 64));
slv_ack_o <= '1';
- when x"0008" =>
+
+ when x"000b" =>
slv_data_out_o <=
std_logic_vector(channel_done(127 downto 96));
slv_ack_o <= '1';
-- Output Signals
-----------------------------------------------------------------------------
- PROCESS_BUSY_OUT <= process_busy_o;
+ TRIGGER_BUSY_OUT <= trigger_busy_o;
DATA_OUT <= data_o or t_data_o;
DATA_CLK_OUT <= data_clk_o or t_data_clk_o;
- DATA_FIFO_RESET_OUT <= data_fifo_reset_o;
+ NOMORE_DATA_OUT <= nomore_data_o;
-- Slave
SLV_DATA_OUT <= slv_data_out_o;
SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
SLV_ACK_OUT <= slv_ack_o;
-
--------------------------------------------------------------------------------
--- Channel Sttaus Handler
--------------------------------------------------------------------------------
- PROC_CHANNEL_STATUS_CMD: process(ch_status_cmd_tr,
- ch_status_cmd_pr)
- begin
- if (ch_status_cmd_tr /= CS_NONE) then
- channel_status_cmd <= ch_status_cmd_tr;
- elsif (ch_status_cmd_pr /= CS_NONE) then
- channel_status_cmd <= ch_status_cmd_pr;
- else
- channel_status_cmd <= CS_NONE;
- end if;
- end process PROC_CHANNEL_STATUS_CMD;
-
- PROC_CHANNEL_STATUS: process(CLK_IN)
- constant all_one : unsigned(127 downto 0) := (others => '1');
-
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1') then
- channel_wait <= (others => '0');
- channel_done <= (others => '0');
- channel_all_done <= '0';
-
- else
- -- Check done status
- if (channel_done = all_one) then
- channel_all_done <= '1';
- end if;
-
- -- Process Command
- case channel_status_cmd is
-
- when CS_RESET =>
- channel_wait <= (others => '0');
- channel_done <= (others => '0');
- channel_all_done <= '0';
-
- when CS_TOKEN_UPDATE =>
- channel_done <= channel_done or (not channel_wait);
- channel_wait <= (others => '0');
-
- when CS_SET_WAIT =>
- case channel_index is
-
- when "0000000" => channel_wait(0) <= '1';
- when "0000001" => channel_wait(1) <= '1';
- when "0000010" => channel_wait(2) <= '1';
- when "0000011" => channel_wait(3) <= '1';
- when "0000100" => channel_wait(4) <= '1';
- when "0000101" => channel_wait(5) <= '1';
- when "0000110" => channel_wait(6) <= '1';
- when "0000111" => channel_wait(7) <= '1';
- when "0001000" => channel_wait(8) <= '1';
- when "0001001" => channel_wait(9) <= '1';
- when "0001010" => channel_wait(10) <= '1';
- when "0001011" => channel_wait(11) <= '1';
- when "0001100" => channel_wait(12) <= '1';
- when "0001101" => channel_wait(13) <= '1';
- when "0001110" => channel_wait(14) <= '1';
- when "0001111" => channel_wait(15) <= '1';
- when "0010000" => channel_wait(16) <= '1';
- when "0010001" => channel_wait(17) <= '1';
- when "0010010" => channel_wait(18) <= '1';
- when "0010011" => channel_wait(19) <= '1';
- when "0010100" => channel_wait(20) <= '1';
- when "0010101" => channel_wait(21) <= '1';
- when "0010110" => channel_wait(22) <= '1';
- when "0010111" => channel_wait(23) <= '1';
- when "0011000" => channel_wait(24) <= '1';
- when "0011001" => channel_wait(25) <= '1';
- when "0011010" => channel_wait(26) <= '1';
- when "0011011" => channel_wait(27) <= '1';
- when "0011100" => channel_wait(28) <= '1';
- when "0011101" => channel_wait(29) <= '1';
- when "0011110" => channel_wait(30) <= '1';
- when "0011111" => channel_wait(31) <= '1';
- when "0100000" => channel_wait(32) <= '1';
- when "0100001" => channel_wait(33) <= '1';
- when "0100010" => channel_wait(34) <= '1';
- when "0100011" => channel_wait(35) <= '1';
- when "0100100" => channel_wait(36) <= '1';
- when "0100101" => channel_wait(37) <= '1';
- when "0100110" => channel_wait(38) <= '1';
- when "0100111" => channel_wait(39) <= '1';
- when "0101000" => channel_wait(40) <= '1';
- when "0101001" => channel_wait(41) <= '1';
- when "0101010" => channel_wait(42) <= '1';
- when "0101011" => channel_wait(43) <= '1';
- when "0101100" => channel_wait(44) <= '1';
- when "0101101" => channel_wait(45) <= '1';
- when "0101110" => channel_wait(46) <= '1';
- when "0101111" => channel_wait(47) <= '1';
- when "0110000" => channel_wait(48) <= '1';
- when "0110001" => channel_wait(49) <= '1';
- when "0110010" => channel_wait(50) <= '1';
- when "0110011" => channel_wait(51) <= '1';
- when "0110100" => channel_wait(52) <= '1';
- when "0110101" => channel_wait(53) <= '1';
- when "0110110" => channel_wait(54) <= '1';
- when "0110111" => channel_wait(55) <= '1';
- when "0111000" => channel_wait(56) <= '1';
- when "0111001" => channel_wait(57) <= '1';
- when "0111010" => channel_wait(58) <= '1';
- when "0111011" => channel_wait(59) <= '1';
- when "0111100" => channel_wait(60) <= '1';
- when "0111101" => channel_wait(61) <= '1';
- when "0111110" => channel_wait(62) <= '1';
- when "0111111" => channel_wait(63) <= '1';
- when "1000000" => channel_wait(64) <= '1';
- when "1000001" => channel_wait(65) <= '1';
- when "1000010" => channel_wait(66) <= '1';
- when "1000011" => channel_wait(67) <= '1';
- when "1000100" => channel_wait(68) <= '1';
- when "1000101" => channel_wait(69) <= '1';
- when "1000110" => channel_wait(70) <= '1';
- when "1000111" => channel_wait(71) <= '1';
- when "1001000" => channel_wait(72) <= '1';
- when "1001001" => channel_wait(73) <= '1';
- when "1001010" => channel_wait(74) <= '1';
- when "1001011" => channel_wait(75) <= '1';
- when "1001100" => channel_wait(76) <= '1';
- when "1001101" => channel_wait(77) <= '1';
- when "1001110" => channel_wait(78) <= '1';
- when "1001111" => channel_wait(79) <= '1';
- when "1010000" => channel_wait(80) <= '1';
- when "1010001" => channel_wait(81) <= '1';
- when "1010010" => channel_wait(82) <= '1';
- when "1010011" => channel_wait(83) <= '1';
- when "1010100" => channel_wait(84) <= '1';
- when "1010101" => channel_wait(85) <= '1';
- when "1010110" => channel_wait(86) <= '1';
- when "1010111" => channel_wait(87) <= '1';
- when "1011000" => channel_wait(88) <= '1';
- when "1011001" => channel_wait(89) <= '1';
- when "1011010" => channel_wait(90) <= '1';
- when "1011011" => channel_wait(91) <= '1';
- when "1011100" => channel_wait(92) <= '1';
- when "1011101" => channel_wait(93) <= '1';
- when "1011110" => channel_wait(94) <= '1';
- when "1011111" => channel_wait(95) <= '1';
- when "1100000" => channel_wait(96) <= '1';
- when "1100001" => channel_wait(97) <= '1';
- when "1100010" => channel_wait(98) <= '1';
- when "1100011" => channel_wait(99) <= '1';
- when "1100100" => channel_wait(100) <= '1';
- when "1100101" => channel_wait(101) <= '1';
- when "1100110" => channel_wait(102) <= '1';
- when "1100111" => channel_wait(103) <= '1';
- when "1101000" => channel_wait(104) <= '1';
- when "1101001" => channel_wait(105) <= '1';
- when "1101010" => channel_wait(106) <= '1';
- when "1101011" => channel_wait(107) <= '1';
- when "1101100" => channel_wait(108) <= '1';
- when "1101101" => channel_wait(109) <= '1';
- when "1101110" => channel_wait(110) <= '1';
- when "1101111" => channel_wait(111) <= '1';
- when "1110000" => channel_wait(112) <= '1';
- when "1110001" => channel_wait(113) <= '1';
- when "1110010" => channel_wait(114) <= '1';
- when "1110011" => channel_wait(115) <= '1';
- when "1110100" => channel_wait(116) <= '1';
- when "1110101" => channel_wait(117) <= '1';
- when "1110110" => channel_wait(118) <= '1';
- when "1110111" => channel_wait(119) <= '1';
- when "1111000" => channel_wait(120) <= '1';
- when "1111001" => channel_wait(121) <= '1';
- when "1111010" => channel_wait(122) <= '1';
- when "1111011" => channel_wait(123) <= '1';
- when "1111100" => channel_wait(124) <= '1';
- when "1111101" => channel_wait(125) <= '1';
- when "1111110" => channel_wait(126) <= '1';
- when "1111111" => channel_wait(127) <= '1';
-
- end case;
-
- when CS_SET_DONE =>
- case channel_index is
-
- when "0000000" => channel_done(0) <= '1';
- when "0000001" => channel_done(1) <= '1';
- when "0000010" => channel_done(2) <= '1';
- when "0000011" => channel_done(3) <= '1';
- when "0000100" => channel_done(4) <= '1';
- when "0000101" => channel_done(5) <= '1';
- when "0000110" => channel_done(6) <= '1';
- when "0000111" => channel_done(7) <= '1';
- when "0001000" => channel_done(8) <= '1';
- when "0001001" => channel_done(9) <= '1';
- when "0001010" => channel_done(10) <= '1';
- when "0001011" => channel_done(11) <= '1';
- when "0001100" => channel_done(12) <= '1';
- when "0001101" => channel_done(13) <= '1';
- when "0001110" => channel_done(14) <= '1';
- when "0001111" => channel_done(15) <= '1';
- when "0010000" => channel_done(16) <= '1';
- when "0010001" => channel_done(17) <= '1';
- when "0010010" => channel_done(18) <= '1';
- when "0010011" => channel_done(19) <= '1';
- when "0010100" => channel_done(20) <= '1';
- when "0010101" => channel_done(21) <= '1';
- when "0010110" => channel_done(22) <= '1';
- when "0010111" => channel_done(23) <= '1';
- when "0011000" => channel_done(24) <= '1';
- when "0011001" => channel_done(25) <= '1';
- when "0011010" => channel_done(26) <= '1';
- when "0011011" => channel_done(27) <= '1';
- when "0011100" => channel_done(28) <= '1';
- when "0011101" => channel_done(29) <= '1';
- when "0011110" => channel_done(30) <= '1';
- when "0011111" => channel_done(31) <= '1';
- when "0100000" => channel_done(32) <= '1';
- when "0100001" => channel_done(33) <= '1';
- when "0100010" => channel_done(34) <= '1';
- when "0100011" => channel_done(35) <= '1';
- when "0100100" => channel_done(36) <= '1';
- when "0100101" => channel_done(37) <= '1';
- when "0100110" => channel_done(38) <= '1';
- when "0100111" => channel_done(39) <= '1';
- when "0101000" => channel_done(40) <= '1';
- when "0101001" => channel_done(41) <= '1';
- when "0101010" => channel_done(42) <= '1';
- when "0101011" => channel_done(43) <= '1';
- when "0101100" => channel_done(44) <= '1';
- when "0101101" => channel_done(45) <= '1';
- when "0101110" => channel_done(46) <= '1';
- when "0101111" => channel_done(47) <= '1';
- when "0110000" => channel_done(48) <= '1';
- when "0110001" => channel_done(49) <= '1';
- when "0110010" => channel_done(50) <= '1';
- when "0110011" => channel_done(51) <= '1';
- when "0110100" => channel_done(52) <= '1';
- when "0110101" => channel_done(53) <= '1';
- when "0110110" => channel_done(54) <= '1';
- when "0110111" => channel_done(55) <= '1';
- when "0111000" => channel_done(56) <= '1';
- when "0111001" => channel_done(57) <= '1';
- when "0111010" => channel_done(58) <= '1';
- when "0111011" => channel_done(59) <= '1';
- when "0111100" => channel_done(60) <= '1';
- when "0111101" => channel_done(61) <= '1';
- when "0111110" => channel_done(62) <= '1';
- when "0111111" => channel_done(63) <= '1';
- when "1000000" => channel_done(64) <= '1';
- when "1000001" => channel_done(65) <= '1';
- when "1000010" => channel_done(66) <= '1';
- when "1000011" => channel_done(67) <= '1';
- when "1000100" => channel_done(68) <= '1';
- when "1000101" => channel_done(69) <= '1';
- when "1000110" => channel_done(70) <= '1';
- when "1000111" => channel_done(71) <= '1';
- when "1001000" => channel_done(72) <= '1';
- when "1001001" => channel_done(73) <= '1';
- when "1001010" => channel_done(74) <= '1';
- when "1001011" => channel_done(75) <= '1';
- when "1001100" => channel_done(76) <= '1';
- when "1001101" => channel_done(77) <= '1';
- when "1001110" => channel_done(78) <= '1';
- when "1001111" => channel_done(79) <= '1';
- when "1010000" => channel_done(80) <= '1';
- when "1010001" => channel_done(81) <= '1';
- when "1010010" => channel_done(82) <= '1';
- when "1010011" => channel_done(83) <= '1';
- when "1010100" => channel_done(84) <= '1';
- when "1010101" => channel_done(85) <= '1';
- when "1010110" => channel_done(86) <= '1';
- when "1010111" => channel_done(87) <= '1';
- when "1011000" => channel_done(88) <= '1';
- when "1011001" => channel_done(89) <= '1';
- when "1011010" => channel_done(90) <= '1';
- when "1011011" => channel_done(91) <= '1';
- when "1011100" => channel_done(92) <= '1';
- when "1011101" => channel_done(93) <= '1';
- when "1011110" => channel_done(94) <= '1';
- when "1011111" => channel_done(95) <= '1';
- when "1100000" => channel_done(96) <= '1';
- when "1100001" => channel_done(97) <= '1';
- when "1100010" => channel_done(98) <= '1';
- when "1100011" => channel_done(99) <= '1';
- when "1100100" => channel_done(100) <= '1';
- when "1100101" => channel_done(101) <= '1';
- when "1100110" => channel_done(102) <= '1';
- when "1100111" => channel_done(103) <= '1';
- when "1101000" => channel_done(104) <= '1';
- when "1101001" => channel_done(105) <= '1';
- when "1101010" => channel_done(106) <= '1';
- when "1101011" => channel_done(107) <= '1';
- when "1101100" => channel_done(108) <= '1';
- when "1101101" => channel_done(109) <= '1';
- when "1101110" => channel_done(110) <= '1';
- when "1101111" => channel_done(111) <= '1';
- when "1110000" => channel_done(112) <= '1';
- when "1110001" => channel_done(113) <= '1';
- when "1110010" => channel_done(114) <= '1';
- when "1110011" => channel_done(115) <= '1';
- when "1110100" => channel_done(116) <= '1';
- when "1110101" => channel_done(117) <= '1';
- when "1110110" => channel_done(118) <= '1';
- when "1110111" => channel_done(119) <= '1';
- when "1111000" => channel_done(120) <= '1';
- when "1111001" => channel_done(121) <= '1';
- when "1111010" => channel_done(122) <= '1';
- when "1111011" => channel_done(123) <= '1';
- when "1111100" => channel_done(124) <= '1';
- when "1111101" => channel_done(125) <= '1';
- when "1111110" => channel_done(126) <= '1';
- when "1111111" => channel_done(127) <= '1';
- end case;
-
- when others => null;
-
- end case;
- end if;
- end if;
- end process PROC_CHANNEL_STATUS;
-
-
end Behavioral;
-- TRBNet interfaces
-------------------------------------------------------------------------------
-component nXyter_FEE_board
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- CLK_ADC_IN : in std_logic;
-
- I2C_SDA_INOUT : inout std_logic;
- I2C_SCL_INOUT : inout std_logic;
- I2C_SM_RESET_OUT : out std_logic;
- I2C_REG_RESET_OUT : out std_logic;
-
- SPI_SCLK_OUT : out std_logic;
- SPI_SDIO_INOUT : inout std_logic;
- SPI_CSB_OUT : out std_logic;
-
- NX_CLK128_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX_RESET_OUT : out std_logic;
- NX_TESTPULSE_OUT : out std_logic;
-
- ADC_FCLK_IN : in std_logic_vector(1 downto 0);
- ADC_DCLK_IN : in std_logic_vector(1 downto 0);
- ADC_SAMPLE_CLK_OUT : out std_logic;
- ADC_A_IN : in std_logic_vector(1 downto 0);
- ADC_B_IN : in std_logic_vector(1 downto 0);
- ADC_NX_IN : in std_logic_vector(1 downto 0);
- ADC_D_IN : in std_logic_vector(1 downto 0);
-
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
- REGIO_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_READ_ENABLE_IN : in std_logic;
- REGIO_WRITE_ENABLE_IN : in std_logic;
- REGIO_TIMEOUT_IN : in std_logic;
- REGIO_DATAREADY_OUT : out std_logic;
- REGIO_WRITE_ACK_OUT : out std_logic;
- REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic;
-
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
--------------------------------------------------------------------------------
--- TrbNet Data Interface
--------------------------------------------------------------------------------
-
-component nXyter_data_handler
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
- REGIO_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_READ_ENABLE_IN : in std_logic;
- REGIO_WRITE_ENABLE_IN : in std_logic;
- REGIO_TIMEOUT_IN : in std_logic;
- REGIO_DATAREADY_OUT : out std_logic;
- REGIO_WRITE_ACK_OUT : out std_logic;
- REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic;
- LVL1_TRG_DATA_VALID_IN : in std_logic;
- LVL1_VALID_TIMING_TRG_IN : in std_logic;
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
- LVL1_INVALID_TRG_IN : in std_logic;
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- FEE_TRG_RELEASE_OUT : out std_logic;
- FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_OUT : out std_logic;
- FEE_DATA_FINISHED_OUT : out std_logic;
- FEE_DATA_ALMOST_FULL_IN : in std_logic;
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
+ component nXyter_FEE_board
+ generic (
+ BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ CLK_NX_IN : in std_logic;
+ CLK_ADC_IN : in std_logic;
+
+ I2C_SDA_INOUT : inout std_logic;
+ I2C_SCL_INOUT : inout std_logic;
+ I2C_SM_RESET_OUT : out std_logic;
+ I2C_REG_RESET_OUT : out std_logic;
+
+ SPI_SCLK_OUT : out std_logic;
+ SPI_SDIO_INOUT : inout std_logic;
+ SPI_CSB_OUT : out std_logic;
+
+ NX_CLK128_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_RESET_OUT : out std_logic;
+ NX_TESTPULSE_OUT : out std_logic;
+
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SAMPLE_CLK_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
+
+ LVL1_TRG_DATA_VALID_IN : in std_logic;
+ LVL1_VALID_TIMING_TRG_IN : in std_logic;
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
+ LVL1_INVALID_TRG_IN : in std_logic;
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+
+ FEE_TRG_RELEASE_OUT : out std_logic;
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_DATA_ALMOST_FULL_IN : in std_logic;
+
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_TIMEOUT_IN : in std_logic;
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
+ );
+ end component;
-------------------------------------------------------------------------------
-- nXyter I2C Interface
RESET_IN : in std_logic;
SDA_INOUT : inout std_logic;
SCL_INOUT : inout std_logic;
+ INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);
+ COMMAND_BUSY_OUT : out std_logic;
+ I2C_DATA_OUT : out std_logic_vector(31 downto 0);
+ I2C_LOCK_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
SCLK_OUT : out std_logic;
SDIO_INOUT : inout std_logic;
CSB_OUT : out std_logic;
+ INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0);
+ COMMAND_BUSY_OUT : out std_logic;
+ SPI_DATA_OUT : out std_logic_vector(31 downto 0);
+ SPI_LOCK_IN : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
-- TRBNet Registers
-------------------------------------------------------------------------------
+component nx_setup
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ I2C_COMMAND_OUT : out std_logic_vector(31 downto 0);
+ I2C_COMMAND_BUSY_IN : in std_logic;
+ I2C_DATA_IN : in std_logic_vector(31 downto 0);
+ I2C_LOCK_OUT : out std_logic;
+ SPI_COMMAND_OUT : out std_logic_vector(31 downto 0);
+ SPI_COMMAND_BUSY_IN : in std_logic;
+ SPI_DATA_IN : in std_logic_vector(31 downto 0);
+ SPI_LOCK_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
component nxyter_registers
port (
CLK_IN : in std_logic;
I2C_SM_RESET_OUT : out std_logic;
I2C_REG_RESET_OUT : out std_logic;
NX_TS_RESET_OUT : out std_logic;
+ OFFLINE_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector(15 downto 0)
);
end component;
component fifo_32_data
port (
- Data : in std_logic_vector(31 downto 0);
- Clock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic
+ Data : in std_logic_vector(31 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ WCNT : out std_logic_vector(10 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic
);
end component;
RESET_IN : in std_logic;
NX_TIMESTAMP_CLK_IN : in std_logic;
NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- ADC_CLK_DAT_SRC_IN : in std_logic;
+ ADC_CLK_DAT_IN : in std_logic;
ADC_FCLK_IN : in std_logic_vector(1 downto 0);
ADC_DCLK_IN : in std_logic_vector(1 downto 0);
ADC_SAMPLE_CLK_OUT : out std_logic;
ADC_DATA_IN : in std_logic_vector(11 downto 0);
NX_TOKEN_RETURN_IN : in std_logic;
NX_NOMORE_DATA_IN : in std_logic;
- TIMESTAMP_REF_IN : in unsigned(11 downto 0);
TRIGGER_IN : in std_logic;
- PROCESS_BUSY_OUT : out std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ TIMESTAMP_REF_IN : in unsigned(11 downto 0);
DATA_OUT : out std_logic_vector(31 downto 0);
DATA_CLK_OUT : out std_logic;
- DATA_FIFO_RESET_OUT : out std_logic;
+ NOMORE_DATA_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
);
end component;
+component nx_event_buffer
+ generic (
+ BOARD_ID : std_logic_vector(15 downto 0));
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ RESET_DATA_BUFFER_IN : in std_logic;
+ NXYTER_OFFLINE_IN : in std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ DATA_CLK_IN : in std_logic;
+ EVT_NOMORE_DATA_IN : in std_logic;
+ LVL2_TRIGGER_IN : in std_logic;
+ FAST_CLEAR_IN : in std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_DATA_ALMOST_FULL_IN : in std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+-------------------------------------------------------------------------------
+
component level_to_pulse
port (
CLK_IN : in std_logic;
);
end component;
-
-component nx_data_buffer
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- DATA_IN : in std_logic_vector(31 downto 0);
- DATA_CLK_IN : in std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
component pll_125_hub
port (
CLK : in std_logic;
);
end component;
+component nx_trigger_handler
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ NXYTER_OFFLINE_IN : in std_logic;
+ LVL1_TRG_DATA_VALID_IN : in std_logic;
+ LVL1_VALID_TIMING_TRG_IN : in std_logic;
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
+ LVL1_INVALID_TRG_IN : in std_logic;
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ FEE_TRG_RELEASE_OUT : out std_logic;
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+ INTERNAL_TRIGGER_IN : in std_logic;
+ TRIGGER_VALIDATE_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_BUSY_IN : in std_logic;
+ VALIDATE_TRIGGER_OUT : out std_logic;
+ TIMESTAMP_HOLD_OUT : out std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ EVENT_BUFFER_CLEAR_OUT : out std_logic;
+ FAST_CLEAR_OUT : out std_logic;
+ TRIGGER_BUSY_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
component nx_trigger_generator
port (
CLK_IN : in std_logic;
);
end component;
-component nx_trigger_handler
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- TRIGGER_IN : in std_logic;
- TRIGGER_RELEASE_IN : in std_logic;
- TRIGGER_OUT : out std_logic;
- TIMESTAMP_HOLD_OUT : out std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
- SLV_READ_IN : in std_logic;
- SLV_WRITE_IN : in std_logic;
- SLV_DATA_OUT : out std_logic_vector(31 downto 0);
- SLV_DATA_IN : in std_logic_vector(31 downto 0);
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);
- SLV_ACK_OUT : out std_logic;
- SLV_NO_MORE_DATA_OUT : out std_logic;
- SLV_UNKNOWN_ADDR_OUT : out std_logic;
- DEBUG_OUT : out std_logic_vector(15 downto 0));
-end component;
-
-------------------------------------------------------------------------------
-- ADC Handler
-------------------------------------------------------------------------------
);
end component;
-component adc_receiver
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- RESTART_IN : in std_logic;
- SAMPLE_CLK_IN : in std_logic;
- DATA_CLK_SRC_IN : in std_logic;
-
- ADC_FCLK_IN : in std_logic_vector(1 downto 0);
- ADC_DCLK_IN : in std_logic_vector(1 downto 0);
- ADC_SC_CLK32_OUT : out std_logic;
- ADC_A_IN : in std_logic_vector(1 downto 0);
- ADC_B_IN : in std_logic_vector(1 downto 0);
- ADC_NX_IN : in std_logic_vector(1 downto 0);
- ADC_D_IN : in std_logic_vector(1 downto 0);
-
- DATA_OUT : out std_logic_vector(11 downto 0);
- DATA_VALID_OUT : out std_logic;
-
- DEBUG_OUT : out std_logic_vector(15 downto 0)
- );
-end component;
-
-------------------------------------------------------------------------------
-- Misc Tools
-------------------------------------------------------------------------------
+++ /dev/null
-----------------------------------------------------------------------------
---
--- two nXyter FEB Data handler
---
------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.nxyter_components.all;
-
-entity nXyter_data_handler is
-
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
-
- -- TRBNet RegIO Port for the slave bus
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
- REGIO_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_READ_ENABLE_IN : in std_logic;
- REGIO_WRITE_ENABLE_IN : in std_logic;
- REGIO_TIMEOUT_IN : in std_logic;
- REGIO_DATAREADY_OUT : out std_logic;
- REGIO_WRITE_ACK_OUT : out std_logic;
- REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic;
-
- -- TrbNet Timing trigger
- LVL1_TRG_DATA_VALID_IN : in std_logic;
- LVL1_VALID_TIMING_TRG_IN : in std_logic;
- LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
- LVL1_INVALID_TRG_IN : in std_logic;
-
- LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
- LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
-
- -- Response from FEE
- FEE_TRG_RELEASE_OUT : out std_logic;
- FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_OUT : out std_logic;
- FEE_DATA_FINISHED_OUT : out std_logic;
- FEE_DATA_ALMOST_FULL_IN : in std_logic;
-
- -- Debug Signals
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
- );
-
-end nXyter_data_handler;
-
-
-architecture Behavioral of nXyter_data_handler is
-
--------------------------------------------------------------------------------
--- Signals
--------------------------------------------------------------------------------
-
- -- LV2 Data Out Handler
- signal fee_trg_release_o : std_logic;
- signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal fee_data_o : std_logic_vector(31 downto 0);
- signal fee_data_write_o : std_logic;
- signal fee_data_finished_o : std_logic;
-
- type STATES is (S_IDLE,
- S_SEND_DATA,
- S_END
- );
- signal STATE : STATES;
-
-begin
-
--------------------------------------------------------------------------------
--- DEBUG
--------------------------------------------------------------------------------
- DEBUG_LINE_OUT(0) <= CLK_IN;
- DEBUG_LINE_OUT(1) <= LVL1_TRG_DATA_VALID_IN;
- DEBUG_LINE_OUT(2) <= LVL1_VALID_TIMING_TRG_IN;
- DEBUG_LINE_OUT(3) <= LVL1_VALID_NOTIMING_TRG_IN;
- DEBUG_LINE_OUT(4) <= LVL1_INVALID_TRG_IN;
- DEBUG_LINE_OUT(5) <= FEE_TRG_RELEASE_OUT;
- DEBUG_LINE_OUT(6) <= FEE_DATA_WRITE_OUT;
- DEBUG_LINE_OUT(7) <= FEE_DATA_FINISHED_OUT;
- DEBUG_LINE_OUT(8) <= FEE_DATA_ALMOST_FULL_IN;
- DEBUG_LINE_OUT(15 downto 9) <= LVL1_TRG_NUMBER_IN(6 downto 0);
-
- PROC_DATA_HANDLER: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- fee_trg_release_o <= '0';
- fee_data_o <= (others => '0');
- fee_data_write_o <= '0';
- fee_data_finished_o <= '0';
- STATE <= S_IDLE;
- else
- fee_trg_release_o <= '0';
- fee_data_o <= (others => '0');
- fee_data_write_o <= '0';
- fee_data_finished_o <= '0';
-
- case STATE is
- when S_IDLE =>
- if (LVL1_TRG_DATA_VALID_IN = '1') then
- STATE <= S_SEND_DATA;
- end if;
-
- when S_SEND_DATA =>
- fee_data_o <= x"deadbeef";
- fee_data_write_o <= '1';
- STATE <= S_END;
-
- when S_END =>
- fee_trg_release_o <= '1';
- fee_data_finished_o <= '1';
- STATE <= S_IDLE;
-
- end case;
- end if;
- end if;
-
- end process PROC_DATA_HANDLER;
-
-
--------------------------------------------------------------------------------
--- OUTPUT
--------------------------------------------------------------------------------
- FEE_TRG_RELEASE_OUT <= fee_trg_release_o;
- FEE_TRG_STATUSBITS_OUT <= fee_trg_statusbits_o;
- FEE_DATA_OUT <= fee_data_o;
- FEE_DATA_WRITE_OUT <= fee_data_write_o;
- FEE_DATA_FINISHED_OUT <= fee_data_finished_o;
-
-
-end Behavioral;
-----------------------------------------------------------------------------
+---------------------------------------------------------------------------
--
-- One nXyter FEB
--
use work.nxyter_components.all;
entity nXyter_FEE_board is
-
+ generic (
+ BOARD_ID : std_logic_vector(15 downto 0) := x"ffff"
+ );
port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- CLK_ADC_IN : in std_logic;
-
- -- I2C Ports
- I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
- I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
- I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine
- I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers
-
- -- ADC SPI
- SPI_SCLK_OUT : out std_logic;
- SPI_SDIO_INOUT : inout std_logic;
- SPI_CSB_OUT : out std_logic;
-
- -- nXyter Timestamp Ports
- NX_CLK128_IN : in std_logic;
- NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
- NX_RESET_OUT : out std_logic;
- NX_TESTPULSE_OUT : out std_logic;
-
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ CLK_NX_IN : in std_logic;
+ CLK_ADC_IN : in std_logic;
+
+ -- I2C Ports
+ I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line
+ I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line
+ I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine
+ I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers
+
+ -- ADC SPI
+ SPI_SCLK_OUT : out std_logic;
+ SPI_SDIO_INOUT : inout std_logic;
+ SPI_CSB_OUT : out std_logic;
+
+ -- nXyter Timestamp Ports
+ NX_CLK128_IN : in std_logic;
+ NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
+ NX_RESET_OUT : out std_logic;
+ NX_TESTPULSE_OUT : out std_logic;
+
-- ADC nXyter Pulse Hight Ports
- ADC_FCLK_IN : in std_logic_vector(1 downto 0);
- ADC_DCLK_IN : in std_logic_vector(1 downto 0);
- ADC_SAMPLE_CLK_OUT : out std_logic;
- ADC_A_IN : in std_logic_vector(1 downto 0);
- ADC_B_IN : in std_logic_vector(1 downto 0);
- ADC_NX_IN : in std_logic_vector(1 downto 0);
- ADC_D_IN : in std_logic_vector(1 downto 0);
-
- -- TRBNet RegIO Port for the slave bus
- REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
- REGIO_DATA_IN : in std_logic_vector(31 downto 0);
- REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
- REGIO_READ_ENABLE_IN : in std_logic;
- REGIO_WRITE_ENABLE_IN : in std_logic;
- REGIO_TIMEOUT_IN : in std_logic;
- REGIO_DATAREADY_OUT : out std_logic;
- REGIO_WRITE_ACK_OUT : out std_logic;
- REGIO_NO_MORE_DATA_OUT : out std_logic;
- REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ ADC_FCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_DCLK_IN : in std_logic_vector(1 downto 0);
+ ADC_SAMPLE_CLK_OUT : out std_logic;
+ ADC_A_IN : in std_logic_vector(1 downto 0);
+ ADC_B_IN : in std_logic_vector(1 downto 0);
+ ADC_NX_IN : in std_logic_vector(1 downto 0);
+ ADC_D_IN : in std_logic_vector(1 downto 0);
+
+ -- Event Buffer
+ --LVL1 trigger to FEE
+ LVL1_TRG_DATA_VALID_IN : in std_logic;
+ LVL1_VALID_TIMING_TRG_IN : in std_logic;
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- Status + Info TypE
+ LVL1_INVALID_TRG_IN : in std_logic;
+
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+
+ --Response from FEE
+ FEE_TRG_RELEASE_OUT : out std_logic;
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_DATA_ALMOST_FULL_IN : in std_logic;
+ -- TRBNet RegIO Port for the slave bus
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_TIMEOUT_IN : in std_logic;
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+
-- Debug Signals
- DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
+ DEBUG_LINE_OUT : out std_logic_vector(15 downto 0)
);
-end nXyter_FEE_board;
+end entity;
architecture Behavioral of nXyter_FEE_board is
-- Signals
-------------------------------------------------------------------------------
-- Clock 256
- signal clk_250_o : std_logic;
-
- -- Bus Handler
- signal slv_read : std_logic_vector(10-1 downto 0);
- signal slv_write : std_logic_vector(10-1 downto 0);
- signal slv_no_more_data : std_logic_vector(10-1 downto 0);
- signal slv_ack : std_logic_vector(10-1 downto 0);
- signal slv_addr : std_logic_vector(10*16-1 downto 0);
- signal slv_data_rd : std_logic_vector(10*32-1 downto 0);
- signal slv_data_wr : std_logic_vector(10*32-1 downto 0);
- signal slv_unknown_addr : std_logic_vector(10-1 downto 0);
-
- -- TRB Register
- signal i2c_sm_reset_o : std_logic;
- signal nx_ts_reset_1 : std_logic;
- signal nx_ts_reset_2 : std_logic;
- signal nx_ts_reset_o : std_logic;
- signal i2c_reg_reset_o : std_logic;
+ signal clk_250_o : std_logic;
+
+ -- Bus Handler
+ signal slv_read : std_logic_vector(16-1 downto 0);
+ signal slv_write : std_logic_vector(16-1 downto 0);
+ signal slv_no_more_data : std_logic_vector(16-1 downto 0);
+ signal slv_ack : std_logic_vector(16-1 downto 0);
+ signal slv_addr : std_logic_vector(16*16-1 downto 0);
+ signal slv_data_rd : std_logic_vector(16*32-1 downto 0);
+ signal slv_data_wr : std_logic_vector(16*32-1 downto 0);
+ signal slv_unknown_addr : std_logic_vector(16-1 downto 0);
+
+ -- TRB Register
+ signal i2c_sm_reset_o : std_logic;
+ signal nx_ts_reset_1 : std_logic;
+ signal nx_ts_reset_2 : std_logic;
+ signal nx_ts_reset_o : std_logic;
+ signal i2c_reg_reset_o : std_logic;
+
+ -- NX Register Access
+ signal i2c_lock : std_logic;
+ signal i2c_command : std_logic_vector(31 downto 0);
+ signal i2c_command_busy : std_logic;
+ signal i2c_data : std_logic_vector(31 downto 0);
+ signal spi_lock : std_logic;
+ signal spi_command : std_logic_vector(31 downto 0);
+ signal spi_command_busy : std_logic;
+ signal spi_data : std_logic_vector(31 downto 0);
+
+ -- SPI Interface ADC
+ signal spi_sdi : std_logic;
+ signal spi_sdo : std_logic;
+
+ -- Data Receiver
+ signal adc_data_valid : std_logic;
+ signal adc_new_data : std_logic;
+
+ signal new_timestamp : std_logic_vector(31 downto 0);
+ signal new_adc_data : std_logic_vector(11 downto 0);
+ signal new_data : std_logic;
+
+ -- Data Validate
+ signal timestamp : std_logic_vector(13 downto 0);
+ signal timestamp_channel_id : std_logic_vector(6 downto 0);
+ signal timestamp_status : std_logic_vector(2 downto 0);
+ signal adc_data : std_logic_vector(11 downto 0);
+ signal data_valid : std_logic;
+
+ signal nx_token_return : std_logic;
+ signal nx_nomore_data : std_logic;
+
+ -- Trigger Validate
+ signal trigger_data : std_logic_vector(31 downto 0);
+ signal trigger_data_clk : std_logic;
+ signal event_buffer_clear : std_logic;
+ signal trigger_validate_busy : std_logic;
+ signal validate_nomore_data : std_logic;
- -- SPI Interface ADC
- signal spi_sdi : std_logic;
- signal spi_sdo : std_logic;
-
- -- Data Receiver
- signal adc_data_valid : std_logic;
- signal adc_new_data : std_logic;
-
- signal new_timestamp : std_logic_vector(31 downto 0);
- signal new_adc_data : std_logic_vector(11 downto 0);
- signal new_data : std_logic;
-
- -- Data Validate
- signal timestamp : std_logic_vector(13 downto 0);
- signal timestamp_channel_id : std_logic_vector(6 downto 0);
- signal timestamp_status : std_logic_vector(2 downto 0);
- signal adc_data : std_logic_vector(11 downto 0);
- signal data_valid : std_logic;
-
- signal nx_token_return : std_logic;
- signal nx_nomore_data : std_logic;
-
- -- Timestamp Process
- signal ts_data : std_logic_vector(31 downto 0);
- signal ts_data_clk : std_logic;
- signal data_fifo_reset : std_logic;
+ -- Event Buffer
+ signal trigger_evt_busy : std_logic;
+ signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
+ signal fee_data_o : std_logic_vector(31 downto 0);
+ signal fee_data_write_o : std_logic;
+ signal fee_data_finished_o : std_logic;
+ signal fee_almost_full_i : std_logic;
- -- FPGA Timestamp
- signal timestamp_trigger : unsigned(11 downto 0);
- signal nx_timestamp_sync : std_logic;
-
- -- Data Buffer
- signal data_buffer_reset : std_logic;
-
-- Trigger Handler
- signal trigger_release : std_logic;
- signal trigger_ack : std_logic;
- signal timestamp_hold : std_logic;
- signal trigger_busy : std_logic;
+ signal trigger : std_logic;
+ signal timestamp_hold : std_logic;
+ signal lvl2_trigger : std_logic;
+ signal trigger_busy : std_logic;
+ signal fast_clear : std_logic;
+ signal nxyter_offline : std_logic;
+ signal fee_trg_release_o : std_logic;
+
+ -- FPGA Timestamp
+ signal timestamp_trigger : unsigned(11 downto 0);
+ signal nx_timestamp_sync : std_logic;
-- Trigger Generator
- signal trigger : std_logic;
- signal nx_testpulse_o : std_logic;
-
-
- -- ADC FIFO Entity
--- signal adc_fclk_i : std_logic;
--- signal adc_dclk_i : std_logic;
--- signal adc_sc_clk32_o : std_logic;
--- signal adc_a_i : std_logic;
--- signal adc_b_i : std_logic;
--- signal adc_nx_i : std_logic;
--- signal adc_d_i : std_logic;
---
--- signal adc_ref_clk : std_logic;
--- signal adc_10MHz_clock : std_logic;
---
--- signal adc_dat_clk : std_logic;
--- signal adc_restart : std_logic;
--- signal adc_clk : std_logic;
---
--- signal adc_dat_clk_i : std_logic_vector(1 downto 0);
--- signal adc_fco_clk_i : std_logic_vector(1 downto 0);
---
--- signal adc_data_word : std_logic_vector(95 downto 0);
--- signal adc_fco : std_logic_vector(23 downto 0);
--- signal adc_data_valid : std_logic_vector(1 downto 0);
-
+ signal trigger_intern : std_logic;
+ signal nx_testpulse_o : std_logic;
+
begin
-------------------------------------------------------------------------------
-- DEBUG
-------------------------------------------------------------------------------
--- DEBUG_LINE_OUT(0) <= CLK_IN;
+-- DEBUG_LINE_OUT(0) <= nx_testpulse_o; --CLK_IN;
-- DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
-- DEBUG_LINE_OUT(2) <= ADC_SAMPLE_CLK_OUT;
-- DEBUG_LINE_OUT(7 downto 3) <= (others => '0');
-- DEBUG_LINE_OUT(14) <= ADC_D_IN;
-- DEBUG_LINE_OUT(15) <= '0';
- --DEBUG_LINE_OUT(15 downto 8) <= (others => '0');
+-- DEBUG_LINE_OUT(15 downto 8) <= slv_read(9 downto 2);
-------------------------------------------------------------------------------
-- Port Maps
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 9,
+ PORT_NUMBER => 10,
PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler
1 => x"0040", -- I2C Master
5 => x"0140", -- Trigger Generator
6 => x"0120", -- Data Validate
7 => x"0160", -- Trigger Handler
- 8 => x"0180", -- Timestamp Process
+ 8 => x"0180", -- Trigger Validate
+ 9 => x"0200", -- NX Register Setup
+
others => x"0000"),
PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
1 => 0, -- I2C master
2 => 3, -- Data Receiver
- 3 => 1, -- Data Buffer
+ 3 => 3, -- Data Buffer
4 => 0, -- SPI Master
5 => 3, -- Trigger Generator
6 => 4, -- Data Validate
7 => 1, -- Trigger Handler
- 8 => 4, -- Timestamp Process
+ 8 => 4, -- Trigger Validate
+ 9 => 8, -- NX Register Setup
others => 0)
)
port map(
CLK => CLK_IN,
RESET => RESET_IN,
+
DAT_ADDR_IN => REGIO_ADDR_IN,
DAT_DATA_IN => REGIO_DATA_IN,
DAT_DATA_OUT => REGIO_DATA_OUT,
BUS_WRITE_ENABLE_OUT(3) => slv_write(3),
BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32),
BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32),
- BUS_ADDR_OUT(3*16+0) => slv_addr(3*16+0),
- BUS_ADDR_OUT(3*16+15 downto 3*16+1) => open,
+ BUS_ADDR_OUT(3*16+2 downto 3*16) => slv_addr(3*16+2 downto 3*16),
+ BUS_ADDR_OUT(3*16+15 downto 3*16+3) => open,
BUS_TIMEOUT_OUT(3) => open,
BUS_DATAREADY_IN(3) => slv_ack(3),
BUS_WRITE_ACK_IN(3) => slv_ack(3),
BUS_NO_MORE_DATA_IN(8) => slv_no_more_data(8),
BUS_UNKNOWN_ADDR_IN(8) => slv_unknown_addr(8),
+ -- NX Register Setup
+ BUS_READ_ENABLE_OUT(9) => slv_read(9),
+ BUS_WRITE_ENABLE_OUT(9) => slv_write(9),
+ BUS_DATA_OUT(9*32+31 downto 9*32) => slv_data_wr(9*32+31 downto 9*32),
+ BUS_DATA_IN(9*32+31 downto 9*32) => slv_data_rd(9*32+31 downto 9*32),
+ BUS_ADDR_OUT(9*16+7 downto 9*16) => slv_addr(9*16+7 downto 9*16),
+ BUS_ADDR_OUT(9*16+15 downto 9*16+5) => open,
+ BUS_TIMEOUT_OUT(9) => open,
+ BUS_DATAREADY_IN(9) => slv_ack(9),
+ BUS_WRITE_ACK_IN(9) => slv_ack(9),
+ BUS_NO_MORE_DATA_IN(9) => slv_no_more_data(9),
+ BUS_UNKNOWN_ADDR_IN(9) => slv_unknown_addr(9),
+
---- debug
STAT_DEBUG => open
);
I2C_SM_RESET_OUT => i2c_sm_reset_o,
I2C_REG_RESET_OUT => i2c_reg_reset_o,
NX_TS_RESET_OUT => nx_ts_reset_1,
- --DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8)
+ OFFLINE_OUT => nxyter_offline,
+ --DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
+ nx_register_setup_1: nx_setup
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ I2C_COMMAND_OUT => i2c_command,
+ I2C_COMMAND_BUSY_IN => i2c_command_busy,
+ I2C_DATA_IN => i2c_data,
+ I2C_LOCK_OUT => i2c_lock,
+ SPI_COMMAND_OUT => spi_command,
+ SPI_COMMAND_BUSY_IN => spi_command_busy,
+ SPI_DATA_IN => spi_data,
+ SPI_LOCK_OUT => spi_lock,
+ SLV_READ_IN => slv_read(9),
+ SLV_WRITE_IN => slv_write(9),
+ SLV_DATA_OUT => slv_data_rd(9*32+31 downto 9*32),
+ SLV_DATA_IN => slv_data_wr(9*32+31 downto 9*32),
+ SLV_ADDR_IN => slv_addr(9*16+15 downto 9*16),
+ SLV_ACK_OUT => slv_ack(9),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(9),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(9),
+ --DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
+ );
+
-------------------------------------------------------------------------------
-- I2C master block for accessing the nXyter
-------------------------------------------------------------------------------
RESET_IN => RESET_IN,
SDA_INOUT => I2C_SDA_INOUT,
SCL_INOUT => I2C_SCL_INOUT,
+ INTERNAL_COMMAND_IN => i2c_command,
+ COMMAND_BUSY_OUT => i2c_command_busy,
+ I2C_DATA_OUT => i2c_data,
+ I2C_LOCK_IN => i2c_lock,
SLV_READ_IN => slv_read(1),
SLV_WRITE_IN => slv_write(1),
SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
SLV_ACK_OUT => slv_ack(1),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
- -- DEBUG_OUT => DEBUG_LINE_OUT
+ --DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
SCLK_OUT => SPI_SCLK_OUT,
SDIO_INOUT => SPI_SDIO_INOUT,
CSB_OUT => SPI_CSB_OUT,
+ INTERNAL_COMMAND_IN => spi_command,
+ COMMAND_BUSY_OUT => spi_command_busy,
+ SPI_DATA_OUT => spi_data,
+ SPI_LOCK_IN => spi_lock,
SLV_READ_IN => slv_read(4),
SLV_WRITE_IN => slv_write(4),
SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
nx_fpga_timestamp_1: nx_fpga_timestamp
port map (
- CLK_IN => clk_250_o,
+ CLK_IN => CLK_NX_IN,
RESET_IN => RESET_IN,
TIMESTAMP_SYNC_IN => nx_ts_reset_o,
TRIGGER_IN => timestamp_hold,
nx_trigger_handler_1: nx_trigger_handler
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TRIGGER_IN => trigger,
- TRIGGER_RELEASE_IN => not trigger_release,
- TRIGGER_OUT => trigger_ack,
- TIMESTAMP_HOLD_OUT => timestamp_hold,
- TRIGGER_BUSY_OUT => trigger_busy,
- SLV_READ_IN => slv_read(7),
- SLV_WRITE_IN => slv_write(7),
- SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
- SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),
- SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16),
- SLV_ACK_OUT => slv_ack(7),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
- -- DEBUG_OUT => DEBUG_LINE_OUT
- DEBUG_OUT => open
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ NXYTER_OFFLINE_IN => nxyter_offline,
+
+ LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
+ LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN,
+ LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN,
+ LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN,
+
+ LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
+ LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,
+ LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN,
+ LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
+ LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN,
+
+ FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT,
+ FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT,
+
+ INTERNAL_TRIGGER_IN => trigger_intern,
+
+ TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy,
+ LVL2_TRIGGER_BUSY_IN => trigger_evt_busy,
+
+ VALIDATE_TRIGGER_OUT => trigger,
+ TIMESTAMP_HOLD_OUT => timestamp_hold,
+ LVL2_TRIGGER_OUT => lvl2_trigger,
+ EVENT_BUFFER_CLEAR_OUT => event_buffer_clear,
+ FAST_CLEAR_OUT => fast_clear,
+ TRIGGER_BUSY_OUT => trigger_busy,
+
+ SLV_READ_IN => slv_read(7),
+ SLV_WRITE_IN => slv_write(7),
+ SLV_DATA_OUT => slv_data_rd(7*32+31 downto 7*32),
+ SLV_DATA_IN => slv_data_wr(7*32+31 downto 7*32),
+ SLV_ADDR_IN => slv_addr(7*16+15 downto 7*16),
+ SLV_ACK_OUT => slv_ack(7),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(7),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(7),
+
+ --DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
);
-
+
-------------------------------------------------------------------------------
-- NX Trigger Generator
-------------------------------------------------------------------------------
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
- TRIGGER_OUT => trigger,
+ TRIGGER_OUT => trigger_intern,
TS_RESET_OUT => nx_ts_reset_2,
TESTPULSE_OUT => nx_testpulse_o,
SLV_READ_IN => slv_read(5),
NX_TIMESTAMP_CLK_IN => NX_CLK128_IN,
NX_TIMESTAMP_IN => NX_TIMESTAMP_IN,
- ADC_CLK_DAT_SRC_IN => CLK_ADC_IN,
+ ADC_CLK_DAT_IN => CLK_ADC_IN,
ADC_FCLK_IN => ADC_FCLK_IN,
ADC_DCLK_IN => ADC_DCLK_IN,
ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT,
SLV_ACK_OUT => slv_ack(6),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6),
- DEBUG_OUT => DEBUG_LINE_OUT
- --DEBUG_OUT => open
+ --DEBUG_OUT => DEBUG_LINE_OUT
+ DEBUG_OUT => open
);
-------------------------------------------------------------------------------
--- NX Timestamp Process
+-- NX Trigger Validate
-------------------------------------------------------------------------------
nx_trigger_validate_1: nx_trigger_validate
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
-
+
DATA_CLK_IN => data_valid,
TIMESTAMP_IN => timestamp,
CHANNEL_IN => timestamp_channel_id,
NX_TOKEN_RETURN_IN => nx_token_return,
NX_NOMORE_DATA_IN => nx_nomore_data,
+ TRIGGER_IN => trigger,
+ FAST_CLEAR_IN => fast_clear,
+ TRIGGER_BUSY_OUT => trigger_validate_busy,
TIMESTAMP_REF_IN => timestamp_trigger,
- TRIGGER_IN => trigger_ack,
-
- PROCESS_BUSY_OUT => trigger_release,
- DATA_OUT => ts_data,
- DATA_CLK_OUT => ts_data_clk,
- DATA_FIFO_RESET_OUT => data_fifo_reset,
+
+ DATA_OUT => trigger_data,
+ DATA_CLK_OUT => trigger_data_clk,
+ NOMORE_DATA_OUT => validate_nomore_data,
SLV_READ_IN => slv_read(8),
SLV_WRITE_IN => slv_write(8),
SLV_ACK_OUT => slv_ack(8),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(8),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8),
- -- DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8),
- -- DEBUG_OUT(15 downto 8) => open
- DEBUG_OUT(15 downto 0) => open
+ DEBUG_OUT => DEBUG_LINE_OUT
+ --DEBUG_OUT => open
);
-------------------------------------------------------------------------------
-- Data Buffer FIFO
-------------------------------------------------------------------------------
- nx_data_buffer_1: nx_data_buffer
+ nx_event_buffer_1: nx_event_buffer
+ generic map (
+ BOARD_ID => BOARD_ID
+ )
port map (
- CLK_IN => CLK_IN,
- RESET_IN => data_buffer_reset,
- DATA_IN => ts_data,
- DATA_CLK_IN => ts_data_clk,
-
- SLV_READ_IN => slv_read(3),
- SLV_WRITE_IN => slv_write(3),
- SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
- SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
- SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
- SLV_ACK_OUT => slv_ack(3),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
-
- --DEBUG_OUT => DEBUG_LINE_OUT
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ RESET_DATA_BUFFER_IN => event_buffer_clear,
+ NXYTER_OFFLINE_IN => nxyter_offline,
+
+ DATA_IN => trigger_data,
+ DATA_CLK_IN => trigger_data_clk,
+ EVT_NOMORE_DATA_IN => validate_nomore_data,
+
+ LVL2_TRIGGER_IN => lvl2_trigger,
+ FAST_CLEAR_IN => fast_clear,
+ TRIGGER_BUSY_OUT => trigger_evt_busy,
+
+ FEE_DATA_OUT => FEE_DATA_OUT,
+ FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
+ FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
+ FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN,
+
+ SLV_READ_IN => slv_read(3),
+ SLV_WRITE_IN => slv_write(3),
+ SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
+ SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32),
+ SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16),
+ SLV_ACK_OUT => slv_ack(3),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+
+ --DEBUG_OUT => DEBUG_LINE_OUT
DEBUG_OUT => open
);
- data_buffer_reset <= RESET_IN or data_fifo_reset;
-
-------------------------------------------------------------------------------
-- nXyter Signals
-------------------------------------------------------------------------------
SLV_READ_IN : in std_logic;\r
SLV_WRITE_IN : in std_logic;\r
SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
- SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
- SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);\r
SLV_ACK_OUT : out std_logic;\r
SLV_NO_MORE_DATA_OUT : out std_logic;\r
SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
I2C_SM_RESET_OUT : out std_logic;\r
I2C_REG_RESET_OUT : out std_logic;\r
NX_TS_RESET_OUT : out std_logic;\r
+ OFFLINE_OUT : out std_logic;\r
\r
DEBUG_OUT : out std_logic_vector(15 downto 0)\r
);\r
signal i2c_sm_reset_o : std_logic;\r
signal i2c_reg_reset_o : std_logic;\r
signal nx_ts_reset_o : std_logic;\r
+ signal offline_o : std_logic;\r
\r
type STATES is (S_IDLE,\r
S_I2C_SM_RESET,\r
signal wait_timer_init : unsigned(7 downto 0);\r
signal wait_timer_done : std_logic;\r
\r
- type reg_32bit_t is array (0 to 7) of std_logic_vector(31 downto 0);\r
- signal reg_data : reg_32bit_t;\r
- \r
begin\r
\r
DEBUG_OUT(0) <= I2C_SM_RESET_OUT ;\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- reg_data(0) <= x"0000_0000";\r
- reg_data(1) <= x"0000_0000";\r
- reg_data(2) <= x"0000_0000";\r
- reg_data(3) <= x"babe_0003";\r
- reg_data(4) <= x"babe_0004";\r
- reg_data(5) <= x"babe_0005";\r
- reg_data(6) <= x"babe_0006";\r
- reg_data(7) <= x"babe_0007";\r
-\r
slv_data_out_o <= (others => '0');\r
slv_no_more_data_o <= '0';\r
slv_unknown_addr_o <= '0';\r
i2c_sm_reset_start <= '0';\r
i2c_reg_reset_start <= '0';\r
nx_ts_reset_start <= '0';\r
+ offline_o <= '1';\r
else\r
- slv_ack_o <= '1';\r
+ slv_ack_o <= '1';\r
slv_unknown_addr_o <= '0';\r
slv_no_more_data_o <= '0';\r
slv_data_out_o <= (others => '0'); \r
i2c_sm_reset_start <= '0';\r
i2c_reg_reset_start <= '0';\r
nx_ts_reset_start <= '0';\r
-\r
+ \r
if (SLV_WRITE_IN = '1') then\r
case SLV_ADDR_IN is\r
when x"0000" =>\r
- i2c_sm_reset_start <= '1';\r
- reg_data(0) <= std_logic_vector(unsigned(reg_data(0)) + 1);\r
- when x"0001" =>\r
- i2c_reg_reset_start <= '1';\r
- reg_data(1) <= std_logic_vector(unsigned(reg_data(1)) + 1);\r
- when x"0002" =>\r
- nx_ts_reset_start <= '1';\r
- reg_data(2) <= std_logic_vector(unsigned(reg_data(2)) + 1);\r
- when x"0003" => reg_data(3) <= SLV_DATA_IN;\r
- when x"0004" => reg_data(4) <= SLV_DATA_IN;\r
- when x"0005" => reg_data(5) <= SLV_DATA_IN;\r
- when x"0006" => reg_data(6) <= SLV_DATA_IN;\r
- when x"0007" => reg_data(7) <= SLV_DATA_IN;\r
- when others => slv_unknown_addr_o <= '1';\r
- slv_ack_o <= '0';\r
+ i2c_sm_reset_start <= '1';\r
+\r
+ when x"0001" => \r
+ i2c_reg_reset_start <= '1';\r
+\r
+ when x"0002" => \r
+ nx_ts_reset_start <= '1';\r
+\r
+ when x"0003" => \r
+ offline_o <= SLV_DATA_IN(0);\r
+ \r
+ when others => \r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
end case;\r
\r
elsif (SLV_READ_IN = '1') then\r
case SLV_ADDR_IN is\r
- when x"0000" => slv_data_out_o <= reg_data(0);\r
- when x"0001" => slv_data_out_o <= reg_data(1);\r
- when x"0002" => slv_data_out_o <= reg_data(2);\r
- when x"0003" => slv_data_out_o <= reg_data(3);\r
- when x"0004" => slv_data_out_o <= reg_data(4);\r
- when x"0005" => slv_data_out_o <= reg_data(5);\r
- when x"0006" => slv_data_out_o <= reg_data(6);\r
- when x"0007" => slv_data_out_o <= reg_data(7);\r
- when others => slv_unknown_addr_o <= '1';\r
- slv_ack_o <= '0';\r
+ when x"0003" =>\r
+ slv_data_out_o(0) <= offline_o;\r
+ slv_data_out_o(31 downto 1) <= (others => '0');\r
+\r
+ when others =>\r
+ slv_unknown_addr_o <= '1';\r
+ slv_ack_o <= '0';\r
end case;\r
\r
else\r
I2C_SM_RESET_OUT <= i2c_sm_reset_o;\r
I2C_REG_RESET_OUT <= i2c_reg_reset_o;\r
NX_TS_RESET_OUT <= nx_ts_reset_o;\r
-\r
+ OFFLINE_OUT <= offline_o;\r
end Behavioral;\r
LEVEL_OUT : out std_logic
);
-end pulse_to_level;
+end entity;
architecture Behavioral of pulse_to_level is
CTR_WIDTH => 5
)
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- TIMER_START_IN => start_timer,
- TIMER_DONE_OUT => timer_done
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ TIMER_START_IN => start_timer,
+ TIMER_DONE_OUT => timer_done
);
PROC_CONVERT: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- start_timer <= (others => '0');
- level_o <= '0';
- STATE <= IDLE;
+ start_timer <= (others => '0');
+ level_o <= '0';
+ STATE <= IDLE;
else
level_o <= '0';
- start_timer <= (others => '0');
+ start_timer <= (others => '0');
case STATE is
-- Control Register
-0x8100 : r/w w: reset I2C State Machine r: reset ctr
-0x8101 : r/w w: reset I2C all Register r: reset ctr
-0x8102 : r/w w: Reset and Sync Timestamps (nXyter and FPGA) r: reset ctr
+0x8100 : w w: reset I2C State Machine
+0x8101 : w w: reset I2C all Register
+0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA)
+0x8103 : r/w Put nxyter into offline mode
-- NX Data Validate
0x8120 : rw Invalid Frame Counter (16 bit) / w: clear all counters
0x8144 : r/w Bit0 : 1: send timestamp-reset before trigger
-- Trigger Handler
-0x8160 : r/w Bit 15-0 : Delay Trigger in Timestamp Hold
+0x8160 : r/w Bit 15-0 : Delay Timestamp Hold signal (8bit, 10ns)
-- NX Data Receiver
0x8500 : r current Timestamp FIFO value
-- Event Data Buffer
0x8600 : r read FIFO buffer
-0x8601 : r/w r: read FIFO status
+0x8601 : r FIFO write counter
+0x8602 : r FIFO flush counter
+0x8603 : r/w r: read FIFO status
w: enable/disable FIFO write
-- I2C Master
add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd"
add_file -vhdl -lib "work" "cores/pll_adc_clk32.vhd"
add_file -vhdl -lib "work" "cores/pll_adc_clk192.vhd"
-#add_file -vhdl -lib "work" "cores/fifo_32to32_dc.vhd"
add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd"
-add_file -vhdl -lib "work" "cores/fifo_12_adc.vhd"
add_file -vhdl -lib "work" "cores/fifo_32_data.vhd"
add_file -vhdl -lib "work" "trb3_periph.vhd"
-
add_file -vhdl -lib "work" "source/nxyter_components.vhd"
add_file -vhdl -lib "work" "source/level_to_pulse.vhd"
add_file -vhdl -lib "work" "source/pulse_to_level.vhd"
add_file -vhdl -lib "work" "source/nx_data_receiver.vhd"
add_file -vhdl -lib "work" "source/nx_data_validate.vhd"
add_file -vhdl -lib "work" "source/nx_trigger_validate.vhd"
-add_file -vhdl -lib "work" "source/nx_data_buffer.vhd"
+add_file -vhdl -lib "work" "source/nx_event_buffer.vhd"
-add_file -vhdl -lib "work" "source/nxyter_data_handler.vhd"
add_file -vhdl -lib "work" "source/nxyter_registers.vhd"
+add_file -vhdl -lib "work" "source/nx_setup.vhd"
add_file -vhdl -lib "work" "source/nx_i2c_master.vhd"
add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd"
NX1_ADC_B_IN : in std_logic;
NX1_ADC_NX_IN : in std_logic;
NX1_ADC_D_IN : in std_logic;
-
NX1B_ADC_FCLK_IN : in std_logic;
NX1B_ADC_DCLK_IN : in std_logic;
NX1B_ADC_A_IN : in std_logic;
NX2_ADC_B_IN : in std_logic;
NX2_ADC_NX_IN : in std_logic;
NX2_ADC_D_IN : in std_logic;
-
+ NX2B_ADC_FCLK_IN : in std_logic;
+ NX2B_ADC_DCLK_IN : in std_logic;
+ NX2B_ADC_A_IN : in std_logic;
+ NX2B_ADC_B_IN : in std_logic;
+ NX2B_ADC_NX_IN : in std_logic;
+ NX2B_ADC_D_IN : in std_logic;
---------------------------------------------------------------------------
-- END AddonBoard nXyter
signal trg_spike_detected_i : std_logic;
--Data channel
- signal fee_trg_release_i : std_logic;
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
- signal fee_data_i : std_logic_vector(31 downto 0);
- signal fee_data_write_i : std_logic;
- signal fee_data_finished_i : std_logic;
- signal fee_almost_full_i : std_logic;
+ signal fee_trg_release_i : std_logic_vector(2-1 downto 0);
+ signal fee_trg_statusbits_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_i : std_logic_vector(2*32-1 downto 0);
+ signal fee_data_write_i : std_logic_vector(2-1 downto 0);
+ signal fee_data_finished_i : std_logic_vector(2-1 downto 0);
+ signal fee_almost_full_i : std_logic_vector(2-1 downto 0);
--Slow Control channel
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal time_counter : unsigned(31 downto 0);
- -- NXYTER Clock
+ -- nXyter-FEE-Board Clocks
+ signal nx_clk256 : std_logic;
signal pll_lock_clk256 : std_logic;
+ signal clk_adc_dat : std_logic;
+ signal clk_adc_dat_lock : std_logic;
-- nXyter 1 Regio Bus
signal nx1_regio_addr_in : std_logic_vector (15 downto 0);
signal nx1_regio_write_ack_out : std_logic;
signal nx1_regio_no_more_data_out : std_logic;
signal nx1_regio_unknown_addr_out : std_logic;
-
+
signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0);
signal nx1_clk128_sim_o : std_logic;
- signal nx1_clk256_o : std_logic;
-
-- nXyter 2 Regio Bus
signal nx2_regio_addr_in : std_logic_vector (15 downto 0);
signal nx2_regio_data_in : std_logic_vector (31 downto 0);
signal nx2_regio_write_ack_out : std_logic;
signal nx2_regio_no_more_data_out : std_logic;
signal nx2_regio_unknown_addr_out : std_logic;
-
- signal nx2_clk256_o : std_logic;
-
+
+ signal nx2_timestamp_sim_o : std_logic_vector(7 downto 0);
+ signal nx2_clk128_sim_o : std_logic;
+
begin
---------------------------------------------------------------------------
-- Reset Generation
--BROADCAST_SPECIAL_ADDR => x"45",
BROADCAST_SPECIAL_ADDR => x"48",
REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000003",
- REGIO_INIT_ADDRESS => x"f305",
+ REGIO_HARDWARE_VERSION => x"9100_6000",
+ REGIO_INIT_ADDRESS => x"1100",
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
CLOCK_FREQUENCY => 125,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1,
+ DATA_INTERFACE_NUMBER => 2,
DATA_BUFFER_DEPTH => 13, --13
DATA_BUFFER_WIDTH => 32,
DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
- FEE_DATA_IN => fee_data_i,
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+ --Response from FEE, i.e. nXyter #0
+ FEE_TRG_RELEASE_IN(0) => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_IN(0*32+31 downto 0*32) => fee_trg_statusbits_i(0*32+31 downto 0*32),
+ FEE_DATA_IN(0*32+31 downto 0*32) => fee_data_i(0*32+31 downto 0*32),
+ FEE_DATA_WRITE_IN(0) => fee_data_write_i(0),
+ FEE_DATA_FINISHED_IN(0) => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i(0),
+
+ --Response from FEE, i.e. nXyter #1
+ FEE_TRG_RELEASE_IN(1) => fee_trg_release_i(1),
+ FEE_TRG_STATUSBITS_IN(1*32+31 downto 1*32) => fee_trg_statusbits_i(1*32+31 downto 1*32),
+ FEE_DATA_IN(1*32+31 downto 1*32) => fee_data_i(1*32+31 downto 1*32),
+ FEE_DATA_WRITE_IN(1) => fee_data_write_i(1),
+ FEE_DATA_FINISHED_IN(1) => fee_data_finished_i(1),
+ FEE_DATA_ALMOST_FULL_OUT(1) => fee_almost_full_i(1),
-- Slow Control Data Port
REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
);
timing_trg_received_i <= TRIGGER_LEFT;
-
+
+-- fee_trg_release_i(1) <= '1';
+-- fee_data_i(1*32+31 downto 1*32) <= (others => '1');
+-- fee_trg_statusbits_i(1*32+31 downto 1*32) <= (others => '0');
+-- fee_data_write_i(1) <= '0';
+-- fee_data_finished_i(1) <= '1';
+
---------------------------------------------------------------------------
-- AddOn
---------------------------------------------------------------------------
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 3,
+ PORT_NUMBER => 4,
PORT_ADDRESSES => (0 => x"d000",
1 => x"d100",
2 => x"8000",
- -- 3 => x"9000",
+ 3 => x"9000",
others => x"0000"),
PORT_ADDR_MASK => (0 => 1,
1 => 6,
2 => 12,
- -- 3 => 12,
+ 3 => 12,
others => 0)
)
port map(
BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
- -- --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
- -- BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
- -- BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
- -- BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
- -- BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in,
- -- BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in,
- -- BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
- -- BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
- -- BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
- -- BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
- -- BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
+ --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
+ BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
+ BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
+ BUS_ADDR_OUT(3*16+11 downto 3*16) => nx2_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(3*16+15 downto 3*16+12) => open,
+ BUS_TIMEOUT_OUT(3) => open, --nx2_regio_timeout_in,
+ BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
+ BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
+ BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
+
STAT_DEBUG => open
);
LED_RED <= timing_trg_received_i;
LED_YELLOW <= not med_stat_op(11);
--------------------------------------------------------------------------------
--- nXyter Data Handler
--------------------------------------------------------------------------------
- nXyter_data_handler_1: nXyter_data_handler
+-----------------------------------------------------------------------------
+-- The xXyter-FEB #1
+-----------------------------------------------------------------------------
+
+ nXyter_FEE_board_0: nXyter_FEE_board
+ generic map (
+ BOARD_ID => x"affe"
+ )
port map (
CLK_IN => clk_100_i,
RESET_IN => reset_i,
-
- REGIO_ADDR_IN => open, --REGIO_ADDR_IN,
- REGIO_DATA_IN => open, --REGIO_DATA_IN,
- REGIO_DATA_OUT => open, --REGIO_DATA_OUT,
- REGIO_READ_ENABLE_IN => open, --REGIO_READ_ENABLE_IN,
- REGIO_WRITE_ENABLE_IN => open, --REGIO_WRITE_ENABLE_IN,
- REGIO_TIMEOUT_IN => open, --REGIO_TIMEOUT_IN,
- REGIO_DATAREADY_OUT => open, --REGIO_DATAREADY_OUT,
- REGIO_WRITE_ACK_OUT => open, --REGIO_WRITE_ACK_OUT,
- REGIO_NO_MORE_DATA_OUT => open, --REGIO_NO_MORE_DATA_OUT,
- REGIO_UNKNOWN_ADDR_OUT => open, --REGIO_UNKNOWN_ADDR_OUT,
+ CLK_NX_IN => nx_clk256,
+ CLK_ADC_IN => clk_adc_dat,
+
+ I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX1_SPI_CSB_OUT,
+
+ NX_CLK128_IN => NX1_CLK128_IN,
+ NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
+ -- NX_CLK128_IN => nx1_clk128_sim_o,
+ -- NX_TIMESTAMP_IN => nx1_timestamp_sim_o,
+
+ NX_RESET_OUT => NX1_RESET_OUT,
+ NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
+
+ ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => NX1_ADC_SAMPLE_CLK_OUT,
+ ADC_A_IN(0) => NX1_ADC_A_IN,
+ ADC_A_IN(1) => NX1B_ADC_A_IN,
+ ADC_B_IN(0) => NX1_ADC_B_IN,
+ ADC_B_IN(1) => NX1B_ADC_B_IN,
+ ADC_NX_IN(0) => NX1_ADC_NX_IN,
+ ADC_NX_IN(1) => NX1B_ADC_NX_IN,
+ ADC_D_IN(0) => NX1_ADC_D_IN,
+ ADC_D_IN(1) => NX1B_ADC_D_IN,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
LVL1_TRG_INFORMATION_IN => trg_information_i,
LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
- FEE_TRG_RELEASE_OUT => fee_trg_release_i,
- FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i,
- FEE_DATA_OUT => fee_data_i,
- FEE_DATA_WRITE_OUT => fee_data_write_i,
- FEE_DATA_FINISHED_OUT => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i,
-
- -- DEBUG_LINE_OUT => TEST_LINE
- DEBUG_LINE_OUT => open
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(0),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(31 downto 0),
+ FEE_DATA_OUT => fee_data_i(31 downto 0),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(0),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(0),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(0),
+
+ REGIO_ADDR_IN => nx1_regio_addr_in,
+ REGIO_DATA_IN => nx1_regio_data_in,
+ REGIO_DATA_OUT => nx1_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+
+ DEBUG_LINE_OUT => TEST_LINE
+ --DEBUG_LINE_OUT => open
);
-
+
-----------------------------------------------------------------------------
--- The xXyter-FEB
+-- The xXyter-FEB #2
-----------------------------------------------------------------------------
nXyter_FEE_board_1: nXyter_FEE_board
+ generic map (
+ BOARD_ID => x"babe"
+ )
port map (
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- CLK_ADC_IN => CLK_PCLK_LEFT,
+ CLK_IN => clk_100_i,
+ RESET_IN => reset_i,
+ CLK_NX_IN => nx_clk256,
+ CLK_ADC_IN => clk_adc_dat,
+
+ I2C_SDA_INOUT => NX2_I2C_SDA_INOUT,
+ I2C_SCL_INOUT => NX2_I2C_SCL_INOUT,
+ I2C_SM_RESET_OUT => NX2_I2C_SM_RESET_OUT,
+ I2C_REG_RESET_OUT => NX2_I2C_REG_RESET_OUT,
+
+ SPI_SCLK_OUT => NX2_SPI_SCLK_OUT,
+ SPI_SDIO_INOUT => NX2_SPI_SDIO_INOUT,
+ SPI_CSB_OUT => NX2_SPI_CSB_OUT,
- I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
- I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
- I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
- I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
-
- SPI_SCLK_OUT => NX1_SPI_SCLK_OUT,
- SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT,
- SPI_CSB_OUT => NX1_SPI_CSB_OUT,
-
- NX_CLK128_IN => NX1_CLK128_IN,
- NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
- -- NX_CLK128_IN => nx1_clk128_sim_o,
- -- NX_TIMESTAMP_IN => nx1_timestamp_sim_o,
+ NX_CLK128_IN => NX2_CLK128_IN,
+ NX_TIMESTAMP_IN => NX2_TIMESTAMP_IN,
+
+ NX_RESET_OUT => NX2_RESET_OUT,
+ NX_TESTPULSE_OUT => NX2_TESTPULSE_OUT,
+
+ ADC_FCLK_IN(0) => NX2_ADC_FCLK_IN,
+ ADC_FCLK_IN(1) => NX2B_ADC_FCLK_IN,
+ ADC_DCLK_IN(0) => NX2_ADC_DCLK_IN,
+ ADC_DCLK_IN(1) => NX2B_ADC_DCLK_IN,
+ ADC_SAMPLE_CLK_OUT => NX2_ADC_SAMPLE_CLK_OUT,
+ ADC_A_IN(0) => NX2_ADC_A_IN,
+ ADC_A_IN(1) => NX2B_ADC_A_IN,
+ ADC_B_IN(0) => NX2_ADC_B_IN,
+ ADC_B_IN(1) => NX2B_ADC_B_IN,
+ ADC_NX_IN(0) => NX2_ADC_NX_IN,
+ ADC_NX_IN(1) => NX2B_ADC_NX_IN,
+ ADC_D_IN(0) => NX2_ADC_D_IN,
+ ADC_D_IN(1) => NX2B_ADC_D_IN,
+
+ LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
+ LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
+ LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
+ LVL1_INVALID_TRG_IN => trg_invalid_i,
+ LVL1_TRG_TYPE_IN => trg_type_i,
+ LVL1_TRG_NUMBER_IN => trg_number_i,
+ LVL1_TRG_CODE_IN => trg_code_i,
+ LVL1_TRG_INFORMATION_IN => trg_information_i,
+ LVL1_INT_TRG_NUMBER_IN => trg_int_number_i,
+
+ FEE_TRG_RELEASE_OUT => fee_trg_release_i(1),
+ FEE_TRG_STATUSBITS_OUT => fee_trg_statusbits_i(63 downto 32),
+ FEE_DATA_OUT => fee_data_i(63 downto 32),
+ FEE_DATA_WRITE_OUT => fee_data_write_i(1),
+ FEE_DATA_FINISHED_OUT => fee_data_finished_i(1),
+ FEE_DATA_ALMOST_FULL_IN => fee_almost_full_i(1),
- NX_RESET_OUT => NX1_RESET_OUT,
- NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
-
- ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN,
- ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN,
- ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN,
- ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN,
- ADC_SAMPLE_CLK_OUT => NX1_ADC_SAMPLE_CLK_OUT,
- ADC_A_IN(0) => NX1_ADC_A_IN,
- ADC_A_IN(1) => NX1B_ADC_A_IN,
- ADC_B_IN(0) => NX1_ADC_B_IN,
- ADC_B_IN(1) => NX1B_ADC_B_IN,
- ADC_NX_IN(0) => NX1_ADC_NX_IN,
- ADC_NX_IN(1) => NX1B_ADC_NX_IN,
- ADC_D_IN(0) => NX1_ADC_D_IN,
- ADC_D_IN(1) => NX1B_ADC_D_IN,
-
- REGIO_ADDR_IN => nx1_regio_addr_in,
- REGIO_DATA_IN => nx1_regio_data_in,
- REGIO_DATA_OUT => nx1_regio_data_out,
- REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in,
- REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in,
- REGIO_TIMEOUT_IN => nx1_regio_timeout_in,
- REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
- REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
- REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
-
- DEBUG_LINE_OUT => TEST_LINE
- -- DEBUG_LINE_OUT => open
+ REGIO_ADDR_IN => nx2_regio_addr_in,
+ REGIO_DATA_IN => nx2_regio_data_in,
+ REGIO_DATA_OUT => nx2_regio_data_out,
+ REGIO_READ_ENABLE_IN => nx2_regio_read_enable_in,
+ REGIO_WRITE_ENABLE_IN => nx2_regio_write_enable_in,
+ REGIO_TIMEOUT_IN => nx2_regio_timeout_in,
+ REGIO_DATAREADY_OUT => nx2_regio_dataready_out,
+ REGIO_WRITE_ACK_OUT => nx2_regio_write_ack_out,
+ REGIO_NO_MORE_DATA_OUT => nx2_regio_no_more_data_out,
+ REGIO_UNKNOWN_ADDR_OUT => nx2_regio_unknown_addr_out,
+
+ --DEBUG_LINE_OUT => TEST_LINE
+ DEBUG_LINE_OUT => open
);
+ -----------------------------------------------------------------------------
+ -- nXyter common Clocks
+ -----------------------------------------------------------------------------
pll_nx_clk256_1: entity work.pll_nx_clk256
port map (
CLK => clk_100_i,
- CLKOP => nx1_clk256_o,
+ CLKOP => nx_clk256,
LOCK => pll_lock_clk256
);
- NX1_CLK256A_OUT <= nx1_clk256_o;
+ NX1_CLK256A_OUT <= nx_clk256;
+ NX2_CLK256A_OUT <= nx_clk256;
+
+ -- ADC Receiver Clock
+ pll_adc_clk192_1: pll_adc_clk192
+ port map (
+ CLK => CLK_PCLK_LEFT,
+ CLKOP => clk_adc_dat,
+ LOCK => clk_adc_dat_lock
+ );
+ -----------------------------------------------------------------------------
-- 250MHz Clock to nXyters
--pll_nx_clk250_1: entity work.pll_nx_clk250
FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
FREQUENCY PORT NX1_CLK256A_OUT 256 MHz;
+ FREQUENCY PORT NX2_CLK256A_OUT 256 MHz;
#Put the names of your nxyter inputs here:
FREQUENCY PORT NX1_CLK128_IN 128 MHz;
FREQUENCY PORT NX2_ADC_DCLK_IN 192 MHz;
#Change the next two lines to the clk_fast signal of the ADC
- USE PRIMARY2EDGE NET "nXyter_FEE_board_1/adc_receiver_1/pll_192MHz";
- USE PRIMARY NET "nXyter_FEE_board_1/adc_receiver_1/pll_192MHz";
-
- USE PRIMARY NET "CLK_PCLK_LEFT";
- USE PRIMARY NET "CLK_PCLK_LEFT_c";
-
USE PRIMARY2EDGE NET "THE_MAIN_PLL/PLLInst_0";
USE PRIMARY NET "THE_MAIN_PLL/PLLInst_0";
- USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT";
- USE PRIMARY NET "NX1_ADC_SC_CLK32_OUT_c";
+
+ USE PRIMARY NET "CLK_PCLK_LEFT";
+ USE PRIMARY NET "CLK_PCLK_LEFT_c";
+
+ USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT";
+ USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT_c";
+ USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT";
+ USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT_c";
+ USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+ USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+
+ #USE PRIMARY2EDGE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
+ #USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_dat_clk";
#################################################################
# Reset Nets
PROHIBIT PRIMARY NET "NX1_CLK128_IN_c";
PROHIBIT SECONDARY NET "NX1_CLK128_IN_c";
+PROHIBIT PRIMARY NET "NX2_CLK128_IN_c";
+PROHIBIT SECONDARY NET "NX2_CLK128_IN_c";
+
PROHIBIT PRIMARY NET "TEST_LINE_c_0";
PROHIBIT SECONDARY NET "TEST_LINE_c_0";
-DEFINE PORT GROUP "NX_IN" "NX1_TIMESTAMP_*";
-INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ;
+DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ;
+
+DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*";
+INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN" ;
-MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c_c" 50 ns;
+MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c" 50 ns;
+MULTICYCLE FROM CLKNET "NX2_CLK256A_OUT_c" 50 ns;
#PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN_c";
#PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN_c";
jspc29 / trb3.git / commitdiff