update template project

diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl
index 6c1aa49b0c99408e14f0e402c6897c251763b806..c29ab11dc7f6c9f08be3d69fb2464e01c6b5a9ec 100644 (file)
--- a/template/config_compile_frankfurt.pl
+++ b/template/config_compile_frankfurt.pl
@@ -8,7 +8,7 @@ TOPNAME                      => "trb5sc_template",
 lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@jspc29",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.12',
-synplify_path                => '/d/jspc29/lattice/synplify/S-2021.09-SP2/',
+synplify_path                => '/d/jspc29/lattice/synplify/T-2022.09-SP2/',
 
 nodelist_file                => '../nodelist_frankfurt.txt',
 pinout_file                  => 'trb5sc_tdc',

diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj
index ad431384c908f24ab4eb479b64ba6563c0ba96fb..07b06ab27167bf3f00309fde0de63c4f905829d6 100644 (file)
--- a/template/trb5sc_template.prj
+++ b/template/trb5sc_template.prj
@@ -127,6 +127,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"

diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd
index 9256c3f75a97110151953bc94fb7587c548d8b1a..58351093509d83cf6cd13c467079131ba56e5d9c 100644 (file)
--- a/template/trb5sc_template.vhd
+++ b/template/trb5sc_template.vhd
@@ -67,7 +67,7 @@ entity trb5sc_template is
     
     --Other Connectors
     TEST    : inout std_logic_vector(14 downto 1);
-    HDR_IO  : inout std_logic_vector(15 downto 0)
+    HDR_IO  : inout std_logic_vector(23 downto 0)
     );
 
 
@@ -130,7 +130,7 @@ architecture arch of trb5sc_template is
   
   signal link_stat_in_reg : std_logic;
 
-
+  signal header_i : std_logic_vector(10 downto 1);
 
 begin
 
@@ -175,7 +175,7 @@ THE_CAL_PLL : entity work.pll_in125_out50
   THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync
     generic map(
       SERDES_NUM    => 0,
-      USE_NEW_ECP5_RESET => 0,
+      USE_NEW_ECP5_RESET => 1,
       IS_SYNC_SLAVE => c_YES
       )
     port map(
@@ -386,7 +386,7 @@ THE_CAL_PLL : entity work.pll_in125_out50
 
   assert     DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
 
-  HDR_IO(15 downto 10) <= (others => '0');
+  HDR_IO(23 downto 10) <= (others => '0');
   TEST(13 downto 1)    <= (others => '0');
   TEST(14) <= flash_ncs_i;
   FLASH_NCS <= flash_ncs_i;