--- /dev/null
+*.jhd
+*.naf
+*.srp
+*.sym
+*.log
+*tmpl.vhd
+*pp
+*readme
+*tft
entity trb_net16_med_scm_sfp_gbe is
generic(
SERDES_NUM : integer range 0 to 3 := 0; -- DO NOT CHANGE
- EXT_CLOCK : integer range 0 to 1 := c_NO; -- DO NOT CHANGE
- USE_200_MHZ: integer range 0 to 1 := c_YES -- DO NOT CHANGE
+ EXT_CLOCK : integer range 0 to 1 := c_NO;
+ USE_200_MHZ: integer range 0 to 1 := c_YES
);
port(
CLK : in std_logic; -- SerDes clock
\r
\r
#################################################################\r
-# Aux Flash\r
+# FPGA Flash\r
#################################################################\r
-LOCATE COMP "SPI_D_IN" SITE "AG5" ;\r
-LOCATE COMP "SPI_SCK_OUT" SITE "AL4" ;\r
-LOCATE COMP "SPI_CS_OUT" SITE "AL3" ;\r
-LOCATE COMP "SPI_SI_OUT" SITE "AF7" ;\r
+LOCATE COMP "SPI_D_IN" SITE "B14"; #"AG5" ;\r
+LOCATE COMP "SPI_SCK_OUT" SITE "F16"; #SITE "AL4" ;\r
+LOCATE COMP "SPI_CS_OUT" SITE "K15"; #SITE "AL3" ;\r
+LOCATE COMP "SPI_SI_OUT" SITE "J15"; #SITE "AF7" ;\r
\r
DEFINE PORT GROUP "SPI_group" "SPI*" ;\r
IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=8;\r
\r
+LOCATE COMP "PROGRMN_OUT" SITE "AM4";\r
+IOBUF PORT "PROGRMN_OUT" IO_TYPE=LVTTL33 PULLMODE=UP;\r
\r
#################################################################\r
# I2C Tempsens\r
-- missing: end of PP/RDCMD by data_done signal.\r
\r
entity spi_slim is\r
+ generic(\r
+ SLOW_SPI : integer range c_YES to c_NO := c_YES\r
+ );\r
port(\r
SYSCLK : in std_logic; -- 100MHz sysclock\r
RESET : in std_logic; -- synchronous reset\r
architecture Behavioral of spi_slim is\r
\r
-- new clock divider\r
-signal div_counter : std_logic_vector(1 downto 0);\r
+signal div_counter : std_logic_vector(1+SLOW_SPI downto 0);\r
signal div_done_x : std_logic;\r
signal div_done : std_logic; -- same as clk_en\r
signal clk_en : std_logic; -- same as div_done\r
\r
signal addr_ctr : std_logic_vector(7 downto 0);\r
signal data_done_x : std_logic;\r
-signal data_done : std_logic_vector(2 downto 0);\r
+signal data_done : std_logic_vector(5 downto 0);\r
\r
signal last_tx_bit_x : std_logic;\r
signal last_tx_bit : std_logic;\r
end if;\r
end process THE_CLOCK_DIVIDER;\r
\r
-div_done_x <= '1' when ( div_counter = b"00" ) else '0';\r
+div_done_x <= '1' when ( or_all(div_counter) = '0' ) else '0';\r
\r
-spi_sck_x <= '1' when ( ((div_counter = b"11") or (div_counter = b"00")) and\r
+spi_sck_x <= '1' when ( ((div_counter(1+SLOW_SPI downto 0+SLOW_SPI) = b"11") or (div_counter(1+SLOW_SPI downto 0+SLOW_SPI) = b"00")) and\r
((tx_ena = '1') or (rx_ena = '1')) ) else '0';\r
\r
clk_en <= div_done;\r
-----------------------------------------------------------\r
-- state machine transition table\r
-----------------------------------------------------------\r
-THE_STATE_TRANSITIONS: process( STATE, cmd_int, start, tx_bit_cnt, rx_bit_cnt, data_done(2) )\r
+THE_STATE_TRANSITIONS: process( STATE, cmd_int, start, tx_bit_cnt, rx_bit_cnt, data_done(5) )\r
begin\r
rx_ena_x <= '0';\r
tx_ena_x <= '0';\r
\r
when WAIT6 =>\r
case cmd_int is\r
- when PP => if( data_done(2) = '1' ) then\r
+ when PP => if( data_done(5) = '1' ) then\r
NEXT_STATE <= CSH;\r
spi_cs_x <= '0';\r
else\r
when WAIT8 =>\r
case cmd_int is\r
when RDCMD | RDID | RDSR | RDSPR\r
- => if( data_done(2) = '1' ) then\r
+ => if( data_done(5) = '1' ) then\r
NEXT_STATE <= CSH;\r
spi_cs_x <= '0';\r
else\r
elsif( ce_addr = '1' ) then\r
addr_ctr <= addr_ctr + 1;\r
end if;\r
- data_done(2 downto 1) <= data_done(1 downto 0);\r
+ data_done(5 downto 1) <= data_done(4 downto 0);\r
data_done(0) <= data_done_x;\r
inc_addr_rx <= inc_addr_rx_x;\r
inc_addr_tx <= inc_addr_tx_x;\r
library work;
use work.trb_net_std.all;
use work.trb_net_components.all;
+use work.pcie_components.all;
use work.trb_net16_hub_func.all;
entity trb_net_bridge_pcie_endpoint_hub is
port(
RESET : in std_logic;
CLK : in std_logic;
+ CLK_125_IN : in std_logic;
BUS_ADDR_IN : in std_logic_vector(31 downto 0);
BUS_WDAT_IN : in std_logic_vector(31 downto 0);
MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);
MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);
+ REQUESTOR_ID_IN : in std_logic_vector(15 downto 0);
+ TX_ST_OUT : out std_logic; --tx first word
+ TX_END_OUT : out std_logic; --tx last word
+ TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit
+ TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out
+ TX_REQ_OUT : out std_logic; --tx request out
+ TX_RDY_IN : in std_logic; --tx arbiter can read
+ TX_VAL_IN : in std_logic; --tx data is valid
+ TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write
+ TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words
+ TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read
+
+ RX_CR_CPLH_OUT : out std_logic;
+ RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0);
+ UNEXP_CMPL_OUT : out std_logic;
+ RX_ST_IN : in std_logic;
+ RX_END_IN : in std_logic;
+ RX_DWEN_IN : in std_logic;
+ RX_DATA_IN : in std_logic_vector(63 downto 0);
+
+ PROGRMN_OUT : out std_logic;
SEND_RESET_OUT : out std_logic;
DEBUG_OUT : out std_logic_vector (31 downto 0)
);
signal bus_spi_ack_i : std_logic;
signal bus_spi_data_i : std_logic_vector(31 downto 0);
+ signal spi_bram_addr : std_logic_vector(7 downto 0);
+ signal spi_bram_wr_d : std_logic_vector(7 downto 0);
+ signal spi_bram_rd_d : std_logic_vector(7 downto 0);
+ signal spi_bram_we : std_logic;
+
+ signal spictrl_read_en : std_logic;
+ signal spictrl_write_en : std_logic;
+ signal spictrl_ack : std_logic;
+ signal spictrl_data_out : std_logic_vector(31 downto 0);
+ signal spimem_read_en : std_logic;
+ signal spimem_write_en : std_logic;
+ signal spimem_ack : std_logic;
+ signal spimem_data_out : std_logic_vector(31 downto 0);
+ signal spi_fake_ack : std_logic;
+
+ signal dma_start_address_i : std_logic_vector(31 downto 0);
+ signal dma_length_i : std_logic_vector(31 downto 0);
+ signal dma_control_i : std_logic_vector(31 downto 0);
+ signal dma_status_i : std_logic_vector(31 downto 0);
+ signal dma_config_i : std_logic_vector(31 downto 0);
+ signal apl_read_dma : std_logic;
+ signal debug_dma_core : std_logic_vector(31 downto 0);
+ signal status_dma_core : std_logic_vector(127 downto 0);
+
+ signal do_reprogram_i : std_logic;
+ signal reprogram_i : std_logic;
+ signal restart_fpga_counter: unsigned(11 downto 0);
+
begin
RESET_i <= RESET;
apl_to_buf_REPLY_PACKET_NUM(9) <= '0';
-
--- APL : trb_net_bridge_pcie_apl
--- port map(
--- CLK => CLK,
--- RESET => RESET_i,
--- CLK_EN => '1',
--- APL_DATA_OUT => apl_data_in,
--- APL_PACKET_NUM_OUT => apl_packet_num_in,
--- APL_DATAREADY_OUT => apl_dataready_in,
--- APL_READ_IN => apl_read_out,
--- APL_SHORT_TRANSFER_OUT => apl_short_transfer_in,
--- APL_DTYPE_OUT => apl_dtype_in,
--- APL_ERROR_PATTERN_OUT => apl_error_pattern_in,
--- APL_SEND_OUT => apl_send_in,
--- APL_DATA_IN => apl_data_out,
--- APL_PACKET_NUM_IN => apl_packet_num_out,
--- APL_TYP_IN => apl_typ_out,
--- APL_DATAREADY_IN => apl_dataready_out,
--- APL_READ_OUT => apl_read_in,
--- APL_RUN_IN => apl_run_out,
--- APL_SEQNR_IN => apl_seqnr_out,
--- APL_TARGET_ADDRESS_OUT => apl_target_address_in,
--- APL_FIFO_COUNT_IN => apl_fifo_count_out,
--- EXT_TRIGGER_INFO => reg_extended_trigger_information,
--- BUS_ADDR_IN => BUS_ADDR_IN,
--- BUS_WDAT_IN => BUS_WDAT_IN,
--- BUS_RDAT_OUT => BUS_RDAT_OUT,
--- BUS_SEL_IN => BUS_SEL_IN,
--- BUS_WE_IN => BUS_WE_IN,
--- BUS_CYC_IN => BUS_CYC_IN,
--- BUS_STB_IN => BUS_STB_IN,
--- BUS_LOCK_IN => BUS_LOCK_IN,
--- BUS_ACK_OUT => BUS_ACK_OUT,
--- SEND_RESET_OUT => SEND_RESET_OUT,
--- STAT => open,
--- CTRL => (others => '0')
--- );
-
-
--------------------------------
-- r/w registers
--------------------------------
end process;
bus_stb_rising <= BUS_STB_IN and not bus_stb_last;
- bus_read_i <= not BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"00";
- bus_write_i <= BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"00";
+ bus_read_i <= not BUS_WE_IN and bus_stb_rising and not or_all(BUS_ADDR_IN(23 downto 16));
+ bus_write_i <= BUS_WE_IN and bus_stb_rising and not or_all(BUS_ADDR_IN(23 downto 16));
+
- bus_spi_read_i <= not BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"01";
- bus_spi_write_i <= BUS_WE_IN and bus_stb_rising and BUS_ADDR_IN(23 downto 16) = x"01";
channel_address <= to_integer(unsigned(BUS_ADDR_IN(6 downto 5)));
& "00000" & apl_fifo_count_out(11*channel_address+10 downto 11*channel_address);
when x"30" =>
bus_data_i <= api_status(channel_address*32+31 downto channel_address*32);
+ when x"70" =>
+ bus_data_i <= dma_start_address_i;
+ when x"71" =>
+ bus_data_i <= dma_length_i;
+ when x"72" =>
+ bus_data_i <= dma_status_i;
+ when x"73" =>
+ bus_data_i <= dma_config_i;
+ when x"74" =>
+ bus_data_i <= status_dma_core(31 downto 0);
+ when x"75" =>
+ bus_data_i <= status_dma_core(63 downto 32);
+ when x"76" =>
+ bus_data_i <= status_dma_core(95 downto 64);
+ when x"77" =>
+ bus_data_i <= status_dma_core(127 downto 96);
when others =>
bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19);
end case;
sender_control <= (others => '0');
sender_target <= (others => '0');
sender_error <= (others => '0');
+ dma_control_i <= (others => '0');
+ dma_start_address_i <= (others => '0');
+ dma_length_i <= (others => '0');
+ reg_extended_trigger_information <= (others => '0');
+ dma_config_i <= x"0000001f";
else
+ dma_control_i <= (others => '0');
+ do_reprogram_i <= '0';
if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" and USE_CHANNELS(channel_address) = c_YES then
case BUS_ADDR_IN(3 downto 0) is
--middle nibble is dont care
end if;
when others => null;
end case;
+ elsif bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"7" then
+ case BUS_ADDR_IN(3 downto 0) is
+ when x"0" =>
+ dma_start_address_i <= BUS_WDAT_IN;
+ when x"1" =>
+ dma_length_i <= BUS_WDAT_IN;
+ when x"2" =>
+ dma_control_i <= BUS_WDAT_IN; --pulses only!
+ when x"3" =>
+ dma_config_i <= BUS_WDAT_IN;
+ when others => null;
+ end case;
+ elsif bus_write_i = '1' and BUS_ADDR_IN(23 downto 0) = x"000020" then
+ do_reprogram_i <= '1';
end if;
end if;
end if;
-- apl_target_address_in <= sender_target(111 downto 96) & sender_target(47 downto 32) & sender_target(15 downto 0);
apl_dtype_in <= sender_control(99 downto 96) & sender_control(35 downto 32) & sender_control(3 downto 0);
- apl_read_in <= fifo_net_to_pci_read(3) & fifo_net_to_pci_read(1) & fifo_net_to_pci_read(0);
+ apl_read_in <= (fifo_net_to_pci_read(3) or apl_read_dma) & fifo_net_to_pci_read(1) & fifo_net_to_pci_read(0);
fifo_net_to_pci_empty <= not (apl_dataready_out(2) & '0' & apl_dataready_out(1) & apl_dataready_out(0));
fifo_net_to_pci_dout(31 downto 0) <= "0000000" & fifo_net_to_pci_valid_read(0) & "000000"
& apl_packet_num_out(2) & apl_packet_num_out(0) & apl_data_out(15 downto 0);
begin
if rising_edge(CLK) then
apl_send_in <= next_apl_send_in;
- if bus_spi_ack_i = '1' then
- BUS_RDAT_OUT <= bus_spi_data_i(31 downto 0);
+ if spictrl_ack = '1' then
+ BUS_RDAT_OUT <= spictrl_data_out;
+ elsif spimem_ack = '1' then
+ BUS_RDAT_OUT <= spimem_data_out;
else
BUS_RDAT_OUT <= bus_data_i(31 downto 0);
end if;
end process;
+THE_DMA_CORE : dma_core
+ port map(
+ RESET_IN => reset_i,
+ CLK_IN => CLK,
+ CLK_125_IN => CLK_125_IN,
+
+ DMA_START_ADDR_IN => dma_start_address_i,
+ DMA_LENGTH_IN => dma_length_i,
+ DMA_CONTROL_IN => dma_control_i,
+ DMA_STATUS_OUT => dma_status_i,
+ DMA_CONFIG_IN => dma_config_i,
+
+ API_RUNNING_IN => apl_run_out(2),
+ API_DATA_IN => apl_data_out(47 downto 32),
+ API_PACKET_NUM_IN => apl_packet_num_out(8 downto 6),
+ API_TYP_IN => apl_typ_out(8 downto 6),
+ API_DATAREADY_IN => apl_dataready_out(2),
+ API_READ_OUT => apl_read_dma,
+
+ REQUESTOR_ID_IN => REQUESTOR_ID_IN,
+ TX_ST_OUT => TX_ST_OUT,
+ TX_END_OUT => TX_END_OUT,
+ TX_DWEN_OUT => TX_DWEN_OUT,
+ TX_DATA_OUT => TX_DATA_OUT,
+ TX_REQ_OUT => TX_REQ_OUT,
+ TX_RDY_IN => TX_RDY_IN,
+ TX_VAL_IN => TX_VAL_IN,
+ TX_CA_PH_IN => TX_CA_PH_IN,
+ TX_CA_PD_IN => TX_CA_PD_IN,
+ TX_CA_NPH_IN => TX_CA_NPH_IN,
+
+ RX_CR_CPLH_OUT => RX_CR_CPLH_OUT,
+ RX_CR_CPLD_OUT => RX_CR_CPLD_OUT,
+ UNEXP_CMPL_OUT => UNEXP_CMPL_OUT,
+ RX_ST_IN => RX_ST_IN,
+ RX_END_IN => RX_END_IN,
+ RX_DWEN_IN => RX_DWEN_IN,
+ RX_DATA_IN => RX_DATA_IN,
+
+ STATUS_REG_OUT => status_dma_core,
+ DEBUG_OUT => debug_dma_core
+
+ );
+
+
--------------------------------
-- SPI Flash Programming
--------------------------------
--- bus_spi_write_i --strobe
--- bus_spi_read_i --strobe
--- BUS_WDAT_IN --32bit write data valid with strobe
--- BUS_ADDR_IN --15 downto 0 - your address space
---
--- bus_spi_ack_i -- ack strobe from SPI handler
--- bus_spi_data_i -- 32bit data from SPI
---
--- SPI_CLK_OUT : out std_logic;
--- SPI_D_OUT : out std_logic;
--- SPI_D_IN : in std_logic;
--- SPI_CE_OUT : out std_logic;
+
+ THE_SPI_MASTER: spi_master
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+ -- Slave bus
+ BUS_READ_IN => spictrl_read_en,
+ BUS_WRITE_IN => spictrl_write_en,
+ BUS_BUSY_OUT => open, --spictrl_busy,
+ BUS_ACK_OUT => spictrl_ack,
+ BUS_ADDR_IN(0) => BUS_ADDR_IN(0), --spictrl_addr,
+ BUS_DATA_IN => BUS_WDAT_IN, --spictrl_data_in,
+ BUS_DATA_OUT => spictrl_data_out,
+ -- SPI connections
+ SPI_CS_OUT => SPI_CE_OUT,
+ SPI_SDI_IN => SPI_D_IN,
+ SPI_SDO_OUT => SPI_D_OUT,
+ SPI_SCK_OUT => SPI_CLK_OUT,
+ -- BRAM for read/write data
+ BRAM_A_OUT => spi_bram_addr,
+ BRAM_WR_D_IN => spi_bram_wr_d,
+ BRAM_RD_D_OUT => spi_bram_rd_d,
+ BRAM_WE_OUT => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+ -- data memory for SPI accesses
+ THE_SPI_MEMORY: spi_databus_memory
+ port map(
+ CLK_IN => CLK,
+ RESET_IN => RESET,
+ -- Slave bus
+ BUS_READ_IN => spimem_read_en,
+ BUS_WRITE_IN => spimem_write_en,
+ BUS_ACK_OUT => spimem_ack,
+ BUS_ADDR_IN => BUS_ADDR_IN(5 downto 0),
+ BUS_DATA_IN => BUS_WDAT_IN, --spimem_data_in,
+ BUS_DATA_OUT => spimem_data_out,
+ -- state machine connections
+ BRAM_ADDR_IN => spi_bram_addr,
+ BRAM_WR_D_OUT => spi_bram_wr_d,
+ BRAM_RD_D_IN => spi_bram_rd_d,
+ BRAM_WE_IN => spi_bram_we,
+ -- Status lines
+ STAT => open
+ );
+
+
+
+ spictrl_read_en <= '1' when BUS_WE_IN = '0' and bus_stb_rising = '1' and
+ BUS_ADDR_IN(23 downto 8) = x"01d0" else '0';
+ spictrl_write_en <= '1' when BUS_WE_IN = '1' and bus_stb_rising = '1' and
+ BUS_ADDR_IN(23 downto 8) = x"01d0" else '0';
+
+ spimem_read_en <= '1' when BUS_WE_IN = '0' and bus_stb_rising = '1' and
+ BUS_ADDR_IN(23 downto 8) = x"01d1" else '0';
+ spimem_write_en <= '1' when BUS_WE_IN = '1' and bus_stb_rising = '1' and
+ BUS_ADDR_IN(23 downto 8) = x"01d1" else '0';
+
+
+ bus_spi_ack_i <= spimem_ack or spictrl_ack or spi_fake_ack;
+ spi_fake_ack <= '1' when (BUS_ADDR_IN(23 downto 16) = x"01" and bus_stb_rising = '1' and
+ (spictrl_read_en or spictrl_write_en or spimem_read_en or spimem_write_en) = '0')
+ else '0';
+
+
+---------------------------------------------------------------------------
+--Restart FPGA from Flash
+---------------------------------------------------------------------------
+ --delay restart command to finish trbnet transfer
+ process (CLK)
+ begin
+ if rising_edge(CLK) then
+ PROGRMN_OUT <= not reprogram_i;
+ reprogram_i <= '0';
+ if RESET = '1' then
+ restart_fpga_counter <= to_unsigned(0,12);
+ elsif do_reprogram_i = '1' then
+ restart_fpga_counter <= to_unsigned(4095,12);
+ elsif restart_fpga_counter /= to_unsigned(0,12) then
+ restart_fpga_counter <= restart_fpga_counter - to_unsigned(1,1);
+ if restart_fpga_counter <= to_unsigned(255,12) then
+ reprogram_i <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
--------------------------------
end if;
end process;
-
+DEBUG_OUT <= debug_dma_core;
end architecture;
\ No newline at end of file
--- /dev/null
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all;
+
+entity pcie_tb is
+end entity;
+
+architecture arch of pcie_tb is
+
+component trb_net_bridge_pcie_endpoint_hub is
+ generic(
+ NUM_LINKS : integer range 1 to 4 := 2;
+ COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')
+ );
+ port(
+ RESET : in std_logic;
+ CLK : in std_logic;
+
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);
+ BUS_WE_IN : in std_logic;
+ BUS_CYC_IN : in std_logic;
+ BUS_STB_IN : in std_logic;
+ BUS_LOCK_IN : in std_logic;
+ BUS_ACK_OUT : out std_logic;
+
+ MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);
+
+ MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);
+ MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);
+
+ MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);
+ MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);
+
+ SEND_RESET_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector (31 downto 0)
+ );
+end component;
+
+ constant NUM_LINKS : integer := 2;
+
+ signal CLK : std_logic := '1';
+ signal RESET : std_logic := '1';
+
+ signal BUS_ADDR_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal BUS_WDAT_IN : std_logic_vector(31 downto 0) := (others => '0');
+ signal BUS_RDAT_OUT : std_logic_vector(31 downto 0) := (others => '0');
+ signal BUS_SEL_IN : std_logic_vector(3 downto 0) := (others => '0');
+ signal BUS_WE_IN : std_logic := '0';
+ signal BUS_CYC_IN : std_logic := '0';
+ signal BUS_STB_IN : std_logic := '0';
+ signal BUS_LOCK_IN : std_logic := '0';
+ signal BUS_ACK_OUT : std_logic := '0';
+
+ signal MED_DATAREADY_IN : std_logic_vector (NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_DATA_IN : std_logic_vector (16*NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_PACKET_NUM_IN : std_logic_vector (3*NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_READ_OUT : std_logic_vector (NUM_LINKS-1 downto 0) := (others => '0');
+
+ signal MED_DATAREADY_OUT : std_logic_vector (NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_DATA_OUT : std_logic_vector (16*NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_PACKET_NUM_OUT : std_logic_vector (3*NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_READ_IN : std_logic_vector (NUM_LINKS-1 downto 0) := (others => '0');
+
+ signal MED_STAT_OP_IN : std_logic_vector (16*NUM_LINKS-1 downto 0) := (others => '0');
+ signal MED_CTRL_OP_OUT : std_logic_vector (16*NUM_LINKS-1 downto 0) := (others => '0');
+
+
+begin
+
+ CLK <= not CLK after 5 ns;
+ RESET <= '0' after 100 ns;
+ MED_STAT_OP_IN <= (others => '0');
+
+ UT : trb_net_bridge_pcie_endpoint_hub
+ port map(
+ RESET => RESET,
+ CLK => CLK,
+
+ BUS_ADDR_IN => BUS_ADDR_IN,
+ BUS_WDAT_IN => BUS_WDAT_IN,
+ BUS_RDAT_OUT => BUS_RDAT_OUT,
+ BUS_SEL_IN => BUS_SEL_IN,
+ BUS_WE_IN => BUS_WE_IN,
+ BUS_CYC_IN => BUS_CYC_IN,
+ BUS_STB_IN => BUS_STB_IN,
+ BUS_LOCK_IN => BUS_LOCK_IN,
+ BUS_ACK_OUT => BUS_ACK_OUT,
+
+ MED_DATAREADY_IN => MED_DATAREADY_IN,
+ MED_DATA_IN => MED_DATA_IN,
+ MED_PACKET_NUM_IN => MED_PACKET_NUM_IN,
+ MED_READ_OUT => MED_READ_OUT,
+
+ MED_DATAREADY_OUT => MED_DATAREADY_OUT,
+ MED_DATA_OUT => MED_DATA_OUT,
+ MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
+ MED_READ_IN => MED_READ_IN,
+
+ MED_STAT_OP_IN => MED_STAT_OP_IN,
+ MED_CTRL_OP_OUT => MED_CTRL_OP_OUT,
+
+ SEND_RESET_OUT => open,
+ DEBUG_OUT => open
+ );
+
+ process
+ begin
+ BUS_SEL_IN <= x"F";
+ BUS_WDAT_IN <= (others => '0');
+
+ wait for 500 ns;
+ wait until rising_edge(CLK);
+ BUS_ADDR_IN <= x"00000174";
+ BUS_WE_IN <= '1';
+ BUS_CYC_IN <= '1';
+ BUS_STB_IN <= '1';
+ BUS_LOCK_IN <= '1';
+ wait until BUS_ACK_OUT <= '1';
+ BUS_CYC_IN <= '0';
+ BUS_LOCK_IN <= '0';
+ BUS_STB_IN <= '0';
+ wait until BUS_ACK_OUT <= '0';
+
+ wait until rising_edge(CLK);
+ BUS_ADDR_IN <= x"00000174";
+ BUS_WE_IN <= '1';
+ BUS_CYC_IN <= '1';
+ BUS_STB_IN <= '1';
+ BUS_LOCK_IN <= '1';
+ wait until BUS_ACK_OUT <= '1';
+ BUS_CYC_IN <= '0';
+ BUS_LOCK_IN <= '0';
+ BUS_STB_IN <= '0';
+ wait until BUS_ACK_OUT <= '0';
+
+ wait until rising_edge(CLK);
+ BUS_ADDR_IN <= x"00000174";
+ BUS_WE_IN <= '1';
+ BUS_CYC_IN <= '1';
+ BUS_STB_IN <= '1';
+ BUS_LOCK_IN <= '1';
+ wait until BUS_ACK_OUT <= '1';
+ BUS_CYC_IN <= '0';
+ BUS_LOCK_IN <= '0';
+ BUS_STB_IN <= '0';
+ wait until BUS_ACK_OUT <= '0';
+
+ wait until rising_edge(CLK);
+ BUS_ADDR_IN <= x"00000174";
+ BUS_WE_IN <= '1';
+ BUS_CYC_IN <= '1';
+ BUS_STB_IN <= '1';
+ BUS_LOCK_IN <= '1';
+ wait until BUS_ACK_OUT <= '1';
+ BUS_CYC_IN <= '0';
+ BUS_LOCK_IN <= '0';
+ BUS_STB_IN <= '0';
+ wait until BUS_ACK_OUT <= '0';
+
+
+ wait until rising_edge(CLK);
+ BUS_ADDR_IN <= x"00000170";
+ BUS_WE_IN <= '1';
+ BUS_CYC_IN <= '1';
+ BUS_STB_IN <= '1';
+ BUS_LOCK_IN <= '1';
+ wait until BUS_ACK_OUT <= '1';
+ BUS_CYC_IN <= '0';
+ BUS_LOCK_IN <= '0';
+ BUS_STB_IN <= '0';
+ wait until BUS_ACK_OUT <= '0';
+
+ wait;
+ end process;
+
+
+end architecture;
\ No newline at end of file
USE_ONEWIRE : integer range 0 to 2 := c_YES;
BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
--media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4;
+ MII_NUMBER : integer range 1 to c_MAX_MII_PER_HUB := 4;
MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
signal HUB_CTRL_TIMEOUT_TIME : std_logic_vector (31 downto 0);
signal HUB_ADDRESS : std_logic_vector (15 downto 0);
signal HUBLOGIC_IPU_STAT_DEBUG : std_logic_vector (31 downto 0);
- signal HUB_ERROR_BITS : std_logic_vector (16*4*32-1 downto 0);
+ signal HUB_ERROR_BITS : std_logic_vector (16*32-1 downto 0);
signal buf_HUB_ALL_ERROR_BITS : std_logic_vector ((16*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal IOBUF_STAT_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1))*32-1 downto 0);
signal received_retransmit_requests : counter8b_t;
signal sent_retransmit_requests : counter8b_t;
+ signal dummy : std_logic_vector(270 downto 0);
+ signal tmp_buf_to_hub_REPLY_DATA_ctrl : std_logic_vector(15 downto 0);
+
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
attribute syn_preserve of m_DATA_IN : signal is true;
APL_LENGTH_IN => (others => '1'),
-- Internal direction port
INT_MASTER_DATAREADY_OUT => buf_to_hub_REPLY_DATAREADY(i),
- INT_MASTER_DATA_OUT => buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
+ INT_MASTER_DATA_OUT => tmp_buf_to_hub_REPLY_DATA_ctrl,
INT_MASTER_PACKET_NUM_OUT => buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
INT_MASTER_READ_IN => buf_to_hub_REPLY_READ(i),
INT_MASTER_DATAREADY_IN => hub_to_buf_REPLY_DATAREADY(i),
STAT_FIFO_TO_INT => open,
STAT_FIFO_TO_APL => open
);
- end generate;
+
+--Workaround to get channel number right in local hub in pcie bridge
+ PROC_CORRECT_CHANNEL : process(tmp_buf_to_hub_REPLY_DATA_ctrl, buf_to_hub_REPLY_PACKET_NUM)
+ begin
+ if buf_to_hub_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) = c_H0 then
+ buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= tmp_buf_to_hub_REPLY_DATA_ctrl or x"0038";
+ else
+ buf_to_hub_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= tmp_buf_to_hub_REPLY_DATA_ctrl;
+ end if;
+ end process;
+
+end generate;
+
---------------------------------------------------------------------
--Connection for additional internal interfaces
HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
HUB_INIT_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
buf_HUB_ALL_ERROR_BITS((i+1)*32-1 downto i*32) <= (others => '0');
+ HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32) <= (others => '0');
+ hub_ctrl_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16) <= (others => '0');
+ iobuf_stat_data_counter((i+1)*32-1 downto i*32) <= (others => '0');
+ stat_timeout((i+1)*32-1 downto i*32) <= (others => '0');
end generate;
end generate;
end generate;
+-- THE_BUS_HANDLER : trb_net16_regio_bus_handler
+-- generic map(
+-- PORT_NUMBER => 7,
+-- PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", others => x"0000"),
+-- PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, others => 0)
+-- )
+-- port map(
+-- CLK => CLK,
+-- RESET => reset_i,
+--
+-- DAT_ADDR_IN => DAT_ADDR_OUT,
+-- DAT_DATA_IN => DAT_DATA_OUT,
+-- DAT_DATA_OUT => DAT_DATA_IN,
+-- DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
+-- DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
+-- DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
+-- DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
+-- DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
+-- DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
+-- DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
+--
+-- BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
+-- BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
+-- BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
+-- BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
+-- BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
+-- BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
+-- BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
+-- BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
+-- BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
+-- BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
+--
+-- BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
+-- BUS_ADDR_OUT(31 downto 21) => open,
+-- BUS_DATA_OUT(63 downto 32) => open,
+-- BUS_READ_ENABLE_OUT(1) => stat_packets_read,
+-- BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
+-- BUS_TIMEOUT_OUT(1) => open,
+-- BUS_DATA_IN(63 downto 32) => stat_packets_data,
+-- BUS_DATAREADY_IN(1) => stat_packets_ready,
+-- BUS_WRITE_ACK_IN(1) => stat_packets_ack,
+-- BUS_NO_MORE_DATA_IN(1) => '0',
+-- BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
+--
+-- BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
+-- BUS_ADDR_OUT(47 downto 36) => open,
+-- BUS_DATA_OUT(95 downto 64) => open,
+-- BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
+-- BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
+-- BUS_TIMEOUT_OUT(2) => open,
+-- BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
+-- BUS_DATAREADY_IN(2) => stat_errorbits_ready,
+-- BUS_WRITE_ACK_IN(2) => '0',
+-- BUS_NO_MORE_DATA_IN(2) => '0',
+-- BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
+--
+-- BUS_ADDR_OUT(51 downto 48) => stat_busycntincl_addr,
+-- BUS_ADDR_OUT(63 downto 52) => open,
+-- BUS_DATA_OUT(127 downto 96) => open,
+-- BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
+-- BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
+-- BUS_TIMEOUT_OUT(3) => open,
+-- BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
+-- BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
+-- BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
+-- BUS_NO_MORE_DATA_IN(3) => '0',
+-- BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
+--
+-- BUS_ADDR_OUT(67 downto 64) => stat_busycntexcl_addr,
+-- BUS_ADDR_OUT(79 downto 68) => open,
+-- BUS_DATA_OUT(159 downto 128) => open,
+-- BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
+-- BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
+-- BUS_TIMEOUT_OUT(4) => open,
+-- BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data,
+-- BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
+-- BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
+-- BUS_NO_MORE_DATA_IN(4) => '0',
+-- BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
+--
+-- BUS_ADDR_OUT(95 downto 80) => open,
+-- BUS_DATA_OUT(191 downto 160) => open,
+-- BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
+-- BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
+-- BUS_TIMEOUT_OUT(5) => open,
+-- BUS_DATA_IN(191 downto 160) => global_time,
+-- BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
+-- BUS_WRITE_ACK_IN(5) => '0',
+-- BUS_NO_MORE_DATA_IN(5) => '0',
+-- BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
+--
+-- BUS_ADDR_OUT(99 downto 96) => lsm_addr,
+-- BUS_ADDR_OUT(111 downto 100) => open,
+-- BUS_DATA_OUT(223 downto 192) => open,
+-- BUS_READ_ENABLE_OUT(6) => lsm_read,
+-- BUS_WRITE_ENABLE_OUT(6) => lsm_write,
+-- BUS_TIMEOUT_OUT(6) => open,
+-- BUS_DATA_IN(223 downto 192) => lsm_data,
+-- BUS_DATAREADY_IN(6) => last_lsm_read,
+-- BUS_WRITE_ACK_IN(6) => '0',
+-- BUS_NO_MORE_DATA_IN(6) => '0',
+-- BUS_UNKNOWN_ADDR_IN(6) => lsm_write,
+--
+-- STAT_DEBUG => open
+-- );
+
+--Fucking Modelsim wants it like this...
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
PORT_NUMBER => 7,
DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
- BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
- BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
- BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
- BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
- BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
- BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
- BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
- BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
- BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
- BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
+ BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
- BUS_ADDR_OUT(31 downto 21) => open,
- BUS_DATA_OUT(63 downto 32) => open,
- BUS_READ_ENABLE_OUT(1) => stat_packets_read,
- BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(63 downto 32) => stat_packets_data,
- BUS_DATAREADY_IN(1) => stat_packets_ready,
- BUS_WRITE_ACK_IN(1) => stat_packets_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
-
+ BUS_ADDR_OUT(31 downto 21) => dummy(10 downto 0),
BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
- BUS_ADDR_OUT(47 downto 36) => open,
- BUS_DATA_OUT(95 downto 64) => open,
- BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
- BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
- BUS_DATAREADY_IN(2) => stat_errorbits_ready,
- BUS_WRITE_ACK_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
-
+ BUS_ADDR_OUT(47 downto 36) => dummy(21 downto 10),
BUS_ADDR_OUT(51 downto 48) => stat_busycntincl_addr,
- BUS_ADDR_OUT(63 downto 52) => open,
- BUS_DATA_OUT(127 downto 96) => open,
- BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
- BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
- BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
- BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
-
+ BUS_ADDR_OUT(63 downto 52) => dummy(33 downto 22),
BUS_ADDR_OUT(67 downto 64) => stat_busycntexcl_addr,
- BUS_ADDR_OUT(79 downto 68) => open,
- BUS_DATA_OUT(159 downto 128) => open,
- BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
- BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
- BUS_TIMEOUT_OUT(4) => open,
+ BUS_ADDR_OUT(79 downto 68) => dummy(44 downto 33),
+ BUS_ADDR_OUT(95 downto 80) => dummy(60 downto 45),
+ BUS_ADDR_OUT(99 downto 96) => lsm_addr,
+ BUS_ADDR_OUT(111 downto 100) => dummy(72 downto 61),
+ BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
+ BUS_DATA_IN(63 downto 32) => stat_packets_data,
+ BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
+ BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data,
- BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
- BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
-
- BUS_ADDR_OUT(95 downto 80) => open,
- BUS_DATA_OUT(191 downto 160) => open,
- BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
- BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
- BUS_TIMEOUT_OUT(5) => open,
BUS_DATA_IN(191 downto 160) => global_time,
- BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
- BUS_WRITE_ACK_IN(5) => '0',
- BUS_NO_MORE_DATA_IN(5) => '0',
- BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
-
- BUS_ADDR_OUT(99 downto 96) => lsm_addr,
- BUS_ADDR_OUT(111 downto 100) => open,
- BUS_DATA_OUT(223 downto 192) => open,
- BUS_READ_ENABLE_OUT(6) => lsm_read,
- BUS_WRITE_ENABLE_OUT(6) => lsm_write,
- BUS_TIMEOUT_OUT(6) => open,
BUS_DATA_IN(223 downto 192) => lsm_data,
+ BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
+ BUS_DATA_OUT(63 downto 32) => dummy(104 downto 73),
+ BUS_DATA_OUT(95 downto 64) => dummy(136 downto 105),
+ BUS_DATA_OUT(127 downto 96) => dummy(168 downto 137),
+ BUS_DATA_OUT(159 downto 128) => dummy(200 downto 169),
+ BUS_DATA_OUT(191 downto 160) => dummy(232 downto 201),
+ BUS_DATA_OUT(223 downto 192) => dummy(264 downto 233),
+ BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
+ BUS_DATAREADY_IN(1) => stat_packets_ready,
+ BUS_DATAREADY_IN(2) => stat_errorbits_ready,
+ BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
+ BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
+ BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
BUS_DATAREADY_IN(6) => last_lsm_read,
- BUS_WRITE_ACK_IN(6) => '0',
+ BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_NO_MORE_DATA_IN(2) => '0',
+ BUS_NO_MORE_DATA_IN(3) => '0',
+ BUS_NO_MORE_DATA_IN(4) => '0',
+ BUS_NO_MORE_DATA_IN(5) => '0',
BUS_NO_MORE_DATA_IN(6) => '0',
+ BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
+ BUS_READ_ENABLE_OUT(1) => stat_packets_read,
+ BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
+ BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
+ BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
+ BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
+ BUS_READ_ENABLE_OUT(6) => lsm_read,
+ BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
+ BUS_TIMEOUT_OUT(1) => dummy(265),
+ BUS_TIMEOUT_OUT(2) => dummy(266),
+ BUS_TIMEOUT_OUT(3) => dummy(267),
+ BUS_TIMEOUT_OUT(4) => dummy(268),
+ BUS_TIMEOUT_OUT(5) => dummy(269),
+ BUS_TIMEOUT_OUT(6) => dummy(270),
+ BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
+ BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
+ BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
+ BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
+ BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
+ BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
BUS_UNKNOWN_ADDR_IN(6) => lsm_write,
+ BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
+ BUS_WRITE_ACK_IN(1) => stat_packets_ack,
+ BUS_WRITE_ACK_IN(2) => '0',
+ BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
+ BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
+ BUS_WRITE_ACK_IN(5) => '0',
+ BUS_WRITE_ACK_IN(6) => '0',
+ BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
+ BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
+ BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
+ BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
+ BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
+ BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
+ BUS_WRITE_ENABLE_OUT(6) => lsm_write,
STAT_DEBUG => open
);
-
---------------------------------------------------------------------
--1-wire interface
---------------------------------------------------------------------
when 1 => current_timeout_value(k) <= std_logic_vector(to_unsigned(64,16) - unsigned(hub_level&'0'));
when 2 => current_timeout_value(k) <= std_logic_vector(to_unsigned(128,16) - unsigned(hub_level&'0'));
when 3 => current_timeout_value(k) <= std_logic_vector(to_unsigned(256,16) - unsigned(hub_level&'0'));
- when 4 => current_timeout_value(k) <= std_logic_vector(to_unsigned(1000,16) - unsigned(hub_level&'0'));
- when 5 => current_timeout_value(k) <= std_logic_vector(to_unsigned(2000,16) - unsigned(hub_level&'0'));
- when 6 => current_timeout_value(k) <= std_logic_vector(to_unsigned(4000,16) - unsigned(hub_level&'0'));
- when 7 => current_timeout_value(k) <= std_logic_vector(to_unsigned(8000,16) - unsigned(hub_level&'0'));
+ when 4 => current_timeout_value(k) <= std_logic_vector(to_unsigned(1024,16) - unsigned(hub_level&'0'));
+ when 5 => current_timeout_value(k) <= std_logic_vector(to_unsigned(2048,16) - unsigned(hub_level&'0'));
+ when 6 => current_timeout_value(k) <= std_logic_vector(to_unsigned(4096,16) - unsigned(hub_level&'0'));
+ when 7 => current_timeout_value(k) <= std_logic_vector(to_unsigned(8192,16) - unsigned(hub_level&'0'));
when others => current_timeout_value(k) <= std_logic_vector(to_unsigned(0,16));
end case;
end if;
--Usual common stat reg, trigger counters are not in use here
- HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0);
- HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT;
- HC_COMMON_STAT_REGS(63 downto 32) <= COMMON_STAT_REGS(63 downto 32);
+ HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0);
+ HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT;
+ HC_COMMON_STAT_REGS(255 downto 32) <= COMMON_STAT_REGS(255 downto 32);
--Status Registers
buf_HC_STAT_REGS(3*32+31 downto 0) <= buf_STAT_POINTS_locked;
buf_HC_STAT_REGS(5*32+31 downto 5*32+17) <= (others => '0');
buf_HC_STAT_REGS(6*32+31 downto 6*32+17) <= (others => '0');
buf_HC_STAT_REGS(7*32+31 downto 7*32) <= stat_ipu_fsm;
- buf_HC_STAT_REGS(15*32-1 downto 8*32) <= (others => '0');
+ buf_HC_STAT_REGS(15*32+31 downto 8*32) <= (others => '0');
buf_HC_STAT_REGS(16*32+MII_NUMBER-1 downto 16*32) <= mii_error(MII_NUMBER-1 downto 0);
buf_HC_STAT_REGS(30*32+31 downto 16*32+MII_NUMBER) <= (others => '0');
buf_HC_STAT_REGS(31*32+31 downto 31*32) <= buf_HUB_MISMATCH_PATTERN;
end loop;
end if;
end process;
-
+ mii_error(31 downto MII_NUMBER) <= (others => '0');
PROC_TIMEOUT : process(CLK)
begin
last_lsm_read <= next_last_lsm_read;
next_lsm_data(7 downto 0) <= MED_STAT_OP(tmp*16+7 downto tmp*16+0);
next_lsm_data(15 downto 8) <= (others => '0');
- next_lsm_data(23 downto 16) <= received_retransmit_requests(tmp);
- next_lsm_data(31 downto 24) <= sent_retransmit_requests(tmp);
+ next_lsm_data(23 downto 16) <= std_logic_vector(received_retransmit_requests(tmp));
+ next_lsm_data(31 downto 24) <= std_logic_vector(sent_retransmit_requests(tmp));
lsm_data <= next_lsm_data;
end if;
end process;
end if;
end process;
end generate;
-
+-- received_retransmit_requests(15 downto MII_NUMBER) <= (others => '0');
+-- sent_retransmit_requests(15 downto MII_NUMBER) <= (others => '0');
------------------------------------
--STAT busy counters
if stat_busycntincl_read = '1' then
tmp := to_integer(unsigned(stat_busycntincl_addr));
if tmp < MII_NUMBER then
- stat_busycntincl_data <= busy_counter_incl(tmp);
+ stat_busycntincl_data <= std_logic_vector(busy_counter_incl(tmp));
stat_busycntincl_ready <= '1';
else
stat_busycntincl_data <= (others => '0');
if stat_busycntexcl_read = '1' then
tmp := to_integer(unsigned(stat_busycntexcl_addr));
if tmp < MII_NUMBER then
- stat_busycntexcl_data <= busy_counter_excl(tmp);
+ stat_busycntexcl_data <= std_logic_vector(busy_counter_excl(tmp));
stat_busycntexcl_ready <= '1';
else
stat_busycntexcl_data <= (others => '0');
constant c_MAX_TRG_PER_HUB : integer := 8;
constant c_MAX_POINTS_PER_HUB : integer := 18;
- constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 1,6,6,6, --MII 0
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6,
- 1,6,6,6); --MII 15
+ constant std_HUB_IBUF_DEPTH : hub_iobuf_config_t :=( 6,6,6,6, --MII 0
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6,
+ 6,6,6,6); --MII 15
constant std_IBUF_DEPTH : hub_channel_config_t := (6,6,6,6);
USE_ONEWIRE : integer range 0 to 2 := c_YES;
BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF";
--media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 12;
+ MII_NUMBER : integer range 1 to c_MAX_MII_PER_HUB := 12;
MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
MII_IS_UPLINK : hub_mii_config_t := (others => c_YES);
MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_REGS : out std_logic_vector (16*32-1 downto 0); --Status of custom STAT regs
STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
IOBUF_STAT_INIT_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
IOBUF_STAT_REPLY_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
CLK_EN : in std_logic;\r
\r
--TrbNet connect\r
- APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SHORT_TRANSFER_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DTYPE_OUT : out std_logic_vector (4*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_ERROR_PATTERN_OUT : out std_logic_vector (32*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEND_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_TYP_IN : in std_logic_vector (3*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_DATAREADY_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_READ_OUT : out std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_RUN_IN : in std_logic_vector (2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_SEQNR_IN : in std_logic_vector (8*2**(c_MUX_WIDTH)-1 downto 0);\r
- APL_FIFO_COUNT_IN : in std_logic_vector (11*2**(c_MUX_WIDTH)-1 downto 0);\r
+ APL_DATA_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_OUT : out std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_READ_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SHORT_TRANSFER_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_DTYPE_OUT : out std_logic_vector (3*4-1 downto 0);\r
+ APL_ERROR_PATTERN_OUT : out std_logic_vector (32*3-1 downto 0);\r
+ APL_SEND_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_TARGET_ADDRESS_OUT : out std_logic_vector (16*3-1 downto 0);\r
+ APL_DATA_IN : in std_logic_vector (16*3-1 downto 0);\r
+ APL_PACKET_NUM_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_TYP_IN : in std_logic_vector (3*3-1 downto 0);\r
+ APL_DATAREADY_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_READ_OUT : out std_logic_vector (3-1 downto 0);\r
+ APL_RUN_IN : in std_logic_vector (3-1 downto 0);\r
+ APL_SEQNR_IN : in std_logic_vector (8*3-1 downto 0);\r
+ APL_FIFO_COUNT_IN : in std_logic_vector (11*3-1 downto 0);\r
\r
--Internal Data Bus\r
BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
BUS_CYC_IN : in std_logic;\r
BUS_STB_IN : in std_logic;\r
BUS_LOCK_IN : in std_logic;\r
- -- BUS_CTI_IN : in std_logic_vector(2 downto 0);\r
BUS_ACK_OUT : out std_logic;\r
\r
EXT_TRIGGER_INFO : out std_logic_vector(15 downto 0);\r
\r
component trb_net_bridge_pcie_endpoint is\r
generic(\r
- USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);\r
- AUTO_ANSWER_INCOMING_REQUESTS : channel_config_t := (c_NO,c_NO,c_NO,c_NO)\r
+ USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES)\r
);\r
port(\r
RESET : in std_logic;\r
BUS_CYC_IN : in std_logic;\r
BUS_STB_IN : in std_logic;\r
BUS_LOCK_IN : in std_logic;\r
--- BUS_CTI_IN : in std_logic_vector(2 downto 0);\r
BUS_ACK_OUT : out std_logic;\r
\r
MED_DATAREADY_IN : in STD_LOGIC;\r
end component;\r
\r
\r
+component trb_net_bridge_pcie_endpoint_hub is\r
+ generic(\r
+ NUM_LINKS : integer range 1 to 4 := 2;\r
+ COMPILE_TIME : std_logic_vector(31 downto 0) := (others => '0')\r
+ );\r
+ port(\r
+ RESET : in std_logic;\r
+ CLK : in std_logic;\r
+ CLK_125_IN : in std_logic;\r
+\r
+ BUS_ADDR_IN : in std_logic_vector(31 downto 0);\r
+ BUS_WDAT_IN : in std_logic_vector(31 downto 0);\r
+ BUS_RDAT_OUT : out std_logic_vector(31 downto 0);\r
+ BUS_SEL_IN : in std_logic_vector(3 downto 0);\r
+ BUS_WE_IN : in std_logic;\r
+ BUS_CYC_IN : in std_logic;\r
+ BUS_STB_IN : in std_logic;\r
+ BUS_LOCK_IN : in std_logic;\r
+ BUS_ACK_OUT : out std_logic;\r
+\r
+ SPI_CLK_OUT : out std_logic;\r
+ SPI_D_OUT : out std_logic;\r
+ SPI_D_IN : in std_logic;\r
+ SPI_CE_OUT : out std_logic;\r
+\r
+ MED_DATAREADY_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+\r
+ MED_DATAREADY_OUT : out std_logic_vector (NUM_LINKS-1 downto 0);\r
+ MED_DATA_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_PACKET_NUM_OUT : out std_logic_vector (3*NUM_LINKS-1 downto 0);\r
+ MED_READ_IN : in std_logic_vector (NUM_LINKS-1 downto 0);\r
+\r
+ MED_STAT_OP_IN : in std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+ MED_CTRL_OP_OUT : out std_logic_vector (16*NUM_LINKS-1 downto 0);\r
+\r
+ REQUESTOR_ID_IN : in std_logic_vector(15 downto 0);\r
+ TX_ST_OUT : out std_logic; --tx first word\r
+ TX_END_OUT : out std_logic; --tx last word\r
+ TX_DWEN_OUT : out std_logic; --tx use only upper 32 bit\r
+ TX_DATA_OUT : out std_logic_vector(63 downto 0); --tx data out\r
+ TX_REQ_OUT : out std_logic; --tx request out\r
+ TX_RDY_IN : in std_logic; --tx arbiter can read\r
+ TX_VAL_IN : in std_logic; --tx data is valid\r
+ TX_CA_PH_IN : in std_logic_vector(8 downto 0); --header credit for write\r
+ TX_CA_PD_IN : in std_logic_vector(12 downto 0); --data credits in 32 bit words\r
+ TX_CA_NPH_IN : in std_logic_vector(8 downto 0); --header credit for read\r
+\r
+ RX_CR_CPLH_OUT : out std_logic;\r
+ RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0);\r
+ UNEXP_CMPL_OUT : out std_logic;\r
+ RX_ST_IN : in std_logic;\r
+ RX_END_IN : in std_logic;\r
+ RX_DWEN_IN : in std_logic;\r
+ RX_DATA_IN : in std_logic_vector(63 downto 0);\r
+\r
+ PROGRMN_OUT : out std_logic;\r
+ SEND_RESET_OUT : out std_logic;\r
+ DEBUG_OUT : out std_logic_vector (31 downto 0)\r
+ );\r
+end component;\r
+\r
component trb_net_CRC is\r
port(\r
CLK : in std_logic;\r
jspc29 / trbnet.git / commitdiff