CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE
CLK_CORE_PCLK : in std_logic; --Main Oscillator
CLK_EXT_PLL_LEFT : in std_logic; --External Clock
- --CLK_SUPPL_PLL_LEFT : in std_logic; --not used
- --CLK_SUPPL_PLL_RIGHT : in std_logic; --not used
- --CLK_CORE_PLL_LEFT : in std_logic; --not used
- --CLK_CORE_PLL_RIGHT : in std_logic; --not used
- --CLK_EXT_PCLK : in std_logic; --not used
- --CLK_EXT_PLL_RIGHT : in std_logic; --not used
+
TRIG_LEFT : in std_logic; --Trigger Input
- --TRIG_PLL : in std_logic; --not used
- --TRIG_RIGHT : in std_logic; --not used
--Backplane, all lines
- BACK_GPIO : inout std_logic_vector(15 downto 0);
- BACK_LVDS : inout std_logic_vector(1 downto 0);
- BACK_3V3 : inout std_logic_vector(3 downto 0);
+-- BACK_GPIO : inout std_logic_vector(15 downto 0);
+-- BACK_LVDS : inout std_logic_vector(1 downto 0);
+-- BACK_3V3 : inout std_logic_vector(3 downto 0);
--Backplane for slaves on trbv3scbp1
--- BACK_GPIO : inout std_logic_vector(3 downto 0);
+ BACK_GPIO : inout std_logic_vector(3 downto 0);
--AddOn Connector - 32 Pin AddOn
- INP : in std_logic_vector(31 downto 0);
- DAC_IN_SDI : in std_logic;
- DAC_OUT_SCK : out std_logic;
- DAC_OUT_CS : out std_logic;
- DAC_OUT_SDO : out std_logic;
+ INP : in std_logic_vector(63 downto 0);
+ DAC_OUT_SDO : out std_logic_vector(4 downto 1);
+ DAC_OUT_SCK : out std_logic_vector(4 downto 1);
+ DAC_OUT_CS : out std_logic_vector(4 downto 1);
+ DAC_IN_SDI : in std_logic_vector(4 downto 1);
+
RES : out std_logic;
--KEL Connector
signal time_counter : unsigned(31 downto 0) := (others => '0');
signal led : std_logic_vector(1 downto 0);
signal debug_clock_reset : std_logic_vector(31 downto 0);
+ signal inputs : std_logic_vector(51 downto 0);
--Media Interface
signal med2int : med2int_array_t(0 to 0);
ADC_MISO => ADC_DOUT,
ADC_CLK => ADC_CLK,
--Trigger & Monitor
--- MONITOR_INPUTS(39 downto 0) => KEL(40 downto 1),
--- MONITOR_INPUTS(43 downto 40) => trig_gen_out_i,
--- TRIG_GEN_INPUTS => KEL(40 downto 1),
- MONITOR_INPUTS(31 downto 0) => INP(31 downto 0),
- MONITOR_INPUTS(35 downto 32) => trig_gen_out_i,
- TRIG_GEN_INPUTS => INP(31 downto 0),
+ MONITOR_INPUTS => inputs(51 downto 0),
+ TRIG_GEN_INPUTS => inputs(47 downto 0),
TRIG_GEN_OUTPUTS => trig_gen_out_i,
--SED
SED_ERROR_OUT => sed_error_i,
DEBUG_OUT => open
);
+
+
---------------------------------------------------------------------------
-- Switches
---------------------------------------------------------------------------
BACK_GPIO(1 downto 0) <= (others => 'Z');
BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2);
- BACK_GPIO(15 downto 4) <= (others => 'Z');
BACK_LVDS <= (others => '0');
BACK_3V3 <= (others => 'Z');
- spi_miso(0) <= DAC_IN_SDI;
- DAC_OUT_SCK <= spi_clk(0);
- DAC_OUT_CS <= spi_cs(0);
- DAC_OUT_SDO <= spi_mosi(0);
+
+gen_32pin : if PINOUT = 0 generate
+ inputs(31 downto 0) <= INP(31 downto 0);
+ inputs(47 downto 32) <= (others => '0');
+ inputs(51 downto 48) <= trig_gen_out_i;
+
+ spi_miso(0) <= DAC_IN_SDI(1);
+ DAC_OUT_SCK(1) <= spi_clk(0);
+ DAC_OUT_CS(1) <= spi_cs(0);
+ DAC_OUT_SDO(1) <= spi_mosi(0);
+
+end generate;
+gen_4conn : if PINOUT = 1 generate
+ inputs(47 downto 0) <= INP(47 downto 0);
+ inputs(51 downto 48) <= trig_gen_out_i;
+
+ spi_miso(3 downto 0) <= DAC_IN_SDI(4 downto 1);
+ DAC_OUT_SCK(4 downto 1) <= spi_clk(3 downto 0);
+ DAC_OUT_CS(4 downto 1) <= spi_cs(3 downto 0);
+ DAC_OUT_SDO(4 downto 1) <= spi_mosi(3 downto 0);
+
+end generate;
+
+
---------------------------------------------------------------------------
-- LCD Data to display
-- For single edge measurements
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
- hit_in_i(32 downto 1) <= INP(31 downto 0);
+ hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= inputs(NUM_TDC_CHANNELS-2 downto 0);
end generate;
-- For ToT Measurements
gen_double : if DOUBLE_EDGE_TYPE = 2 generate
- Gen_Hit_In_Signals : for i in 0 to 31 generate
- hit_in_i(i*2+1) <= INP(i);
- hit_in_i(i*2+2) <= not INP(i);
+ Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate
+ hit_in_i(i*2+1) <= inputs(i);
+ hit_in_i(i*2+2) <= not inputs(i);
end generate Gen_Hit_In_Signals;
end generate;
--- -- For single edge measurements
--- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
--- hit_in_i(40 downto 1) <= KEL(40 downto 1);
--- end generate;
---
--- -- For ToT Measurements
--- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
--- Gen_Hit_In_Signals : for i in 1 to 20 generate
--- hit_in_i(i*2-1) <= KEL(i);
--- hit_in_i(i*2) <= not KEL(i);
--- end generate Gen_Hit_In_Signals;
--- end generate;
-
+
end architecture;
jspc29 / trb3sc.git / commitdiff